US7349253B2 - Memory device and method for testing memory devices with repairable redundancy - Google Patents
Memory device and method for testing memory devices with repairable redundancy Download PDFInfo
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- US7349253B2 US7349253B2 US11/343,357 US34335706A US7349253B2 US 7349253 B2 US7349253 B2 US 7349253B2 US 34335706 A US34335706 A US 34335706A US 7349253 B2 US7349253 B2 US 7349253B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
Definitions
- the invention relates to a method for testing the operability of memory devices, in particular of DRAM semiconductor devices, making use of repairable redundancy.
- the invention further relates to a memory device with repairable redundancy for using the inventive method for testing memory devices.
- An integrated memory device comprises a plurality of memory cells that are usually arranged in a matrix of electroconductive supply lines.
- the matrix of electroconductive supply lines is composed of column and row lines which are also referred to as word lines (WL) and bit lines (BL).
- the memory cells are each positioned at the crosspoints of the electroconductive supply lines that are connected with the memory cell via a top and a bottom electrode. To perform a change of the information content in a particular memory cell at the addressed crosspoint, or to recall the content of the memory cell, the corresponding word and bit lines are selected and impacted either with a write current or with a read current.
- RAM Random Access Memory
- a RAM memory device is a memory with optional access, i.e., data can be stored under a particular address and can be read out again under this address later.
- a particular kind of RAM semiconductor memories are DRAMs (Dynamic Random Access Memory) which comprise in general only one single, correspondingly controlled capacitive element per memory cell, e.g., a trench capacitor, with the capacity of which one bit each can be stored as charge.
- semiconductor memory device primarily designates semiconductor memory devices such as functional memory devices (PLAs, PALs, etc.) and table memory devices such as ROM or RAM semiconductor devices, e.g., SRAMs and DRAMs, but also logic semiconductor devices, i.e., integrated (analog or digital) computing circuits.
- PDAs functional memory devices
- PALs PALs
- table memory devices such as ROM or RAM semiconductor devices, e.g., SRAMs and DRAMs, but also logic semiconductor devices, i.e., integrated (analog or digital) computing circuits.
- integrated circuits are established by numerous processes during the manufacturing, which are, for instance, in the case of logic semiconductor devices, capable of performing logic functions, i.e., of processing data in correspondence with predetermined operations, in particular pursuant to a programmed sequence.
- a semiconductor memory device e.g., a RAM semiconductor memory chip
- a plurality of memory cells are integrated, in which, by selective applying of a voltage, electric charge can be stored or read out as an information unit (bit).
- semiconductor devices are, in the course of the manufacturing process, in the semi-finished and/or finished state, prior to the incorporation in appropriate semiconductor modules, subject to extensive tests checking their functioning.
- module tests further tests may be performed after the incorporation of the semiconductor devices in the semiconductor modules (so-called module tests), so as to check the interaction of the individual semiconductor devices in the semiconductor module.
- tests for analyzing defects may be required if a semiconductor module shows malfunctions after the assembly or during operation.
- a so-called wafer a thin disc manufactured of monocrystalline silicon
- the wafer is subject to a plurality of working processes, e.g., coating, exposure, etching, diffusion and implantation processes.
- the semiconductor devices are individualized by the wafer being sawn apart or scratched and broken, so that the individual semiconductor devices or chips are then available for further processing.
- the semiconductor devices are subject to test processes for checking their functioning at one or a plurality of (further) test stations.
- the devices After the sawing apart (or the scratching and breaking, respectively) of the wafer, the devices—which are then available individually—are molded in a plastics mass and may subsequently be subject to further test processes at one or a plurality of test stations.
- a silicon substrate is consequently manufactured first of all in so-called front end processes (FE processes), the silicon substrate comprising the desired memory cells or integrated circuits, respectively.
- FE processes front end processes
- the electrical connections (e.g., contact pads) of the chips are connected (e.g., bonded) via electrical connecting lines (bond wires) with a contact frame so as to enable the electrical contacting of the silicon substrate with the periphery via external contacts (e.g., pins).
- the chips connected with the contact frame are, as a rule, molded in a plastics package along with the contact frame, so that a packed semiconductor device is generated.
- a plurality of such semiconductor devices may then be composed to form a semiconductor module.
- a number of semiconductor devices is composed to form a semiconductor module even prior to the molding in separate plastics packages and is molded together in a common package subsequently only.
- BE processes back end processes
- test steps are consequently performed in the manufacturing stages of the front end (FE), the back end (BE), during burn-in (BI), and at semiconductor memory modules.
- Some of these test methods serve to repair a memory device that is not fully operable, or to check it in conformity with specifications at a certain rate action.
- FE front end
- BE back end
- BI burn-in
- Some of these test methods serve to repair a memory device that is not fully operable, or to check it in conformity with specifications at a certain rate action.
- the memory device or memory chips on the wafer are tested exactly parallel and with a low access rate. In so doing, it is determined, in particular with DRAM memory devices, which of the memory cells has a sufficient margin or rate action, respectively, with respect to the retention requirements, and which memory cells may have to and can be replaced by redundant cells. If all and any defective memory cells can be masked out by an exchange with redundant word lines (WL) or bit lines (BL), a repairable memory device (repairable chip) is available.
- WL redundant word lines
- BL bit lines
- the test process in the FE manufacturing stage comprises the testing in the so-called pre-fuse and post-fuse test step, in which defective column select lines (CSL) and word lines (WL) are detected before or after the repair is performed by means of fusing.
- the test process is, as a rule, performed at least at a particular test temperature, preferably at a high temperature HT, and optionally additionally also at a low temperature LT.
- the column select lines are control lines leading to a group of particular sense amplifiers (SA) that are selected during a row selection by means of the y-address of a memory cell.
- SA sense amplifiers
- RCSL redundant column select lines
- the redundancy information of each memory device or chip on the wafer collected in the pre-fuse test are subsequently burnt in irreversibly in a fuse process (by e-fuse or laser fuse), and the wafer is tested with respect to a successively performed repair.
- both repaired and non-repairable chips are available on the wafer.
- Non-repairable chips are chips whose available redundancy is not sufficient to produce a fully operable and specification-consistent memory device with a defined memory size.
- the chips or memory devices that have been tested and found to be fully operable are usually picked from the wafer and supplied to the back end manufacturing stage so as to mold them in a package.
- the packed semiconductor devices or memory chips are then stressed, burnt in and tested at high voltages and temperatures in a so-called burn-in process. Subsequently, the semiconductor devices are tested for their rate performance in the BE test at low and at high temperature (LT and HT).
- the memory devices that have been found to be operable in the BE test (BE-pass-parts) are provided for the construction of memory modules, wherein between 4 and 36 memory devices per module are used and tested again to sort out defective modules being the result of soldering.
- a defective module may, for instance, be produced by soldering degradation, which is caused by a reduction in quality due to the temperature-induced ageing of the chip during soldering.
- Each test step is, as a rule, based on a so-called test severity, i.e. a specified functionality rate action exceeding the chip specification, for which any electric circuit or any memory cell field (array) of the DRAM memory device is examined with regard to particular causes of defect. Due to the adjustment and guaranty of this test severity, each test step entails a certain loss of yield which can continuously be optimized in the course of series-production readiness by means of test and process optimization. Although exclusively pass-parts are used in the last manufacturing step of the module construction, hard (retention) single cell defects occur due to soldering degradation, which may make the entire module fail in particular in the case of high temperature operation. Here it is, as a rule, the matter of few, frequently only one single, defective memory cell in the memory device.
- the object of the so-called single bit repair is to eliminate such defects of single memory cells (single cell defects) in the memory device, which have occurred after the repair performed in the front end manufacturing stage. This is, for instance, done by providing a supplementary repair possibility on the component or module level of the memory device. It is presupposed that the single cells of the semiconductor memory which are provided for repair are adapted to be integrated as easily as possible and have already been subject to the necessary burn-in stress or do not require same. The (redundant) single cells of the semiconductor memory which are provided for repair must further be tested with respect to all test requirements (FE/BI/BE) in correspondence with the memory cells to be exchanged, or must already fulfill or be able to guarantee same.
- FE/BI/BE all test requirements
- a known possibility of repairing defective memory cells consists in providing DRAM memory cells for redundancy so as to use them in the case of a single bit repair and to thus increase the yield e.g. on the module level.
- This proceeding entails the problems that redundant elements for the repair of single memory cell defects (single bit repair or single bit redundancy, SBR) or of a bit group still have to be available for a single access.
- the knowledge of the test quality of the still available redundancy alone at the time of FE fusing is not sufficient to use the redundancy memory cells in later test steps, for instance, after the BI or the BE test.
- a replacement of defective memory cells by memory cells that have not been tested sufficiently severely would mean a generation of semiconductor memory devices or modules with a lower quality standard vis-à-vis non-repaired memory devices.
- the use of a non-tested redundancy with lower test severity would involve a potential failure risk.
- An additional testing of the repaired memory devices in the BI or the BE is not desirable for cost reasons.
- the quality of free redundancies has to be known at any time of a test sequence without them having to be established anew later or having to be tested separately, since this would increase the test time. In the case of the BI, this could also result in an overstressing of the memory areas that have already been stressed.
- the redundancy elements must be accessible or addressable, respectively, so that they are also examinable.
- the redundancy memory cells must be tested or stressed along with the regular memory cells and possibly also be deactivated if a defect in the redundancy is detected.
- the present invention provides a memory device and method for testing memory devices with repairable redundancy.
- the method for testing the operability of a memory device in particular a DRAM semiconductor memory device, including a control and a regular memory area having a number of regular memory cells, as well as a redundant memory area having a number of redundant memory cells, wherein the redundant memory cells serve to replace one or a plurality of defective memory cells from the regular memory areas includes coupling at least one regular memory cell from the regular memory area with at least one redundant memory cell from the redundant memory area via a coupling circuit, parallel or even loading of the regular memory area including the at least one regular memory cell along with the redundant memory area including the at least one redundant memory cell, e.g., by temperature, stress, and/or tension loads, parallel testing of the operability of the regular memory area including the at least one regular memory cell along with the redundant memory area including the at least one redundant memory cell, evaluation and case distinction on the basis of the result of the testing for operability, and deactivating of defective memory cells.
- FIG. 1 a schematic representation of the structure of a semiconductor memory device with a plurality of arrays or memory cell fields, respectively, in accordance with a preferred embodiment of the present invention.
- FIG. 2 a schematic representation of the structure of a segment of the semiconductor memory device illustrated in FIG. 1 with a control means and a coupling circuit or sticky-pass/fail-XOR circuit, respectively, for testing the function of a semiconductor memory device according to a preferred embodiment of the present invention.
- FIG. 3 a schematic representation of the structure of a sticky-pass/fail XOR circuit in detail for testing the function of a semiconductor memory device according to a preferred embodiment of the present invention.
- FIG. 4 a table in which the logic results of the sticky-pass/fail-XOR circuit illustrated in FIG. 3 are represented.
- the present invention provides in tested and repaired semiconductor memory devices, a so-called redundancy storage space for the repair of defective memory capacity of the semiconductor memory device, wherein the redundancy storage space can be used for repair even in the last memory examination process and has a full test severity and fulfils any requirements of reliability for the repair of qualitatively high-grade memory devices.
- the present invention provides a redundancy concept in which single defective memory cells are repaired by means of column redundancy having experienced the necessary test severity and the required memory cell stress and thus being adapted to be used for the defective memory cells without any quality loss for the semiconductor memory device.
- the technical problem of providing the necessary redundancy with the required quality is consequently solved within the redundancy analysis in the pre-fuse, i.e. during a test process or a test sequence in the manufacturing stage of the front end FE in which defective column select lines (CSL) and word lines (WL) are detected, before the repair is performed by fusing.
- a selected redundancy and a regular memory row or memory column are repaired with the necessary priority to SBR redundancy, and these are jointly coupled to one another for the subsequent test processes, wherein the coupling exists for test purposes only. This may preferably be provided independently for each memory segment of the semiconductor memory device.
- the error addresses of the defective area stored during testing can, at the end of the test sequence, again be burnt in the semiconductor memory device to be repaired, e.g., by e-fuse, laser fuse, or soft fuse, whereby a reprogramming of the address supply line is achieved.
- the repair is preferably performed irreversibly with the above-mentioned redundancy being used which has also been tested due to the coupling to a regular memory device. This requires that the corresponding redundancy has not been used by that point in time and is additionally repairable, i.e., has been evaluated as “pass” during the test, and is preferably available independently for each memory segment of the semiconductor memory device.
- a redundancy that is available in segments has the advantages that a potential multiple repair of defective memory cells is possibly by the use of a plurality of independent redundancies. Furthermore, it can be decided during pre-fuse already whether the providing of a SBR repair is possible for each segment individually due to the redundancy use calculated, which may possibly be postponed due to a consideration of the yield in the FE and in the BE manufacturing field and is introduced at a later time of series-production readiness only.
- FIG. 1 illustrates a schematic representation of the structure of a semiconductor memory device 1 according to one embodiment of the present invention.
- the individual memory cells of semiconductor memory devices 1 are arranged side by side in a plurality of rows and columns in a rectangular or square matrix or a rectangular or square memory cell field or memory cell array 2 , respectively.
- a plurality of, for instance four, individual arrays, so-called memory banks 2 may be provided in a RAM memory device or RAM memory chip (multi-bank chip) instead of one single array 2 .
- the memory cells in the array extend in x-direction and in y-direction, wherein the x-direction constitutes the word line area, i.e. that a particular memory cell within the array can be specified in x-direction by the word line address, and the y-direction constitutes the bit line area, i.e. that a particular memory cell within the array can be specified in y-direction by the bit line or column address.
- the x-direction constitutes the word line area, i.e. that a particular memory cell within the array can be specified in x-direction by the word line address
- the y-direction constitutes the bit line area, i.e. that a particular memory cell within the array can be specified in y-direction by the bit line or column address.
- a word line activate instruction activate instruction
- a corresponding word line WL that is assigned to a particular individual array (memory bank) 2 and that is defined by the row address is first of all activated. Subsequently, it is initiated by means of an appropriate read or write instruction that the data specified by the corresponding column address are output or read in, respectively.
- Each memory cell is equipped with a sense amplifier 8 that is designed as a so-called differential amplifier. The sense amplifier 8 senses the data content of the corresponding memory cell during a read access in that it senses the voltage difference between the two bit lines connected to the sense amplifier 8 , amplifies same, keeps them ready and transmits them to the data bus in the case of an appropriate CSL selection or y-addressing.
- control means (not illustrated) which controls the signal processes in the semiconductor memory device.
- Each memory cell field or memory cell array 2 (memory bank) comprises a plurality of segments 3 in each of which a number of, for instance, 512 word lines is accommodated, which each control e.g. 2048 bit line pairs, wherein e.g. 512 memory cells are assigned to each bit line pair.
- each memory cell is connected with a sense amplifier arranged one below the other on the semiconductor substrate in a line 8 next to the memory cells.
- Each segment 3 is subdivided into two areas 4 and 5 of memory cells, wherein the area 4 comprises the regular memory cells and the area 5 the redundant memory cells.
- the redundant memory cells in the area 5 serve for the exchange or replacement, respectively, of regular memory cells from the area 4 which have been detected as defective (fail) during one of the above-mentioned function tests.
- FIG. 2 illustrates a schematic representation of the structure of a segment 3 of the memory device illustrated in FIG. 1 .
- the segment 3 comprises a number of memory cells which are each connected with a sense amplifier arranged one below the other in a line 8 next to the memory cells.
- the semiconductor memory device 1 is further equipped with control means to control the signal traffic to and from the individual memory cells in each segment 3 .
- the control means comprises, for instance, a multiplexer 9 connected with the respective sense amplifiers 8 and serving to select the data contents of the sense amplifiers 8 .
- the multiplexer 9 is connected with a driver 10 which selects, by means of the y-address of an access instruction, which bits are to be read or written, and which further establishes the connection to the data bus (not illustrated).
- the driver transmits the data or signals supplied by the multiplexer 9 from the corresponding memory cell to a tester (not illustrated).
- the tester finally determines by means of the signals supplied by the driver 10 during testing whether a memory cell in the area 4 of the segment 3 is operable (pass) or not operable (fail).
- the segment 3 is subdivided into the two areas 4 and 5 , wherein the area 4 comprises regular memory cells and the area 5 redundant memory cells (SBR redundancies).
- the area 4 comprises regular memory cells and the area 5 redundant memory cells (SBR redundancies).
- SBR redundancies redundant memory cells
- the two adjacent memory cells 6 and 7 are connected with each other via their corresponding sense amplifiers 8 and a coupling circuit 12 .
- This coupling circuit 12 preferably comprises three marker bits 13 , 14 , and 15 which contain information about the state of the memory cells 6 and 7 .
- the data contents of the marker bits 13 , 14 , and 15 can be read, and thus the information about the state or the usability of the memory cells 6 and 7 can be taken.
- the marker bit 13 may, for instance, indicate a defect of one of the two memory cells 6 or 7 which has occurred within a test step (pass/fail marker); the marker bit 14 may, for instance, indicate that the memory cell 7 is already used as a redundant memory cell for a regular memory cell from the area 4 of the segment 3 (used marker); and the marker bit 15 indicates, for instance, whether the redundant memory cells in the area 5 of the segment 3 are operable or not (pass/fail marker). While the marker bit 13 can be re-written, the marker bits 14 and 15 can each be written once only. This way it is ensured that a defect that has once been detected during a test step, or the use of the redundant memory cells, respectively, is noted permanently. Thus, the information of whether the corresponding segment 3 of the semiconductor memory device 1 is ready for use, is repaired, or is irrepairable is also stored permanently in the marker bits 14 and 15 .
- the test result or the information about the usability with respect to the memory cells 6 and 7 which are connected with each other by the coupling circuit 12 is stored in the marker bits 13 , 14 , and 15 . This information can be transmitted to the multiplexer 9 via a further control element 11 for further utilization.
- the coupling circuit 12 and the control element 11 may transmit the corresponding address of the redundant memory cell from the area 5 to the multiplexer 9 , so that the control of the semiconductor memory device uses the operable memory cell from the redundancy area 5 of the segment 3 instead of the defective memory cell from the regular area 4 .
- Such a process is a so-called single bit repair (SBR) or single bit redundancy.
- SBR single bit repair
- the SBR process or the SBR device serves to repair only one defective memory cell or bit group for one single write or read access.
- FIG. 2 consequently shows the connection of the column select lines (CSL) and of the sense amplifiers 8 contained therein of two respective word lines in different segments 3 or of two column select lines (CSL) in one respective segment by a coupling circuit 12 .
- the coupling circuit 12 is designed as a so-called sticky-pass/fail-XOR circuit which connects the equivalent sense amplifiers 8 of at least one regular memory cell and the sense amplifier 8 of at least one redundant memory cell with one another.
- the coupling circuit 12 thus enables the joint writing and simultaneous evaluating of the redundancy 7 and of the regular memory area 4 .
- the coupling circuit 12 may, for instance, comprise an e-fuse memory serving for the segment-fine storage of the SBR use of the redundant area 5 .
- An e-fuse memory may also be used for the segment-fine storage of the functionality of the used or non-used redundant area 5 .
- CSL column select lines
- SA sense amplifiers
- RCSL redundant column select lines
- test result is “fail” and the fail address is known, it is optionally determined at the end of the test by test mode that the corresponding memory device can be repaired. This, however, requires that the SBR redundancy 7 is pass or operable, respectively.
- the difference to the afore-described case consists in that the regular memory area 6 coupled to the SBR memory has been determined as pass or operable, respectively, but the regular cell field 4 has been determined as fail or non-operable, respectively.
- the error address may then be transmitted to a SBR address memory for subsequent repair.
- the repair merely takes place in the addressed memory segment itself (intrablock redundancy) and is performed only if the redundancy has been determined to be useable, i.e., if the corresponding marker bit 15 and the used marker 14 have been set correspondingly.
- 5 Pass Fail Fail In this case it is clear that the SBR-CSL memory has no more repair potential and that at least one defect exists in the regular cell field 4 which is not coupled with the defect in the SBR-CSL memory area 7.
- 6 Fail Fail Pass The semiconductor device is irrepairable since there are at least two defects that cannot be repaired although the SBR memory area 7 is useable.
- 7 Fail Pass Fail The semiconductor device is irrepairable since the SBR memory area 7 has been detected as defective and is masked out.
- 8 Fail Fail Fail Fail The semiconductor device is irrepairable since there are at least two defects that cannot be repaired; the SBR memory 7 is not useable, either.
- the above-explained features of the inventive method may, for instance, be realized by the above-mentioned sticky-pass/fail-XOR circuit as a coupling circuit 12 , as it is illustrated in FIG. 4 .
- a sticky-pass/fail-XOR circuit 12 has the advantage of a simple and space-saving structure and is preferably integrated on the substrate of the semiconductor device 1 .
- the sense amplifiers 8 of at least one regular memory cell 6 from the regular memory area 4 of the memory segment 3 are coupled with at least one redundant memory cell 7 from the redundant memory area 5 of the memory segment 3 in that the signals from the sense amplifiers 8 of the corresponding memory cells 6 , 7 are supplied to the sticky-pass/fail-XOR circuit 12 via the inputs a and b.
- the procedure of testing substantially consists of the writing of a known data content into the memory cell(s) to be tested and the subsequent reading of the data content out of the corresponding memory cells(s).
- the memory cell(s) is (are) detected as operable if the data content stored in the memory cell during writing is found again during reading. If the written data deviate from the data content read, the memory cell is not operable.
- the memory cells 6 , 7 are preferably written in parallel with the same data content via the connections a and b for testing. During the subsequent reading, the data contents from the memory cells 6 , 7 are called separately into the XOR circuit via the connections a and b.
- the coupling of the two memory cells 6 , 7 consequently consists of the joint writing and the separate reading of the data contents via the XOR circuit of the coupling circuit 12 .
- the signal at the input a originates, for instance, from the sense amplifier 8 of at least one regular memory cell 6 from the regular memory area 4 while the signal at the input b originates from the sense amplifier 8 of at least one redundant memory cell 7 from the redundant memory area 5 .
- the sticky-pass/fail-XOR circuit 12 comprises substantially a XOR circuit and an OR circuit, wherein the signals from the sense amplifiers 8 of the corresponding memory cells 6 , 7 are first of all fed into the XOR circuit via the inputs a and b and are compared with one another there. The result of this comparison is transmitted via the output of the XOR circuit to the input c of the OR circuit. If the result of the XOR circuit has generated a high voltage level or a logic “1”, respectively, this results also in a high voltage level or a logic “1”, respectively, at the output d of the OR circuit.
- FIG. 4 illustrates a table in which the logic results of the sticky-pass/fail-XOR circuit illustrated in FIG. 3 are represented.
- the result of the logic comparison of the signals from the sense amplifiers 8 of the coupled memory cells 6 , 7 by the sticky-pass/fail-XOR circuit 12 is recorded in the above-described marker bits 13 , 14 , and 15 by corresponding data contents, for instance, a logic “0” for “pass” and a logic “1” for “fail”.
- the sticky-pass/fail-XOR circuit 12 can consequently determine whether there is a difference in the values of the sense amplifiers 8 of the coupled memory cells 6 and 7 .
- the state of the coupled SBR area 7 can then be gathered.
- the memory device 1 is judged as fail or defective, so that the device is not processed in a non-repaired state, anyway. If a repair is to be performed even without knowledge of the success of repair, a post-test and an explicit post-test of the SBR memory area are necessary in both cases to find out definitely whether the repaired device is operable or not.
- a first instant post-test without immediate SBR performance prior to the second instant post-test with immediate SBR performance may possibly clarify in the case of the confirmably defective memory devices whether the device defect ascertained only is an incidental contact defect. This way, it may, for instance, be defined that exclusively those semiconductor memory devices are subject to a SBR repair which have at least or exactly twice been judged as fail or defective in the post-test.
- a redundancy that has been provided in the course of the test process can be tested in parallel in the background during the testing of the regular memory cells, and be deactivated in the case of a defect. Due to the plurality of SBR redundancy that has been distributed segment-wise there is, even if a defect is detected only in one CSL, the possibility that the remaining free redundancies are used in the remaining segments as far as they have been reserved and are still “pass”.
- the error address can, by means of a separate tester that has the possibility of logging the error address, be transmitted to the memory device by means of a test mode after the testing.
- a fuse command replaces at least one address in the segment that has been identified as defective, without knowing the functionality of the SBR redundancy.
- the error address may also be stored chip-internally in a self test, so that a re-writing of the error address is omitted and a chip-individual repair is enabled without expensive test methods and testers.
- This is of advantage in particular for modules with components that are operated in parallel, in particular if the memory components of the module are shielded off the tester by a defined, stringent, and thus inflexible, interface.
- the repair step is performed similarly as in the case of a memory cell repair (SBR) by means of SRAM memory cells.
- SBR memory cell repair
- the difference of the CSL-SBR to the SBR with a SRAM consists in that reliable SRAM cells are provided in the SRAM concept, which neither have to be stressed nor tested, and which can be replaced once.
- the repair is performed chip-individually with a defined amount of SRAM cells.
- the advantages of the SRAM-SBR method consists in that the SRAM memory need not be tested and stressed.
- the method for repairing defective memory cells by means of SRAM memory cells is both quicker and more reliable and does not require any specific test logic for simultaneous stressing and testing.
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Abstract
Description
-
- The providing of a redundancy that can be used at any time and whose quality with respect to the stress and the test severity experienced grows within the usual production processes of manufacturing and examination of the semiconductor memory device, without causing any additional test effort.
- The local linking of selected column select lines (CSL) and redundant column select lines (RCSL) or word lines (WL) and redundant word lines (RWL), respectively, for the parallel testing and stressing of the BL or WL redundancy by means of a so-called pass/fail evaluation circuit.
- The connecting of a pass/fail evaluation with the storing of the information about the repairability of the regular memory device or the redundant element, respectively, or the unique exchange of the two locally linked memory devices in the scope of a repair that can be performed at any time.
- The storing of the repairability and of the repair status is preferably enabled by means of a fuse process, e.g. e-fuse, so that the potential SBR capability can be updated at any time of testing even in the packed state of the memory device.
-
- In the pre-fuse, the repair of the
SBR memory area 5 and of the regular memory cell field adjacent to theSBR memory area 5 is, during the repair analysis, prioritized, accepting a yield reduction. When providing a CSL-based redundancy, a repair by means of word line redundancy is preferably performed. In the case of an impossible repair, the corresponding CSL-SBR redundancy of the corresponding area can be characterized as non-usable in the pre-fuse already. - The
SBR memory 5 is segment-individually not used if it can be provided as a non-used and operable post-fuse-SBR redundancy.
- In the pre-fuse, the repair of the
-
- By means of a particular test mode it is decided in advance whether the test/stress is performed with memory cells of the
SBR memory 5 that is coupled to a particular column select line (CSL). - The external pass/fail evaluation is performed in correspondence with the test result of the regular
memory cell field 4. The regularmemory cell field 4 then corresponds to a repaired memory cell field without SBR redundancy.
- By means of a particular test mode it is decided in advance whether the test/stress is performed with memory cells of the
-
- If the test result for the regular
memory cell field 4 is “pass”, it is evaluated at the end of a test with an activated parallel testing whether theredundancy 5 is still useable or operable, respectively. - If a
defective SBR redundancy 7 is detected in thearea 5, the defective SBR redundancy can be deactivated by test mode if it has not been deactivated yet. This process is permanently noted in themarker bit 15, so that thesemiconductor device 1 is characterized as irrepairable.
- If the test result for the regular
Regular, | |||||
repaired, | Regular | Redundant | |||
uncoupled | coupled | coupled | Importance and decision for | ||
| memory | 4 | |
|
|
1 | Pass | Pass | Pass | No decision for repair | |
necessary. SBR redundancy | |||||
has the necessary test | |||||
severity and need | |||||
not be deactivated. | |||||
2 | Pass | Pass | Fail | The test result of the | |
semiconductor device | |||||
is ,,pass”, but a defect was | |||||
detected by the comparison | |||||
of the coupled memory area. | |||||
Therefore, the SBR memory | |||||
area has to be | |||||
characterized as defective and | |||||
has to be masked for a SBR | |||||
repair, e.g. by a defect | |||||
marker = 1. | |||||
Regular, | ||||
repaired, | Regular | Redundant | ||
uncoupled | coupled | coupled | Importance and | |
Case | memory | |||
4 | |
|
for |
|
3 | Pass | Fail | Pass | SBR repair would be |
possible, but SBR-CSL | ||||
has repair potential. | ||||
Usually, this case cannot | ||||
be differentiated from | ||||
|
||||
process. | ||||
4 | Fail | Pass | Pass | The semiconductor |
device is detected as | ||||
defective, in the coupled | ||||
area no defect could be | ||||
found, however, since all | ||||
storages have been | ||||
performed jointly. The | ||||
redundancy can be used | ||||
as SBR. (Only the very | ||||
unlikely case that both in | ||||
the |
||||
the |
||||
same defect occurs with | ||||
the same x-address has | ||||
the same importance | ||||
here. With the | ||||
performance of the repair | ||||
and a subsequent post- | ||||
testing this case can, | ||||
however, be examined. | ||||
5 | Pass | Fail | Fail | In this case it is clear that |
the SBR-CSL memory | ||||
has no more repair | ||||
potential and that at least | ||||
one defect exists in the | ||||
|
||||
is not coupled with the | ||||
defect in the SBR- | ||||
memory area | ||||
7. | ||||
6 | Fail | Fail | Pass | The semiconductor |
device is irrepairable | ||||
since there are at least | ||||
two defects that cannot | ||||
be repaired although the | ||||
|
||||
useable. | ||||
7 | Fail | Pass | Fail | The semiconductor |
device is irrepairable | ||||
since the | ||||
area | ||||
7 has been detected | ||||
as defective and is | ||||
masked out. | ||||
8 | Fail | Fail | Fail | The semiconductor |
device is irrepairable | ||||
since there are at least | ||||
two defects that cannot | ||||
be repaired; the | ||||
memory | ||||
7 is not useable, | ||||
either. | ||||
-
- an SRAM memory has to be provided which cannot be used otherwise,
- the size of the SRAM memory cannot be adapted in the course of the series-production readiness, and
- the SRAM memory has a higher space requirement.
Claims (25)
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DE102005004379A DE102005004379B4 (en) | 2005-01-31 | 2005-01-31 | Memory device and method for testing memory devices with repairable redundancy |
DE102005004379.8 | 2005-01-31 |
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US20060198215A1 US20060198215A1 (en) | 2006-09-07 |
US7349253B2 true US7349253B2 (en) | 2008-03-25 |
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US11/343,357 Active 2026-09-04 US7349253B2 (en) | 2005-01-31 | 2006-01-31 | Memory device and method for testing memory devices with repairable redundancy |
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DE (1) | DE102005004379B4 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080225613A1 (en) * | 2005-08-16 | 2008-09-18 | Morteza Cyrus Afghahi | Memory row and column redundancy |
US20080259682A1 (en) * | 2005-01-14 | 2008-10-23 | Kazuyoshi Shiba | Semiconductor device |
US8839054B2 (en) | 2012-04-12 | 2014-09-16 | International Business Machines Corporation | Read only memory (ROM) with redundancy |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080270828A1 (en) * | 2007-04-27 | 2008-10-30 | Hermann Wienchol | Memory Redundancy Method and Apparatus |
US9146808B1 (en) * | 2013-01-24 | 2015-09-29 | Emulex Corporation | Soft error protection for content addressable memory |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5841709A (en) * | 1995-12-29 | 1998-11-24 | Stmicroelectronics, Inc. | Memory having and method for testing redundant memory cells |
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JP3537087B2 (en) * | 2000-09-29 | 2004-06-14 | Necエレクトロニクス株式会社 | Semiconductor device and method of inspecting semiconductor device |
US6661719B1 (en) * | 2002-07-11 | 2003-12-09 | Exrontechnology, Inc. | Wafer level burn-in for memory integrated circuit |
-
2005
- 2005-01-31 DE DE102005004379A patent/DE102005004379B4/en not_active Expired - Fee Related
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US5841709A (en) * | 1995-12-29 | 1998-11-24 | Stmicroelectronics, Inc. | Memory having and method for testing redundant memory cells |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080259682A1 (en) * | 2005-01-14 | 2008-10-23 | Kazuyoshi Shiba | Semiconductor device |
US7639541B2 (en) * | 2005-01-14 | 2009-12-29 | Renesas Technology Corp. | Semiconductor device |
US20080225613A1 (en) * | 2005-08-16 | 2008-09-18 | Morteza Cyrus Afghahi | Memory row and column redundancy |
US7738308B2 (en) * | 2005-08-16 | 2010-06-15 | Novelies, Llc | Memory row and column redundancy |
US8839054B2 (en) | 2012-04-12 | 2014-09-16 | International Business Machines Corporation | Read only memory (ROM) with redundancy |
US9460811B2 (en) | 2012-04-12 | 2016-10-04 | Globalfoundries Inc. | Read only memory (ROM) with redundancy |
Also Published As
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US20060198215A1 (en) | 2006-09-07 |
DE102005004379A1 (en) | 2006-08-10 |
DE102005004379B4 (en) | 2007-12-27 |
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