US7323910B2 - Circuit arrangement and method for producing a dual-rail signal - Google Patents

Circuit arrangement and method for producing a dual-rail signal Download PDF

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Publication number
US7323910B2
US7323910B2 US10/965,663 US96566304A US7323910B2 US 7323910 B2 US7323910 B2 US 7323910B2 US 96566304 A US96566304 A US 96566304A US 7323910 B2 US7323910 B2 US 7323910B2
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Prior art keywords
signal
switch
processing apparatus
circuit arrangement
signal processing
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US10/965,663
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US20050063478A1 (en
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Thomas Kunemund
Holger Sedlak
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1738—Controllable logic circuits using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]

Definitions

  • the present invention relates to a circuit arrangement and method for producing a dual-rail output signal.
  • Switching networks are normally designed microelectronically such that each bit of the information to be processed is physically represented by one, and only one, electrical node.
  • a configuration such as this is also referred to as “single-rail” circuit technology.
  • Switching networks such as these are, however, relatively uncertain with regard to so-called differential current profile analysis, which is used by unauthorized third parties when attempting to gain access to secret information.
  • Differential current profile analysis which is also referred to as differential power analysis—DPA —, is one of the most important methods, for example, for attacking smart cards for security purposes. This involves deliberate attacks on confidential information (passwords or cryptographic keys).
  • smart card current profiles which are measured by means of statistical methods, and/or their charge integrals calculated over one or more clock cycles, are evaluated, in which case—for a large number of program runs—it is possible to draw conclusions about the information to be protected from the correlation between the systematic data variation and the respective charge integral.
  • each bit within a data path or signal path is physically represented by one, and only one, electrical node k
  • precharge state also referred to just as precharge
  • a state sequence for the precharge state (1, 1) could thus appear as follows:
  • Circuit arrangements for producing a dual-rail signal are used, for example, in a data processing apparatus such as that shown in FIG. 1 .
  • This shows a data processing apparatus 3 which has an arithmetic and logic unit 2 (ALU).
  • An ALU such as this is provided for linking two input values to one another, for example by carrying out an addition process. Two input values a and b are thus linked to form an output value c.
  • a subtraction process can be carried out by supplying one of the two values that are to be linked in inverted form to the ALU, and by at the same time setting a carry bit at the carry-in input of the ALU.
  • the signal not (a) is required instead of the signal a.
  • the data processing apparatus 3 has preprocessing input circuits 1 , which are suitable for producing the function not (a).
  • the input circuit 1 produces an output signal Z, which is transmitted to the ALU.
  • the value “0” or the value “1” is required as the input value for the ALU, so that the input circuit 1 therefore also has to have the capability to provide these two values.
  • the required output functions z of the input circuit 1 are thus:
  • the function f in this case indicates that the input data a may be processed further, for example if the data a is scrambled and is first of all intended to be descrambled in order to allow further processing in the ALU.
  • the control signals S 0 , S 1 which are supplied to the input circuit 1 , determine which of these four functions should be implemented.
  • signal paths for the signals a, b, z and c which are shown by bold lines in FIG. 1
  • signal paths for signals aq, bq, zq and cq are shown by finer lines. These signal paths, or these signals, are present when this is a data processing apparatus 3 which is suitable for processing dual-rail signals.
  • the complementary signal is still always present in addition to the actual data signal, provided that this is a valid data item.
  • a function such as this is implemented by a circuit arrangement such as that illustrated in FIG. 2 .
  • a data word a ⁇ n:1> with a length of n bits is supplied to a first circuit unit 4 , which forms the function f(a).
  • This signal is additionally inverted, so that both f(a) and not (f(a)) are available for further processing.
  • f(a) is then linked to the control bit S 0 in an AND circuit.
  • the value not(f(a)) is likewise linked to the control bit S 1 in an AND circuit.
  • the output values from the two AND gates are linked in an OR circuit in order to form the output value z.
  • a circuit such as this occurs not just once in a data processing apparatus, but must be provided separately for each bit that is to be processed in parallel.
  • An object of the invention is thus to specify a circuit arrangement for producing a dual-rail output signal, whose design is simpler and can be implemented using fewer transistors.
  • a further object is to specify a corresponding method.
  • a circuit arrangement for producing a dual-rail output signal having a first input with at least two connections for receiving a dual-rail input signal, a second input for receiving a control signal, a signal processing apparatus with a first switch and a second switch, which can each be driven as a function of the input signal, as well as two outputs, in which case the first output can be connected by means of one of the switches to a foot point, which is at a first potential, of the control apparatus, and the second output can be connected by means of the other switch to said foot point of the control apparatus, having a switching apparatus, having two inputs which are connected to the outputs of the signal processing apparatus, and having two outputs which are connected to two outputs of the circuit arrangement in order to output a dual-rail output signal, in which case the outputs can each be connected to one or to both inputs as a function of a control signal, and having a potential monitoring apparatus for defining the potentials at the outputs of the circuit arrangement when these are not connected via the switching apparatus and the signal processing
  • the circuit is physically very simple and does not have a large number of transistors.
  • the transistors which are responsible for carrying out the functions f(a, aq) and fq(a, aq) in the signal processing apparatus only four transistors are required for the switching apparatus, as well as transistors for the potential monitoring apparatus. In one preferred refinement, the potential monitoring apparatus requires only two transistors.
  • the circuit arrangement has precisely the functionality which is required for use of an input circuit as in the case of the data processing apparatus in FIG. 1 .
  • an additional precharge apparatus which can produce a predetermined identical potential at all the connections of the output which carry data, before each transmitted data item. This provides particularly good security against differential current profile analysis.
  • the signal processing apparatus includes an XOR function.
  • FIG. 1 shows a data processing apparatus in which a circuit arrangement according to the invention can be used
  • FIG. 2 shows a circuit arrangement according to the prior art
  • FIG. 3 shows a circuit arrangement according to the invention, illustrated schematically
  • FIG. 4 shows one specific implementation of the circuit arrangement shown in FIG. 2 ;
  • FIG. 5 shows a timing diagram with the signals for the circuit arrangement shown in FIG. 4 ;
  • FIG. 6 shows a first exemplary embodiment of a signal processing apparatus
  • FIG. 7 shows a second exemplary embodiment of a signal processing apparatus
  • FIG. 8 shows an embodiment of a circuit arrangement according to the invention, as shown in FIG. 3 , with p-channel transistors.
  • FIG. 1 shows the data processing apparatus which has already been described in the introduction, and in which a circuit arrangement according to the invention can be used.
  • FIG. 2 shows a circuit arrangement according to the prior art, which has likewise already been described in the introduction.
  • FIG. 3 shows a circuit arrangement according to the invention, illustrated schematically.
  • the circuit arrangement 11 has an input A 1 and A 2 , to which a dual-rail signal is fed.
  • the input A 1 in this case receives the data signal a
  • the input A 2 receives the complementary data signal aq. Both signals are supplied to the signal processing apparatus 12 .
  • the outputs x and xq of the signal processing apparatus 12 are connected to inputs D 1 and D 2 of a switching apparatus 13 .
  • Outputs E 1 and E 2 are connected to outputs F 1 and F 2 of the entire circuit arrangement, so that an output signal z and zq is produced there, which is a dual-rail signal.
  • zq is the complementary signal to z.
  • a control input G is provided, at which a control signal z is fed in and can be passed to the switching apparatus 13 .
  • the control signal 7 determines how the inputs D 1 and D 2 are connected to the outputs E 1 and E 2 of the switching apparatus 13 .
  • the potential monitoring apparatus 14 connects the output F 2 to the second potential VDD in the example just described.
  • One of the outputs x or xq of the signal processing apparatus 12 is always connected to the foot point v.
  • the connection of E 1 to both D 1 and D 2 thus means that the output E 1 of the switching apparatus 13 is always connected to the first potential 0 irrespective of the applied data a, aq and of the switch positions s, sq which result from such data, either via the switch s or the switch sq of the signal processing apparatus 12 .
  • this apparatus comprises two pull-up resistors, by means of which the outputs F 1 and F 2 are connected to the second potential VDD.
  • the disadvantage of a solution such as this is that, when one output is connected to the first potential V 0 , a parallel current flows through the resistor, and this leads to an undesirable current being drawn. This undesirable parallel current also occurs when a transistor connected as a resistor is used.
  • two transistors are provided, with in each case one transistor connecting one output to the second potential VDD via its drain-source path.
  • the gate connection is in each case driven by the other output. If these are p-channel transistors, the transistor is thus switched on automatically, as soon as the potential at the output which is connected to the gate becomes 0. This prevents the occurrence of parallel currents.
  • FIG. 4 shows a more detailed exemplary embodiment of a circuit arrangement according to the invention.
  • the control signal 7 is formed by the four individual signals s ⁇ 3 >, s ⁇ 2 >, s ⁇ 1 >and s ⁇ 0 >.
  • two precharge transistors 15 are shown. These connect the second potential VDD to the two outputs F 1 and F 2 .
  • FIG. 5 shows a signal diagram, which illustrates the time sequence of the signals that occur in the circuit shown in FIG. 4 .
  • This shows, by way of example, the time interval Z 1 .
  • FIG. 5 shows the other signal sequences, which have already been described with reference to the circuits in FIGS. 3 and 4 , so that the illustration can also be used to assist understanding of these circuits.
  • the switching apparatus 13 in FIGS. 3 and 4 provides the desired output response with four control bits. Although only four different operating states can be selected, since four transistors are provided, it is advantageous to use four control bits. Alternatively, the drive could be provided by two control bits, which would need to be split by means of an additional circuit in order to drive the four transistors. This results in the following association:
  • FIG. 8 shows a modification of the circuit arrangement shown in FIG. 4 . While the circuit in FIG. 4 is formed essentially from n-channel transistors, the configuration of a circuit arrangement as shown in FIG. 8 is formed mainly using p-channel transistors. The rest of the design is symmetrical with respect to the configuration of the circuit shown in FIG. 4 . It should be noted that n-channel transistors are used for the precharge transistors 25 , however, and are driven by the precharge signal p instead of pq. The foot point transistor 16 to be provided as a function of the drive can likewise be driven by the precharge signal p.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
US10/965,663 2002-04-18 2004-10-14 Circuit arrangement and method for producing a dual-rail signal Expired - Fee Related US7323910B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10217375.3 2002-04-18
DE10217375A DE10217375B4 (de) 2002-04-18 2002-04-18 Schaltungsanordnung und Verfahren zur Erzeugung eines Dual-Rail-Signals
PCT/DE2003/001059 WO2003088488A2 (de) 2002-04-18 2003-04-01 Schaltungsanordnung und verfahren zur erzeugung eines dual-rail-signals

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/001059 Continuation WO2003088488A2 (de) 2002-04-18 2003-04-01 Schaltungsanordnung und verfahren zur erzeugung eines dual-rail-signals

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US20050063478A1 US20050063478A1 (en) 2005-03-24
US7323910B2 true US7323910B2 (en) 2008-01-29

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US (1) US7323910B2 (de)
EP (1) EP1495542B1 (de)
JP (1) JP2005528022A (de)
CN (1) CN100361390C (de)
DE (2) DE10217375B4 (de)
RU (1) RU2286011C2 (de)
TW (1) TW200306072A (de)
WO (1) WO2003088488A2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9531384B1 (en) 2014-12-01 2016-12-27 University Of South Florida Adiabatic dynamic differential logic for differential power analysis resistant secure integrated circuits

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Publication number Priority date Publication date Assignee Title
DE102004001235B4 (de) * 2004-01-07 2005-12-15 Infineon Technologies Ag Übertragungsvorrichtung
DE102004063898B9 (de) * 2004-01-07 2012-12-20 Infineon Technologies Ag Übertragungsvorrichtung
DE102004020576B4 (de) * 2004-04-27 2007-03-15 Infineon Technologies Ag Datenverarbeitungsvorrichtung mit schaltbarer Ladungsneutralität und Verfahren zum Betreiben einer Dual-Rail-Schaltungskomponente
CN102609556A (zh) * 2011-01-25 2012-07-25 深圳市证通电子股份有限公司 抗功耗攻击aes模块功能设计的方法和电路
DE102012207065A1 (de) * 2012-04-27 2013-10-31 Siemens Ag Österreich Verfahren zur Herstellung einer logischen Schaltung

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9531384B1 (en) 2014-12-01 2016-12-27 University Of South Florida Adiabatic dynamic differential logic for differential power analysis resistant secure integrated circuits

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Publication number Publication date
EP1495542B1 (de) 2007-10-17
TW200306072A (en) 2003-11-01
EP1495542A2 (de) 2005-01-12
WO2003088488A2 (de) 2003-10-23
CN100361390C (zh) 2008-01-09
DE10217375A1 (de) 2003-11-06
RU2004133679A (ru) 2005-06-27
US20050063478A1 (en) 2005-03-24
WO2003088488A3 (de) 2004-02-19
JP2005528022A (ja) 2005-09-15
CN1647382A (zh) 2005-07-27
DE50308410D1 (de) 2007-11-29
DE10217375B4 (de) 2006-08-24
RU2286011C2 (ru) 2006-10-20

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