US7253481B2 - High performance MOS device with graded silicide - Google Patents
High performance MOS device with graded silicide Download PDFInfo
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- US7253481B2 US7253481B2 US11/181,521 US18152105A US7253481B2 US 7253481 B2 US7253481 B2 US 7253481B2 US 18152105 A US18152105 A US 18152105A US 7253481 B2 US7253481 B2 US 7253481B2
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- 229910021332 silicide Inorganic materials 0.000 title abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 6
- 206010010144 Completed suicide Diseases 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 230000001965 increasing effect Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
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- 238000005516 engineering process Methods 0.000 description 4
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
Definitions
- This invention generally relates to semiconductor devices and fabrication processes, and particularly to semiconductor device having a strained layer over source/drain regions.
- VLSI circuits The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, device drive current improvement becomes more important. Among efforts being made to improve device drive current, forming a strained silicon channel, thus enhancing carrier mobility, is a known practice. Strain, sometimes referred to as stress, can enhance bulk electron and hole mobility. The performance of a MOS device can be enhanced through a strained-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
- Strain can also be induced by forming a strained contact etch stop (CES) layer on a MOS device.
- CES strained contact etch stop
- a contact etch stop layer is deposited, due to the lattice spacing mismatch between the CES layer and the underlying layer, an in-plane strain develops to match the lattice spacing.
- strain also develops as a response to the strain applied, and the carrier mobility is enhanced.
- Strain applied to the channel region is determined by the intrinsic strain in the CES layer and its thickness, and the intrinsic strain generally increases when the thickness of the CES layer increases.
- FIG. 1 illustrates a conventional method of improving strain without the necessity of increasing the thickness of the CES layer.
- an extra recess step is performed on the substrate 2 along edges of the respective spacers 4 , forming recesses 6 in the source/drain regions 12 .
- a strained CES layer 10 is then formed. Due to the recesses 6 , strain applied on the channel region 8 by the CES layer 10 increases, and about a seven percent device drive current improvement has been observed due to the increased strain.
- the drive current improvement is significant in large devices. In small devices, particularly devices manufactured using 65 nm technologies and beyond, the drive current improvement is less observable, even though the channel mobility is improved. A possible reason is that the recessing of the source/drain regions 12 causes current crowding effects in regions 16 , which are substantially narrower portions of the source/drain regions 12 , and the device drive current is degraded accordingly. The current crowding effects are especially severe in small devices. In devices manufactured using 90 nm technology, the device drive current degradation due to current crowding effects is less than about one percent. In devices manufactured using 65 nm technology, the device drive current is degraded about 12 percent. With the further scaling of the devices, the device drive currents are expected to degrade even more.
- the preferred embodiments of the present invention provide a semiconductor device and a method of forming the same.
- the semiconductor device suffers fewer current crowding effects and has improved drive current.
- the semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer.
- the first portion of the diffusion region has a recessed top surface.
- the semiconductor device further includes a conductive layer on the diffusion region, and a cap layer over the conductive layer.
- the conductive layer is a silicide layer.
- the cap layer provides a strain to the channel region of the semiconductor device.
- the cap layer is a contact etch stop layer.
- the gate spacer includes a first portion and a second portion.
- the first and second portions preferably include materials having different etching characteristics.
- the method of forming the semiconductor device includes providing a substrate, forming a gate structure overlying the substrate, forming a sidewall spacer on a sidewall of the gate structure, removing an exposed portion of the substrate material to form a recess, thinning the sidewall spacer, forming a diffusion region in the semiconductor substrate, forming a silicide region on the diffusion region, and forming a cap layer having an inherent strain over the gate, the gate spacer and the source/drain region.
- the step of forming the sidewall spacer includes forming a first sidewall spacer on the sidewall of the gate and forming a second sidewall spacer along the first sidewall spacer, and the step of thinning the sidewall spacer includes removing a portion of the second sidewall spacer.
- the step of forming the sidewall spacer includes forming a first sidewall spacer on the sidewall of the gate and forming a second sidewall spacer along the first sidewall spacer, and the step of thinning the sidewall spacer includes removing substantially the entire second sidewall spacer.
- the preferred embodiments of the present invention reduce current crowding effects, so that the device drive current is improved. Leakage current is also reduced due to increased distance between the (source/drain) silicide regions and respective junctions.
- FIG. 1 illustrates a conventional method of improving strain in a MOS device by recessing source/drain regions
- FIGS. 2 through 10 are cross-sectional views of intermediate stages in the manufacture of a preferred embodiment, wherein a disposable sidewall spacer is formed substantially entirely removed in subsequent steps;
- FIGS. 11 through 13 illustrate cross-sectional views of intermediate stages in the manufacture of another preferred embodiment, wherein a disposable sidewall spacer is formed and partially removed in subsequent steps;
- FIGS. 14 through 16 are cross-sectional views of intermediate stages in a variation of the preferred embodiment, wherein a sidewall spacer is formed, and an outside portion of the sidewall spacer is removed in subsequent steps.
- FIG. 2 illustrates the formation of a gate stack comprising a gate dielectric 20 and a gate electrode 21 on a substrate 18 .
- the gate dielectric 20 preferably has high dielectric constant (k value).
- the substrate 18 comprises bulk silicon.
- other commonly used materials and structures such as germanium, SiGe, strained silicon on SiGe, silicon on insulator (SOI), silicon germanium on insulator (SGOI), germanium on insulator (GOI), and the like, can also be used.
- Shallow trench isolation regions (STI) 24 are formed in the substrate 18 to isolate subsequently formed devices.
- the formation of STIs 24 includes etching trenches in the substrate 18 and filling the trenches with dielectric materials.
- Lightly doped drain/source (LDD) regions 22 are formed in the substrate 18 , preferably by implanting appropriate impurities using the gate electrode 21 as a mask.
- halo regions 23 having an impurity type opposite the type of impurities in the LDD regions 22 are formed. Halo regions 23 are used for neutralizing the impurity of the LDD regions and the subsequently formed heavily doped source/drain regions, so that the LDD regions and heavily doped source/drain regions have greater abruptness on their borders. Halo regions 23 are preferably located close to the borders of the respective LDD regions 22 and subsequently formed source/drain regions.
- impurities can be implanted to desired depths, preferably with the center of the distribution region close to the desired border of the LDD regions 22 and subsequently formed source/drain regions.
- FIG. 3 illustrates the formation of a dummy layer 25 , which is used for forming spacers.
- the dummy layer 25 includes a liner oxide layer 26 , sometimes referred to as an adhesion layer, and a nitride layer 28 .
- the liner oxide layer 26 has better adhesion to the gate electrode 21 than the nitride layer 28 adheres to the gate electrode 21 .
- the dummy layer 25 may include single or composite layers comprising oxide, silicon nitride, silicon oxynitride (SiON) and/or other low-k materials, and may be formed using commonly used techniques, such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), etc.
- PECVD plasma enhanced chemical vapor deposition
- LPCVD low-pressure chemical vapor deposition
- SACVD sub-atmospheric chemical vapor deposition
- ALD atomic layer deposition
- FIG. 4 illustrates the liner oxide layer 26 and nitride layer 28 being patterned and etched to form gate spacers 30 . Either wet etching or dry etching can be used.
- the resulting spacers 30 comprise liner oxide portions 30 1 and nitride portions 30 2 .
- the thickness W 1 of the spacers 30 is between about 15 nm and about 75 nm.
- Disposable spacers 32 are then formed along outer edges of the respective spacers 30 , as illustrated in FIG. 5 .
- Disposable spacers 32 preferably comprise materials having different etching characteristics from the materials used to form gate spacers 30 , particularly the spacer portions 30 2 , so that disposable spacers 32 can be removed or thinned without damaging the gate spacers 30 .
- the disposable spacers 32 are formed of oxide.
- the thickness W 3 of the disposable spacers 32 is between about 1 nm and 55 nm.
- the combined width W 2 of the gate spacers 30 and disposable spacers 32 are preferably less than about 80 nm, and more preferably between about 30 nm and 80 nm.
- FIG. 6 illustrates the formation of recesses 34 .
- the substrate 18 is preferably etched anisotropocally along edges of the disposable spacers 32 to form the recesses 34 , which preferably extend from the respective edges of the disposable spacers 32 to the respective STI regions 24 .
- Recesses 34 preferably have a depth D of less than about 50 nm, and more preferably between about 1 nm and about 30 nm. Further discussion regarding the recessing depth D and width W 2 are provided in subsequent paragraphs.
- the disposable spacers 32 are then removed, as shown in FIG. 7 .
- wet etching is performed and a suitable etchant is chosen based on the material of the disposable spacers 32 .
- a suitable etchant is chosen based on the material of the disposable spacers 32 .
- an HF-containing etchant is used for stripping disposable spacers 32 that comprise oxides, while an H 3 PO 4 -containing etchant is preferably used for etching silicon nitride based spacers.
- Source/drain regions 36 are then formed, as shown in FIG. 8 , preferably by implanting appropriate impurities using the gate spacers 30 and gate electrode 21 as masks. Although in the preferred embodiment, the source/drain regions 36 are formed after the removal of the disposable spacers 32 , in other embodiments, the source/drain regions 36 can be formed before the disposable spacers 32 are removed.
- a conductive region 38 is formed, as illustrated in FIG. 9 .
- the conductive region 38 is preferably a silicide region, and also preferably comprises nickel.
- other commonly used metals such as titanium, cobalt, palladium, platinum, erbium, and the like, can also be used to form silicides.
- the silicidation is preferably performed by blanket deposition of an appropriate metal layer, followed by an annealing step in which the metal reacts with the underlying exposed silicon. Un-reacted metal is then removed, preferably with a selective etch process, and the silicide regions 38 are left.
- the thickness of the silicide regions 38 is preferably between about 5 nm and about 50 nm.
- the silicide regions 38 are graded due to the step heights of the source/drain regions 36 .
- a cap layer 40 sometimes referred to as a “strain inducing layer” 40 is formed.
- this layer is preferably a contact etch stop (CES) layer and is interchangeably referred to as CES layer 40 throughout the description, it can be any strained layer or layers, even if the layer does not perform an etch stop function.
- the cap layer 40 may also be a composite layer comprising a CES layer and other layers. The type and strength of the strain are determined by the deposition process and materials used. Preferably, nitride, oxynitride, and the like, are used.
- the thickness T of the cap layer 40 is preferably greater than the depth D of the recesses 34 (please refer to FIG. 6 ). Also, the thickness T is preferably between about 100 nm and about 1200 nm.
- the preferred embodiments of the present invention have the effect of shifting the silicide portion 42 away from the channel region 43 by a distance of (W 2 - W 1 ).
- the distance D 1 between the silicide regions 42 and the nearest border 44 , or the junction, of the source/drain regions 36 is therefore increased.
- the current crowding effects are reduced and the device drive current is improved.
- a further advantage of the preferred embodiments of the present invention is that the leakage current flowing from the silicide regions 38 to the substrate 18 is also reduced due to the increased distance between the silicide regions 38 and junctions, which are located at the borders 44 .
- the distance W 2 (as shown in FIG. 6 ) is preferably small.
- the crowding effects increase when the distance W 2 decreases, and the saturation current I dsat (not shown) is adversely affected. Therefore, the beneficial effects caused by the increased strain are offset somewhat.
- the determination of the distance W 2 has to take both factors into account.
- the distance W 2 is less than about 70 nm, and more preferably between about 30 and 70 nm.
- the strain introduced to the channel region and the drain saturation current I dsat of the device are related to the recessing depth D (please refer to FIG. 6). Having a greater recessing depth D increases the strain in the channel. However, the likelihood of current crowding also increases since the silicide regions are closer to the respective junctions when the recessing depth D increases. Considering that increased distance W 2 reduces the likelihood of the current crowding, balanced D and W 2 values will provide optimal effects. The optimal values of the D/W 2 ratio can be found through experiments. In the preferred embodiment, the ratio of D/W 2 is between about 1/7 and 3/7.
- FIGS. 12 and 13 illustrate structures after the formation of silicide regions 38 and cap layer 40 , respectively.
- FIGS. 14 through 16 illustrate yet another embodiment of the present invention.
- the initial steps of this embodiment are similar to those shown in FIG. 2 through 4 , and FIG. 14 illustrates a resulting structure.
- the thickness W 2 ′ of the spacers 30 is preferably greater than the thickness w 1 as shown in FIG.4 , and preferably has a similar value to W 2 as in the previously discussed embodiment.
- FIGS. 15 and 16 illustrate the formation of the recesses 34 , which have depth D, and source/drain regions 36 , respectively.
- the gate spacers 30 are then thinned to the thickness W 1 .
- the resulting structure is the same as shown in FIG. 8 .
- spacer portion 30 1 comprises oxide
- spacer portion 30 2 comprises nitride
- wet etching using an H 3 PO 4 -containing etchant can be performed to remove outer portions of the spacers 30 .
- the ratio of W 1 /W 2 ′ can be controlled by adjusting can be illustrated in FIG. 9 and 10 , respectively. The requirements of the materials, dimensions and forming methods have been discussed in the previously discussed embodiment, and thus are not repeated.
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Abstract
Description
Claims (16)
Priority Applications (3)
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US11/181,521 US7253481B2 (en) | 2005-07-14 | 2005-07-14 | High performance MOS device with graded silicide |
TW094146504A TWI283479B (en) | 2005-07-14 | 2005-12-26 | Semiconductor device and fabrication method thereof |
CN200610001770.3A CN100485964C (en) | 2005-07-14 | 2006-01-25 | Semiconductor device and its forming method |
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US11/181,521 US7253481B2 (en) | 2005-07-14 | 2005-07-14 | High performance MOS device with graded silicide |
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US20070013010A1 US20070013010A1 (en) | 2007-01-18 |
US7253481B2 true US7253481B2 (en) | 2007-08-07 |
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US20070267694A1 (en) * | 2006-05-22 | 2007-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors with stressed channels and methods of manufacture |
US20080044974A1 (en) * | 2004-05-21 | 2008-02-21 | Dureseti Chidambarrao | Embedded stressed nitride liners for cmos performance improvement |
US20080150026A1 (en) * | 2006-12-26 | 2008-06-26 | International Business Machines Corporation | Metal-oxide-semiconductor field effect transistor with an asymmetric silicide |
US20080179688A1 (en) * | 2006-07-20 | 2008-07-31 | Kong Beng Thei | Method and Apparatus for Semiconductor Device with Improved Source/Drain Junctions |
US20080283934A1 (en) * | 2006-05-18 | 2008-11-20 | Zhijiong Luo | Substantially l-shaped silicide for contact and related method |
US20080290412A1 (en) * | 2007-05-22 | 2008-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Suppressing short channel effects |
US20100059831A1 (en) * | 2006-06-05 | 2010-03-11 | Chartered Semiconductor Manufacturing, Ltd. | Spacer-less Low-K Dielectric Processes |
US20100163949A1 (en) * | 2008-12-29 | 2010-07-01 | International Business Machines Corporation | Vertical metal-insulator-metal (mim) capacitor using gate stack, gate spacer and contact via |
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US7825477B2 (en) * | 2007-04-23 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with localized stressor |
US8058123B2 (en) * | 2007-11-29 | 2011-11-15 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit and method of fabrication thereof |
DE102008011814B4 (en) * | 2008-02-29 | 2012-04-26 | Advanced Micro Devices, Inc. | CMOS device with buried insulating layer and deformed channel regions and method for producing the same |
CN101567385B (en) * | 2009-05-27 | 2012-11-14 | 上海宏力半导体制造有限公司 | Insulated source-drain electrode MOD transistor and preparation method thereof |
CN102789986B (en) * | 2011-05-20 | 2015-03-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor apparatus and manufacturing method thereof |
US9735159B2 (en) * | 2013-12-30 | 2017-08-15 | Texas Instruments Incorporated | Optimized layout for relaxed and strained liner in single stress liner technology |
US9660106B2 (en) * | 2014-08-18 | 2017-05-23 | United Microelectronics Corp. | Flash memory and method of manufacturing the same |
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Cited By (15)
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US20080044974A1 (en) * | 2004-05-21 | 2008-02-21 | Dureseti Chidambarrao | Embedded stressed nitride liners for cmos performance improvement |
US7615454B2 (en) * | 2004-05-21 | 2009-11-10 | International Business Machines Corporation | Embedded stressed nitride liners for CMOS performance improvement |
US8643119B2 (en) * | 2006-05-18 | 2014-02-04 | International Business Machines Corporation | Substantially L-shaped silicide for contact |
US20080283934A1 (en) * | 2006-05-18 | 2008-11-20 | Zhijiong Luo | Substantially l-shaped silicide for contact and related method |
US20070267694A1 (en) * | 2006-05-22 | 2007-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors with stressed channels and methods of manufacture |
US7569896B2 (en) * | 2006-05-22 | 2009-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors with stressed channels |
US20100059831A1 (en) * | 2006-06-05 | 2010-03-11 | Chartered Semiconductor Manufacturing, Ltd. | Spacer-less Low-K Dielectric Processes |
US8624329B2 (en) * | 2006-06-05 | 2014-01-07 | Globalfoundries Singapore Pte. Ltd. | Spacer-less low-K dielectric processes |
US20080179688A1 (en) * | 2006-07-20 | 2008-07-31 | Kong Beng Thei | Method and Apparatus for Semiconductor Device with Improved Source/Drain Junctions |
US7868386B2 (en) | 2006-07-20 | 2011-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for semiconductor device with improved source/drain junctions |
US20080150026A1 (en) * | 2006-12-26 | 2008-06-26 | International Business Machines Corporation | Metal-oxide-semiconductor field effect transistor with an asymmetric silicide |
US8354718B2 (en) * | 2007-05-22 | 2013-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including an arrangement for suppressing short channel effects |
US20080290412A1 (en) * | 2007-05-22 | 2008-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Suppressing short channel effects |
US20100163949A1 (en) * | 2008-12-29 | 2010-07-01 | International Business Machines Corporation | Vertical metal-insulator-metal (mim) capacitor using gate stack, gate spacer and contact via |
US8017997B2 (en) * | 2008-12-29 | 2011-09-13 | International Business Machines Corporation | Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via |
Also Published As
Publication number | Publication date |
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TW200703641A (en) | 2007-01-16 |
CN100485964C (en) | 2009-05-06 |
CN1897303A (en) | 2007-01-17 |
TWI283479B (en) | 2007-07-01 |
US20070013010A1 (en) | 2007-01-18 |
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