Connect public, paid and private patent data with Google Patents Public Datasets

Termination arrangement for high speed data rate multi-drop data bit connections

Download PDF

Info

Publication number
US7205789B1
US7205789B1 US11162023 US16202305A US7205789B1 US 7205789 B1 US7205789 B1 US 7205789B1 US 11162023 US11162023 US 11162023 US 16202305 A US16202305 A US 16202305A US 7205789 B1 US7205789 B1 US 7205789B1
Authority
US
Grant status
Grant
Patent type
Prior art keywords
switch
circuit
line
signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11162023
Inventor
Chris Karabatsos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CALLAHAN CELLULAR LLC
Original Assignee
Chris Karabatsos
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048Data bus control circuits, e.g. precharging, presetting, equalising
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0298Arrangement for terminating transmission lines

Abstract

A circuit for terminating devices attached to a signal line and driving a load includes a resistor R1 in series with the signal line circuit CR1 having a resistor in series with a switch wherein CR1 is in parallel with R1, a circuit CR2 having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, a circuit CR3 having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, a circuit CR4 having a resistor in series with a switch, connected at one end to ground and at the other to the load, a circuit CR5 having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, and a capacitor connected between the receiver or transmitter and ground.

Description

PROSECUTION HISTORY

This application claims priority based on Provisional Patent 60/604,482 (Aug. 26, 2004), for a “High Speed Termination Arrangement”

BACKGROUND OF INVENTION

The computer industry, with the advances of silicon technology, is constantly faced with the complexities of high speed Data Buses. The high speed of microprocessor CPUs requires a high speed data bus between the memory subsystem and the front end CPU data bus. However, speed without density of memory is an unbalanced combination. Modern computer systems require increasingly large RAM arrays, and these arrays are packaged in modules of approximately the same size as used in previous, lower capacity memories. Thus, the density of the memory modules, in bits or bytes per square inch of circuit board, is constantly increasing.

The CPU by itself cannot increase computer performance without a high speed memory sub-system and without such a high speed memory the CPU does not perform at the speed it was designed for. When memory access is substantially slower than CPU speed a bottleneck is created between memory and CPU Front End bus. With advances of the Internet, complex application programs and operating systems, memory sub-systems with high-density memory modules have become a necessity.

However, as the density of memory goes up above what a single memory chip can provide the capacitive loading of each data bit of the Data Bus increases. With the increase of the capacitive loading on the Data Bus, the driver of the data bit line is taxed for higher driving capability. As is well known, when the capacitive loading on a data line increases, the speed at which the corresponding driver circuit can change state on the data line decreases. Thus, on a given data line, the capacitive loading and the speed of data transfer are inversely proportional.

Many bus schemes have been designed to maximize speed in memory modules having increasing memory density. For that purpose, circuits utilizing pass gate switches have been designed into the data path to isolate and reduce the capacitive loading. Patents granted to the present inventor, Chris Karabatsos, include U.S. Pat. No. 6,446,1 58, U.S. Pat. No. 6,737,691, and U.S. Pat. No. 6,854,042, all intended to remedy this problem.

Data pulse widths in the nanosecond and sub nanosecond range are limited by high frequency data rates.

There are several factors to be considered in the design of such Bus circuits:

(a) Data bus widths must be broad enough to satisfy wide Data Bus requirements of the modern CPU.

(a) High Memory density must be maintained on the same Data Bus. That is, more Memory Modules are attached to the same Data Bus, and more connectors appear on the motherboard attached to the Bus.

The presence of parasitic Resistors, Inductors and Capacitors (RLC) in the structure of the Data Bus and on the devices, including Connectors, Memory modules, Printed circuit boards, Memory chips and logic chips connected to the Bus.

Effects of the physical RLC quantities affecting the overall speed by which data can be transported on the Bus and thus affecting the overall performance and bandwidth of such bus.

Synchronization of the Data signals and Strobe signals required to latch the data at the destination receiver.

Solutions to these problems in the prior art disclosed systems having dual data banks in which the data rate at each data bank is one-half the data rate at the memory subsystem bus, as described in inventions referenced above. However, further increases in computer speed have created synchronization and data capturing problems in the reading and writing of data between the system bus and the memory banks either directly or indirectly, as described in said prior art.

The present invention presents a radical improvement over the prior art by generating strobe signals and data signals which are synchronized with each other at both ends of the computer DATA BUS memory subsystem. One element is described herein that will allow the high speed reception and transmission of data bits and a termination scheme to reduce reflections and allow multi-drop memory data bit connections in the memory high speed subsystem.

The present invention provides a significant improvement in memory data rate speed and accuracy with substantial improvement in synchronization between the strobes and data in either direction of transmission and reception and better quality of signal over the prior art. It provides a termination arrangement for high speed data rate multi-drop data bit connections, described in the following description of the preferred embodiments of this invention.

SUMMARY OF THE INVENTION

It is an object of this invention to provide a termination circuit for devices connected to the data signal lines of electrical circuits to minimize reflected wave resulting from improper termination loads.

In accordance with one aspect of the invention a circuit for terminating devices attached to a signal line and driving a receiver or driver includes a resistor R1 in series with the signal line, a circuit CR1 comprising a resistor r2 in series with a switch s1, wherein CR1 is in parallel with R1, a circuit CR2 comprising a resistor R3 in series with switch S2, connected at one end to Vcc and at the other end to the receiver or driver, a circuit CR3 comprising a resistor R5 in series with switch S4, connected at one end to Vcc and at the other end to the receiver or driver, a circuit CR4 comprising a resistor R6 in series with switch S5, connected at one end to GND and at the other end to the receiver or driver, a circuit CR5 comprising a resistor R4 in series with switch S3, connected at one end to Vcc and at the other end to the receiver or driver, and a capacitor connected between the receiver or transmitter and ground.

In accordance with a second aspect of the invention, the circuit is configured in Write mode, wherein switch S1 is ON, switch S2 is ON, switch S3 is ON, switch S4 is ON, and switch S5 is ON.

In accordance with a third aspect of the invention, the circuit is configured Read mode, wherein switch S1 is ON, switch S1 is OFF, switch S1 is OFF, switch S1 is OFF, and switch S1 is OFF.

In accordance with a fourth aspect of the invention, the circuit is configured in Inactive mode, wherein switch S1 is OFF, switch S1 is ON, switch S1 is ON, switch S1 is OFF, and switch S1 is OFF.

BRIEF DESCRIPTION OF DRAWINGS

The invention will be more fully described in the following detailed description in conjunction with the drawings in which:

FIG. 1 a depicts a prior art termination circuit.

FIG. 1 b depicts a logic table of the present termination circuit.

FIG. 1 c depicts the present termination circuit in Write Mode.

FIG. 1 d depicts the present termination circuit in Read Mode.

FIG. 1 e depicts the present termination circuit in Inactive Mode.

PREFERRED EMBODIMENT OF THE INVENTION

It is well known that a signal traveling on a transmission line will reach the end of the transmission line and it will either be totally dissipated or it will be partially dissipated and partially reflected back to the source. This reflection process will continue until the energy traveling back and forth is totally dissipated, eventually being reduced to zero. This phenomenon happens because the amount of energy originating from the source is not totally used by the receiving load at the other end of the transmission line. In order not to have energy left on the line, the receiving load must be capable of using all of the energy. This means that the receiving load must be equal to the transmitting load. It is referred in the electronics industry as impedance matching.

In electronic circuits with the high speeds and complexities and construction of printed circuit boards, it is quite complex and difficult to obtain these ideal matching impedances. Several reasons contributing to the difficulties. The printed circuit boards cannot be made to correspond to the idea circuit elements of a paper design. System buses are made up of many signal lines, all of which have the characteristics of transmission lines. The signal receiving loads cannot be easily matched to the source loads, all of which contain Capacitive, Inductive and Resistive elements which exist in the connections and the packaging as well as in the silicon elements themselves. Several such loads are often attached to the same transmission line, further increasing the difficulty of impedance matching.

Furthermore, today's circuits operate at very high frequencies. For receiving circuits to operate properly, they need to receive signals of good quality, or high “signal integrity”, in terms of transition, duration and amplitude.

When a signal traveling on the transmission line has a short duration, it becomes very difficult to maintain good signal integrity. As the number of loads attached to the same transmission line increases, the lines become less and less capable of handling high frequency signals. Thus, the frequency of the traveling signal wave must be decreased in order for the receiver to receive it and process it properly. When several loads are connected to the same transmission line, the capacitive load increases and the time constant increases. A large time constant requires more time for the signal to stay in its intended value to be recognized by the receiver. At high frequencies, the signal has very short durations, commonly in the nanosecond and sub-nanosecond regions. As a result, the number of receiving loads that can be attached to the same transmission line must be decreases, and it approaches the number one.

To add to the problem, the quality of the signal deteriorates as the quality of the transmission line worsens due to construction variations and variations of terminating loads.

Electronics engineers designing the high frequency systems have adapted several methods to try to make the systems work. The simplest approach has been to construct the shortest line possible between the transmitter and receiver. However, due to the complexity of functions and system requirements in modern circuits, this approach is often not practical. In this description a memory subsystem is described wherein more than one device is attached to the main transmission line in a drop off mode, with terminations which allow good signal integrity at high transmission speeds.

The present computer environment requires that a memory subsystem have both high density and be operated at high speed in order to run complex software. The memory industry, and specifically the Standards body of the industry (“JEDEC®”), works constantly to find ways to cope with the existing problem of density and speed.

The individual memory devices of today are capable of operating at much higher speeds than their predecessors. When these devices are connected to a transmission line, an impedance matching circuit is contained within the memory device and within the controller to which it is attached. One such method is known as internal termination, wherein each signal line is terminated inside the silicon. The entry to the receiver is connected to the center of a resistor divider having one end connected to Vcc and the other to ground. This prior art circuit is shown in FIG. 1 a.

Still referring to this prior art circuit, when it is desired to drive a receiver along a transmission line switches s7 and s8 are closed, so that a resistive-capacititive (RC) network is established, having an R value of R7 and R8 in parallel, equal to 150 ohms in this example, and in parallel with capacitor C1. These values are selected to be the characteristic impedance of the transmission line, so that the receiver load is properly terminated. When it is not desired to drive a particular receiver 8 switches S7 and S8 are opened, supposedly creating an infinite impedance. However, this does not happen in practice, and the receiver 8 still presents an impedance to the transmission lines, creating reflecting waves.

When there are a multiple of such memory devices connected in parallel to the same transmission line, the problem of termination becomes more complex. Each line length from the transmission line to the memory device is known as a stub. Terminating all of these stubs to reduce signal reflections is not a simple process. Several problems are associated with said stubs. The termination at the end of each stub presents signal reflections and capacitive load to the main line. Such reflections traveling back and forth make the signal integrity to be unacceptable. In addition when the terminator network is active, it consumes power and makes the device that much hotter.

The capacitive load at each stub end is additive and as such it causes the amplitude of the signal to be small to reliably operate a receiver. The result is that stubs at high frequencies when added together complicate the values of terminator networks. To reduce this effect, the reduction of number of devices that can be attached to the same transmission line becomes necessary. This is a big problem when the present systems have to operate at high speeds requiring high memory densities.

The present invention solves the problem of properly terminating multiple stubs along a transmission line.

The circuit shown in FIG. 1 a is that used in the industry and adopted by JEDEC, the standards body. In this circuit a resistive divider is used as a termination, as previously discussed. The values of such resistor terminations are experimentally determined for acceptable signal integrity. However, the capacitive loads added together from all the stubs increase the overall time constant that affects the amplitude of the signal and the reflected signals. In addition, the reflections from the impedance of the receiver and the terminators travels back uninhibited to the main line. All of these reflections result in unacceptable signal degradation.

To state this in another way, the standard prior art approach uses a straight-through connection from the pad of the package to the pad of the silicon and to the center of the termination divider and straight to the internal silicon devices. This approach does nothing to reduce reflections.

The termination method of the present invention may be understood now by referring to FIGS. 1 c, 1 d, 1 e. These figures disclose a parallel resistor network built on the silicon at the entry of the signal path, before it reaches the internal receiver capacitive load. One side of this network is connected to the silicon entry pad and the other is connected to the resistor divider for the termination as shown. The characteristic impedance of the entry network are chosen carefully, as they must be appropriate for the operation performed. The parallel entry network resistor values are selected for each application to approximate the characteristic impedance of the network.

The component values shown in FIGS. 1 c, 1 d, and 1 e are used as examples, and are not intended to be the only values possible in this invention. For the purpose of this explanation and as a result of simulation and testing done with current circuits, these values appear to be appropriate for multi-drop (having a multitude of stubs) device connections. Other values could be selected for other wiring topologies and for other applications. The effect that these values have will be apparent with the discussion of each function.

These figures show the configuration of the present invention during three different functions. The WRITE function is shown in FIG. 1 c, the READ function in FIG. 1 d and the INACTIVE function as shown in FIG. 1 e, where the termination is neither written to nor being read from, as shown in FIG. 1 e. For use in multi-drop memory device connections, in this case memory modules known as DIMM (Dual In line Memory Module), only one function is performed on each module at a time.

Regardless of mode, the circuit of the present invention connects a signal line 2 to a Receiver or Driver 8. The figures show that the signal line 2 terminates at a package pad 6, typically a pad on a printed circuit board. The package pad 6 connects to a silicon pad 4, typically through bonding wire on the silicon device package.

On the other side of the bonding wire, as shown in FIGS. 1 a and 1 c through 1 e is resistor R1 in series with the signal line 2. Resistor R2 is in series with electronic switch S1, and the R2-S1 circuit is in parallel with R1. S1 may be opened or closed, depending upon the desired mode. Circuitry, not shown, is provided to open or close this switch automatically when the mode is switched. All the other switches of this circuit are controlled in a similar manner.

A complex resistor bridge is connected between Vcc (power) and GND (ground), in these figures. Resistor R5 is in series with switch S4, and resistor R3 is in series with switch S2. Resistor R6 is in series with switch S5, and resistor R4 is in series with switch S3. As in the prior art version, capacitor C connects the signal line to GND.

For the WRITE function of the selected device, as shown in FIG. 1 c, all of the switches are closed. The overall series input resistance of the network is the parallel combination of resistors R1 and R2. That small resistance slows down the signal by increasing the rise and fall time of the signal traveling to the input of the receiver 8. This slight reduction in speed produces fewer disturbances in the quality of the signal. The termination divider comprised of resistors R3 and R4, R5 and R6 is selected to minimize the reflections and reduce power consumption. The result is that for the application designed the signal reaches the receiver 8 with acceptable integrity and amplitude.

Since there are more devices attached to the same line and they are not selected, they are inactive and are configured as shown in FIG. 1 e.

The device in inactive mode has the switches S2 and S3 closed and S1, S4 and S5 open as shown in the figure. This combination applies higher resistance values for the termination and thus reduces power consumption. The value of R3 and R4 are selected for the application. When switch S1 is open a high resistance is inserted in series with the signal. The high input resistance R1 with the associated internal capacitive load causes a large time constant. It also isolates the internal capacitive load from the main line. As a result the selected device overall capacitive load time constant is smaller and it is affected mainly by the selected device. This allows the amplitude of the signal to reach acceptable value and integrity at the receiver of the selected device. The inactive capacitive load is not directly added to the selected device capacitive load. The reflection from the receiver of the inactive device is further attenuated by the high value of the series resistor and as such it has a very small effect in the integrity of the signal.

The READ mode operation is shown in FIG. 1 d. In this mode only S1 is closed and all other switches are open. The parallel combination of R1 and R2 reduces the overall resistance of the path and the signal traveling from inside the selected driver, the source, to the transmission line has a smoother transition and better impedance control of the main line. The effect is a better quality signal at the selected receiver 8 at the other end of the line. The small series equivalent resistance adds to the damping factor of the signal.

The Activation tables which are shown in FIG. 1 b show the combination of the switches for each operation.

While the invention has been described with reference to specific embodiments, it will be apparent that improvements and modifications may be made within the purview of the invention without departing from the scope of the invention defined in the appended claims.

Claims (4)

1. A circuit for terminating devices attached to a signal line and driving a receiver or driver, the circuit comprising:
(a) a resistor R1 in series with the signal line;
(b) a circuit CR1 comprising a resistor r2 in series with a switch s1, wherein CR1 is in parallel with R1;
(c) a circuit CR2 comprising a resistor R3 in series with switch S2, connected at one end to Vcc and at the other end to the receiver or driver;
(d) a circuit CR3 comprising a resistor R5 in series with switch S4, connected at one end to Vcc and at the other end to the receiver or driver;
(e) a circuit CR4 comprising a resistor R6 in series with switch S5, connected at one end to GND and at the other end to the receiver or driver;
(f) a circuit CR5 comprising a resistor R4 in series with switch S3, connected at one end to ground and at the other end to the receiver or driver; and
(g) a capacitor connected between the receiver or transmitter and ground.
2. The circuit of claim 1, configured in Write mode, wherein:
(a) switch S1 is ON;
(b) switch S2 is ON;
(c) switch S3 is ON;
(d) switch S4 is ON; and
(e) switch S5 is ON.
3. The circuit of claim 1, configured in Read mode, wherein:
(a) switch S1 is ON;
(b) switch S1 is OFF;
(c) switch S1 is OFF;
(d) switch S1 is OFF; and
(e) switch S1 is OFF.
4. The circuit of claim 1, configured in Inactive mode, wherein:
(a) switch S1 is OFF;
(b) switch S1 is ON;
(c) switch S1 is ON;
(d) switch S1 is OFF; and
(e) switch S1 is OFF.
US11162023 2004-08-26 2005-08-25 Termination arrangement for high speed data rate multi-drop data bit connections Active 2025-12-08 US7205789B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US60448204 true 2004-08-26 2004-08-26
US11162023 US7205789B1 (en) 2004-08-26 2005-08-25 Termination arrangement for high speed data rate multi-drop data bit connections

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11162023 US7205789B1 (en) 2004-08-26 2005-08-25 Termination arrangement for high speed data rate multi-drop data bit connections

Publications (1)

Publication Number Publication Date
US7205789B1 true US7205789B1 (en) 2007-04-17

Family

ID=37914126

Family Applications (1)

Application Number Title Priority Date Filing Date
US11162023 Active 2025-12-08 US7205789B1 (en) 2004-08-26 2005-08-25 Termination arrangement for high speed data rate multi-drop data bit connections

Country Status (1)

Country Link
US (1) US7205789B1 (en)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7730338B2 (en) 2006-07-31 2010-06-01 Google Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US7761724B2 (en) 2006-07-31 2010-07-20 Google Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8019589B2 (en) 2006-07-31 2011-09-13 Google Inc. Memory apparatus operable to perform a power-saving operation
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8154935B2 (en) 2006-07-31 2012-04-10 Google Inc. Delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8280714B2 (en) 2006-07-31 2012-10-02 Google Inc. Memory circuit simulation system and method with refresh capabilities
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8566516B2 (en) 2006-07-31 2013-10-22 Google Inc. Refresh management of memory modules
US8582339B2 (en) 2005-09-02 2013-11-12 Google Inc. System including memory stacks
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US20150333869A1 (en) * 2014-05-16 2015-11-19 Thine Electronics, Inc. Receiving device
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US9542353B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220211A (en) * 1991-10-28 1993-06-15 International Business Machines Corporation High speed bus transceiver with fault tolerant design for hot pluggable applications
US5982192A (en) * 1997-07-25 1999-11-09 Mitsubishi Denki Kabushiki Kaisha High speed bus circuit system
US6157688A (en) * 1996-10-09 2000-12-05 Fujitsu Limited Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system
US6356106B1 (en) * 2000-09-12 2002-03-12 Micron Technology, Inc. Active termination in a multidrop memory system
US6853213B2 (en) * 2001-10-29 2005-02-08 Elpida Memory, Inc. Input/output circuit, reference-voltage generating circuit, and semiconductor integrated circuit
US6937111B2 (en) * 2001-11-21 2005-08-30 Hynix Semiconductor Inc. Device and system having self-terminated driver and active terminator for high speed interface
US7058131B2 (en) * 2001-11-08 2006-06-06 International Business Machines Corporation Signal transmission system with programmable voltage reference

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220211A (en) * 1991-10-28 1993-06-15 International Business Machines Corporation High speed bus transceiver with fault tolerant design for hot pluggable applications
US6157688A (en) * 1996-10-09 2000-12-05 Fujitsu Limited Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system
US5982192A (en) * 1997-07-25 1999-11-09 Mitsubishi Denki Kabushiki Kaisha High speed bus circuit system
US6356106B1 (en) * 2000-09-12 2002-03-12 Micron Technology, Inc. Active termination in a multidrop memory system
US6853213B2 (en) * 2001-10-29 2005-02-08 Elpida Memory, Inc. Input/output circuit, reference-voltage generating circuit, and semiconductor integrated circuit
US7058131B2 (en) * 2001-11-08 2006-06-06 International Business Machines Corporation Signal transmission system with programmable voltage reference
US6937111B2 (en) * 2001-11-21 2005-08-30 Hynix Semiconductor Inc. Device and system having self-terminated driver and active terminator for high speed interface

Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8615679B2 (en) 2005-06-24 2013-12-24 Google Inc. Memory modules with reliability and serviceability functions
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8386833B2 (en) 2005-06-24 2013-02-26 Google Inc. Memory systems and memory modules
US8582339B2 (en) 2005-09-02 2013-11-12 Google Inc. System including memory stacks
US8811065B2 (en) 2005-09-02 2014-08-19 Google Inc. Performing error detection on DRAMs
US8619452B2 (en) 2005-09-02 2013-12-31 Google Inc. Methods and apparatus of stacking DRAMs
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US9542353B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8566556B2 (en) 2006-02-09 2013-10-22 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8797779B2 (en) 2006-02-09 2014-08-05 Google Inc. Memory module with memory stack and interface with enhanced capabilites
US9727458B2 (en) 2006-02-09 2017-08-08 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8280714B2 (en) 2006-07-31 2012-10-02 Google Inc. Memory circuit simulation system and method with refresh capabilities
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US7761724B2 (en) 2006-07-31 2010-07-20 Google Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8340953B2 (en) 2006-07-31 2012-12-25 Google, Inc. Memory circuit simulation with power saving capabilities
US8019589B2 (en) 2006-07-31 2011-09-13 Google Inc. Memory apparatus operable to perform a power-saving operation
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8154935B2 (en) 2006-07-31 2012-04-10 Google Inc. Delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US7730338B2 (en) 2006-07-31 2010-06-01 Google Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8566516B2 (en) 2006-07-31 2013-10-22 Google Inc. Refresh management of memory modules
US8745321B2 (en) 2006-07-31 2014-06-03 Google Inc. Simulating a memory standard
US8671244B2 (en) 2006-07-31 2014-03-11 Google Inc. Simulating a memory standard
US8631220B2 (en) 2006-07-31 2014-01-14 Google Inc. Adjusting the timing of signals associated with a memory system
US8595419B2 (en) 2006-07-31 2013-11-26 Google Inc. Memory apparatus operable to perform a power-saving operation
US8601204B2 (en) 2006-07-31 2013-12-03 Google Inc. Simulating a refresh operation latency
US8112266B2 (en) 2006-07-31 2012-02-07 Google Inc. Apparatus for simulating an aspect of a memory circuit
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8370566B2 (en) 2006-10-05 2013-02-05 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8751732B2 (en) 2006-10-05 2014-06-10 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module
US8760936B1 (en) 2006-11-13 2014-06-24 Google Inc. Multi-rank partial width memory modules
US8446781B1 (en) 2006-11-13 2013-05-21 Google Inc. Multi-rank partial width memory modules
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8675429B1 (en) 2007-11-16 2014-03-18 Google Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8730670B1 (en) 2007-12-18 2014-05-20 Google Inc. Embossed heat spreader
US8705240B1 (en) 2007-12-18 2014-04-22 Google Inc. Embossed heat spreader
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8631193B2 (en) 2008-02-21 2014-01-14 Google Inc. Emulation of abstracted DIMMS using abstracted DRAMS
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8762675B2 (en) 2008-06-23 2014-06-24 Google Inc. Memory system for synchronous data transmission
US8819356B2 (en) 2008-07-25 2014-08-26 Google Inc. Configurable multirank memory system with interface circuit
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
US9712344B2 (en) * 2014-05-16 2017-07-18 Thine Electronics, Inc. Receiving device with error detection circuit
US20150333869A1 (en) * 2014-05-16 2015-11-19 Thine Electronics, Inc. Receiving device

Similar Documents

Publication Publication Date Title
US6614664B2 (en) Memory module having series-connected printed circuit boards
US6751782B2 (en) Method and apparatus for analog compensation of driver output signal slew rate against device impedance variation
US5122691A (en) Integrated backplane interconnection architecture
US6992501B2 (en) Reflection-control system and method
US6067594A (en) High frequency bus system
US6308232B1 (en) Electronically moveable terminator and method for using same in a memory system
US6745268B1 (en) Capacitive multidrop bus compensation
US8130560B1 (en) Multi-rank partial width memory modules
US6275077B1 (en) Method and apparatus for programmable adjustment of bus driver propagation times
US5953215A (en) Apparatus and method for improving computer memory speed and capacity
US5955889A (en) Electronic circuit apparatus for transmitting signals through a bus and semiconductor device for generating a predetermined stable voltage
US20030200407A1 (en) Memory system
US5311081A (en) Data bus using open drain drivers and differential receivers together with distributed termination impedances
US6249142B1 (en) Dynamically terminated bus
US7024502B2 (en) Apparatus and method for topography dependent signaling
US20050097249A1 (en) Memory systems and methods
US6535945B1 (en) Method and apparatus for programmable adjustment of computer system bus parameters
US6628538B2 (en) Memory module including module data wirings available as a memory access data bus
US6480409B2 (en) Memory modules having integral terminating resistors and computer system boards for use with same
US6519173B2 (en) Memory system
US20040218434A1 (en) Mismatched on-die termination circuits and termination methods therefor
US6177807B1 (en) High frequency valid data strobe
US7111108B2 (en) Memory system having a multiplexed high-speed channel
US6674648B2 (en) Termination cards and systems therefore
US6218854B1 (en) Data line termination circuits and integrated circuit devices including attenuation circuit and charge/discharge circuit

Legal Events

Date Code Title Description
SULP Surcharge for late payment
FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: URENSCHI ASSETS LIMITED LIABILITY COMPANY, DELAWAR

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KARABATSOS, CHRIS;REEL/FRAME:025676/0408

Effective date: 20100831

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: CALLAHAN CELLULAR L.L.C., DELAWARE

Free format text: MERGER;ASSIGNOR:URENSCHI ASSETS LIMITED LIABILITY COMPANY;REEL/FRAME:037405/0751

Effective date: 20150827