US7200197B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
- Publication number
- US7200197B2 US7200197B2 US10/649,931 US64993103A US7200197B2 US 7200197 B2 US7200197 B2 US 7200197B2 US 64993103 A US64993103 A US 64993103A US 7200197 B2 US7200197 B2 US 7200197B2
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- US
- United States
- Prior art keywords
- data
- clock signal
- flip flop
- timing
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Definitions
- the present invention relates to a semiconductor integrated circuit for data processing in synchronization with a clock signal.
- Patent Document 1 JP-A-2000-113025 describes the configuration and fabrication method of such the hard macro.
- the hard macro its data input end is connected to a data input end of a flip flop (hereafter, it is called FF) on the input side and a data output end of an FF on the output side is connected to an output end of the hard macro through delay cells. Then, delay time of the delay cells is set so as to match data timing given to the FF on the input side from the data input end and data timing outputted to the data output end from the FF on the output side with timing of clock signals. Accordingly, the results of the hard macro are sequentially given to the subsequent hard macros in synchronization with the clock signals for assured processing.
- FF flip flop
- the maximum processing time allowed for internal circuits is fixed to a value that the setup time of the FF is subtracted from one cycle of a clock signal.
- the cycle of the clock signal needs to be extended, and the processing speed is likely to be reduced.
- the cycle of the clock signal needs to be matched with the processing time of the internal circuit having a long processing time. Thus, it is difficult to shorten the processing time.
- a semiconductor integrated circuit including: a hard macro having a plurality of combinational circuits for performing predetermined logic processing and a plurality of flip flops for performing data transfer, the hard macro being registered as a circuit pattern beforehand; an input flip flop for taking input data in synchronization with a clock signal; an output flip flop for outputting output data in synchronization with the clock signal; a first data path for giving the input data taken in the input flip flop to the hard macro; and a second data path for giving data outputted from the hard macro to the output flip flop, the had macro is configured as below.
- the hard macro has a first flip flop for holding data given from the first data path at timing delayed from the clock signal, a second flip flop for performing data transfer between the plurality of the combinational circuits in synchronization with the clock signal, and a third flip flop for holding data outputted to the second data path at timing advanced from the clock signal for output.
- FIGS. 1A and 1B are explanatory drawings of a semiconductor integrated circuit illustrating a first embodiment according to the invention
- FIG. 2 is a schematic block diagram of a semiconductor integrated circuit illustrating a second embodiment according to the invention.
- FIG. 3 is a schematic block diagram of a semiconductor integrated circuit illustrating a third embodiment according to the invention.
- FIG. 4 is a schematic block diagram of a semiconductor integrated circuit illustrating a fourth embodiment according to the invention.
- FIGS. 1A and 1B are explanatory drawings of a semiconductor integrated circuit illustrating a first embodiment according to the invention.
- FIG. 1A is a schematic block diagram
- FIG. 1B is an operation timing chart.
- the semiconductor integrated circuit has a hard macro 10 A, an FF group 1 and a combinational circuit 2 for forming a data path, both disposed on the input side of the hard macro 10 A, and a combinational circuit 3 for forming a data path and an FF group 4 , both disposed on the output side of the hard macro 10 A.
- the hard macro 10 A has a plurality of combinational circuits 11 to 17 for forming data paths, FF groups 12 to 16 for connecting the combinational circuits 11 to 17 in between, and nodes 18 a , 18 b and 18 c .
- the FF group 12 is connected to the node 18 a through a clock wiring line 19 a
- the FF group 14 is connected to the node 18 b through a clock wiring line 19 b
- the FF group 16 is connected to the node 18 c through a clock wiring line 19 c.
- the input side of the top combinational circuit 11 in the hard macro 10 A is connected to the output side of the combinational circuit 2 , and the output side of the last combinational circuit 17 at the backend is connected to the input side of a combinational circuit 3 .
- clock wiring lines 6 a and 6 c for feeding clock signals CK 1 and CK 3 from clock terminals 5 a and 5 c , respectively, are disposed for the nodes 18 a and 18 c in the hard macro 10 A. Furthermore, for the FF groups 1 and 4 and the node 18 b in the hard macro 10 A, a clock wiring line 6 b for feeding a clock signal CK 2 from a clock terminal 5 b in the same phase is disposed.
- the clock signal CK 1 slightly delayed from the clock signal CK 2 given to the clock terminal 5 b is given to the clock terminal 5 a .
- the clock signal CK 3 slightly advanced from the clock signal CK 2 is given to the clock terminal 5 c.
- the FF group 1 data D 1 outputted in synchronization with the rise of the clock signal CK 2 reaches the input side of the FF group 12 as data D 11 after processing (delay) time elapsed in the combinational circuits 2 and 11 .
- the data D 11 reached on the input side is held in synchronization with the rise of the clock signal CK 1 , and outputted as data D 12 . Therefore, the maximum allowable delay time between the FF group 1 and the FF group 12 is T+td ⁇ ts, where the cycle of the clock signal CK 2 is T, the delay time of the clock signal CK 1 is d 1 , and the setup time of the FF group 12 is ts.
- the FF group 16 data D 16 outputted in synchronization with the rise of the clock signal CK 3 reaches the input side of the FF group 4 as data D 3 after processing (delay) time elapsed in the combinational circuits 17 and 3 .
- the data D 3 reached on the input side is taken in synchronization with the rise of the clock signal CK 2 . Therefore, the maximum allowable delay time between the FF group 16 and the FF group 4 is T+tl ⁇ ts, where the cycle of the clock signal CK 2 is T, the lead time of the clock signal CK 3 is tl, and the setup time of the FF group 4 is ts.
- the semiconductor integrated circuit of the first embodiment has the clock terminals 5 a to 5 c for feeding the different clock signals CK 1 to CK 3 to the FF groups 12 to 16 in the hard macro 10 A, and the clock wiring lines 6 a to 6 c corresponding to the clock terminals 5 a to 5 c . Therefore, the clock signals fed to the FF groups 12 and 4 to take the data D 11 and D 3 can be delayed more than those fed to the FF groups 1 and 16 to output the data D 1 and D 16 . Accordingly, there are advantages that the time allowed for data transfer can be prolonged, timing conditions are satisfied even in the same clock frequencies, and processing time can be shortened.
- FIG. 2 is a schematic block diagram illustrating a semiconductor integrated circuit of a second embodiment according to the invention.
- the same components as those shown in FIG. 1 are designated the same numerals and signs.
- the semiconductor integrated circuit has a hard macro 10 B, an FF group 1 and a combinational circuit 2 , both disposed on the input side of the hard macro 10 B, and a combinational circuit 3 and an FF group 4 , both disposed on the output side of the hard macro 10 B.
- the hard macro 10 B has a plurality of combinational circuits 11 to 17 , FF groups 12 to 16 for connecting the combinational circuits 11 to 17 in between, a node 18 fed with clock signal CLK, and a clock wiring line 19 for feeding clock signals to the FF groups 12 to 16 from the node 18 .
- a clock signal CLK delayed by delay devices 21 and 22 for forming a unit for adjusting timing from the clock wiring line 19 is given to the FF groups 12 and 14 as clock signals CK 1 and CK 2 .
- the clock signal CLK on the clock wiring line 19 is given to the FF group 16 as a clock signal CK 3 .
- the clock signal CLK from a clock terminal 5 is fed to the FF groups 1 and 4 through delay devices 7 a and 7 b as the clock signal CK 2 in phase with that fed to the FF group 14 .
- the delay devices 22 , 7 a and 7 b are that even numbered inverters are cascade-connected, for example.
- the delay amounts of the delay devices 22 , 7 a and 7 b are set similarly, and the delay amount of a delay device 21 is set greater than those.
- the operation of the semiconductor integrated circuit is the same as the operation of the semiconductor integrated circuit shown in FIG. 1 , except that the clock signals CK 1 and CK 2 in the hard macro 10 B are generated by the delay devices 21 and 22 .
- the semiconductor integrated circuit of the second embodiment has the delay devices 21 and 22 for generating the different clock signals CK 1 to CK 3 in the hard macro 10 B. Accordingly, the semiconductor integrated circuit can generate the proper clock signals CK 1 to CK 3 in the hard macro 10 B in accordance with the function of the hard macro 10 B, having an advantage to allow a highly accurate operation, in addition to the advantage of the first embodiment.
- FIG. 3 is a schematic block diagram of a semiconductor integrated circuit illustrating a third embodiment according to the invention.
- the same components as those in FIG. 1 are designated the same numerals and signs.
- the semiconductor integrated circuit has a hard macro 10 C having a slightly different function instead of the hard macro 10 A. More specifically, three kinds of clock signals CK 1 to CK 3 are fed to FF groups 12 C and 16 C in the hard macro 10 C from nodes 18 a to 18 c through clock wiring lines 19 a to 19 c , and proper clock signals in the clock signals CK 1 to CK 3 are separately given.
- the other configurations are the same as those shown in FIG. 1 .
- the operation of the semiconductor integrated circuit is basically the same as the operation of the semiconductor integrated circuit shown in FIG. 1 . However, since the proper clock signals among the clock signals CK 1 to CK 3 are fed to each FF in the FF groups 12 c and 16 C, the operation is performed at the best timing in accordance with the delay time of the signal.
- the semiconductor integrated circuit of the third embodiment gives a plurality of the clock signals CK 1 to CK 3 having different timing to the FF groups 12 C and 16 C in the hard macro 10 C, and feeds the clock signals having proper timing to each FF in the FF groups 12 B and 16 B. Accordingly, the semiconductor integrated circuit has an advantage that the clock signals having proper timing are given to each FF in the hard macro 10 C and high-speed processing can be performed further highly accurately, in addition to the advantage of the first embodiment.
- FIG. 4 is a schematic block diagram of a semiconductor integrated circuit illustrating a fourth embodiment according to the invention, in which timing of clock signals fed to a synchronous RAM (Random Access Memory) incorporated therein is controlled to intend that limited processing (delay) time is relaxed and processing time is shortened.
- synchronous RAM Random Access Memory
- the semiconductor integrated circuit has FFs 31 and 35 , combinational circuits (LOGIC) 32 and 34 , a synchronous RAM 33 , a clock terminal 36 , delay devices 37 a , 37 b and 38 , and a selector (SEL) 39 for forming a timing supplying unit.
- FFs 31 and 35 combinational circuits (LOGIC) 32 and 34
- synchronous RAM 33 a synchronous RAM 33
- clock terminal 36 a clock terminal 36
- delay devices 37 a , 37 b and 38 for forming a timing supplying unit.
- SEL selector
- the FF 31 is that holds input data in synchronization with a clock signal CK 2 .
- a clock signal CLK given to the clock terminal 36 is delayed by the delay device 37 a and fed the clock signal CK 2 .
- the combinational circuit 32 is connected to an output side of the FF 31 , and an output side of the combinational circuit 32 is connected to an input terminal DI of the RAM 33 .
- the RAM 33 is that reads and writes data in synchronization with clock signals given to a clock terminal C.
- An address signal AD for an object to be accessed is given to an address terminal A, and a write control signal WE and a read control signal RE are given to control terminals W and R.
- the combinational circuit 34 is connected to an output terminal DO of the RAM 33 , and the FF 35 is connected to an output side of the combinational circuit 34 .
- the FF 35 is that holds output data from the combinational circuit 34 in synchronization with the clock signal CK 2 .
- the clock signal CLK given to the clock terminal 36 is delayed by the delay device 37 b , and fed as the clock signal CK 2 .
- the clock signal CLK given to the clock terminal 36 is delayed by the delay device 38 , and fed to a first input side of the selector 39 as clock signal CK 1 . It is also given to a second input side of the selector 39 as the clock signal CK 3 as it is. In the selector 39 , the second input side is selected when the read control signal RE is high (enable), and the first input side is selected when the signal is low (disable). An output side of the selector 39 is connected to the clock terminal C of the RAM 33 .
- the selector 39 selects and gives the clock signal CK 1 to the clock terminal C of the RAM 33 .
- input data held by the FF 31 is given to the input side of the combinational circuit 32 in synchronization with the clock signal CK 2 . Since the clock signal CK 1 has a delay amount greater than that of the clock signal CK 2 , delay (processing) time allowed for the combinational circuit 32 is longer than the cycle of the clock signal CLK.
- the read control signal RE When data is read out of the RAM 33 , the read control signal RE is turned high, the selector 39 selects and gives the clock signal CK 3 to the clock terminal C of the RAM 33 . On the other hand, the clock signal CK 2 is given to the FF 35 on the output side of the combinational circuit 34 . Since the clock signal CK 2 has a delay amount greater than that of the clock signal CK 3 , delay (processing) time allowed for the combinational circuit 34 is longer than the cycle of the clock signal CLK.
- the semiconductor integrated circuit of the fourth embodiment uses the clock signal CK 1 having delay longer than that of the clock signal CK 2 fed to the FFs 31 and 35 when data is written in the RAM 33 .
- the semiconductor integrated circuit uses the clock signal CK 3 having delay shorter than that of the clock signal CK 2 fed to the FFs 31 and 35 when data is readout of the RAM 33 . Accordingly, the delay (processing) time allowed for the combinational circuit 32 and 34 is longer, and a reliable operation is feasible. Furthermore, the clock speed is increased, and the operating speed can be improved.
- the invention is not limited to the embodiments, which can be modified variously. As the modified example, the following are named.
- the numbers of the combinational circuits and the FF groups are not defined. They can be set freely in accordance with the function and scale of a semiconductor integrated circuit applied.
- the hard macro has the first FF for holding data given from the first data path at timing delayed from the clock signals, and the third FF for holding data to be outputted at timing advanced from the clock signals. Accordingly, limits on the delay time of data paths on the input and output sides are relaxed, and the processing time can be shortened.
- the semiconductor integrated circuit has the delay devices for generating the clock signals for the input and output FFs, and the adjusting unit for adjusting the timing of the clock signals to be fed to each of the first to third FF groups in the hard macro. Accordingly, the timing of the clock signals does not need to be adjusted outside, and the hard macro can be operated at proper timing.
- the semiconductor integrated circuit has the clock terminals and the clock wiring lines for inputting the clock signals from outside, the clock signals are given to the first to third FF groups in the hard macro. Accordingly, the clock signals can be given at any given timing, and the optimum time control can be totally performed.
- the semiconductor integrated circuit has the timing supplying unit for giving a timing signal at timing delayed from the clock signal when data is written in the storage part and a timing signal at timing advanced from the clock signal when data is read out of the storage part. Accordingly, a limit on the delay time of the first data path is relaxed by the delay time of the timing signal when written, and a limit on the delay time of the second data path is relaxed by the lead time of the timing signal when read out.
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Abstract
Description
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2002257572A JP3629019B2 (en) | 2002-09-03 | 2002-09-03 | Semiconductor integrated circuit |
JP257572/2002 | 2002-09-03 |
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US20040078774A1 US20040078774A1 (en) | 2004-04-22 |
US7200197B2 true US7200197B2 (en) | 2007-04-03 |
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US10/649,931 Expired - Fee Related US7200197B2 (en) | 2002-09-03 | 2003-08-28 | Semiconductor integrated circuit |
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US (1) | US7200197B2 (en) |
JP (1) | JP3629019B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080028253A1 (en) * | 2006-07-31 | 2008-01-31 | Shaw Craig D | Bus having a dynamic timing bridge |
US8701059B2 (en) * | 2009-08-07 | 2014-04-15 | International Business Machines Corporation | Method and system for repartitioning a hierarchical circuit design |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7248661B1 (en) * | 2003-08-26 | 2007-07-24 | Analog Devices, Inc. | Data transfer between phase independent clock domains |
JP4928200B2 (en) * | 2006-09-11 | 2012-05-09 | キヤノン株式会社 | Data processing apparatus and control method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US4525849A (en) * | 1982-04-08 | 1985-06-25 | Siemens Aktiengesellschaft | Data transmission facility between two asynchronously controlled data processing systems with a buffer memory |
US5272728A (en) * | 1990-03-20 | 1993-12-21 | Fumio Ogawa | Preamble length adjustment method in communication network and independent synchronization type serial data communication device |
JPH0916655A (en) | 1995-07-03 | 1997-01-17 | Mitsubishi Electric Corp | Virtual environment generating device |
US5905766A (en) * | 1996-03-29 | 1999-05-18 | Fore Systems, Inc. | Synchronizer, method and system for transferring data |
US5996052A (en) * | 1996-08-20 | 1999-11-30 | Sony Corporation | Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array |
JP2000113025A (en) | 1998-10-09 | 2000-04-21 | Fujitsu Ltd | Hard macro preparing method, semiconductor chip designing method, and recording medium |
-
2002
- 2002-09-03 JP JP2002257572A patent/JP3629019B2/en not_active Expired - Fee Related
-
2003
- 2003-08-28 US US10/649,931 patent/US7200197B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4525849A (en) * | 1982-04-08 | 1985-06-25 | Siemens Aktiengesellschaft | Data transmission facility between two asynchronously controlled data processing systems with a buffer memory |
US5272728A (en) * | 1990-03-20 | 1993-12-21 | Fumio Ogawa | Preamble length adjustment method in communication network and independent synchronization type serial data communication device |
JPH0916655A (en) | 1995-07-03 | 1997-01-17 | Mitsubishi Electric Corp | Virtual environment generating device |
US5905766A (en) * | 1996-03-29 | 1999-05-18 | Fore Systems, Inc. | Synchronizer, method and system for transferring data |
US5996052A (en) * | 1996-08-20 | 1999-11-30 | Sony Corporation | Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array |
JP2000113025A (en) | 1998-10-09 | 2000-04-21 | Fujitsu Ltd | Hard macro preparing method, semiconductor chip designing method, and recording medium |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080028253A1 (en) * | 2006-07-31 | 2008-01-31 | Shaw Craig D | Bus having a dynamic timing bridge |
US7747889B2 (en) * | 2006-07-31 | 2010-06-29 | Freescale Semiconductor, Inc. | Bus having a dynamic timing bridge |
US8701059B2 (en) * | 2009-08-07 | 2014-04-15 | International Business Machines Corporation | Method and system for repartitioning a hierarchical circuit design |
Also Published As
Publication number | Publication date |
---|---|
US20040078774A1 (en) | 2004-04-22 |
JP3629019B2 (en) | 2005-03-16 |
JP2004094776A (en) | 2004-03-25 |
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