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Method of improving copper pad adhesion

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US7026721B2
US7026721B2 US09755282 US75528201A US7026721B2 US 7026721 B2 US7026721 B2 US 7026721B2 US 09755282 US09755282 US 09755282 US 75528201 A US75528201 A US 75528201A US 7026721 B2 US7026721 B2 US 7026721B2
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pad
layer
metal
structure
bond
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US20010016415A1 (en )
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Sheng-Hsiung Chen
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Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
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Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
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Abstract

This invention relates to a new improved method and structure in the fabricating of aluminum metal pads. The formation special aluminum bond pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by a special interlocking bond pad structure. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact bond pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.

Description

This is a division of patent application Ser. No. 09/442,497, filing date Nov. 18, 1999 now U.S. Pat. No. 6,191,023, Method Of Improving Copper Pad Adhesion, assigned to the same assignee as the present invention.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of aluminum pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by a special interlocking via structure. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.

As a background to the current invention, with the continuous shrinking of device dimensions, copper has been the most attractive material for interconnects. Before packaging of the chip, wire bonding is a serious problem when using gold wire bonding directly to a copper pad. Tantalum nitride has been commonly used as the barrier material for copper metallization in combination with an aluminum wire bond pad structure. A “standard” damascene process is used with copper interconnect metallization and large copper pad contacts to tungsten plugs. For better adhesion, the “convention” solution is the addition of tantalum nitride, TaN, as a barrier layer and the deposition of an AlCu pad on the surface. However, using this method is only a partial solution to the wire bonding problem. This invention describes a new method for improved wire bond pad adhesion in which a special via hole interlocking structure is fabricated between the TaN barrier layer and Al pad structure.

(2) Description of Related Art

The present invention is a new and improved method for fabricating aluminum metal bond pad structures wherein specifically to the formation-of aluminum bond pad metal structures are described which improve adhesion among the tantalum nitride pad barrier layer, top aluminum and the underlying copper pad metallurgy by using a special interlocking via structure. Related Prior Art background patents will now be described in this section.

U.S. Pat. No. 5,700,735 (Shiue et al.) teaches the formation of via plugs between the top metal layer and the pad. A bond pad structure and method of forming the bond pad structure is described which provides for reliable interconnections between the bond pad structure and the next level of circuit integration. The bond pad structure uses three metal pads separated by layers of dielectric. Via plugs are formed between the first and second metal pads and between the second and third metal pads. The via plugs are formed in a diamond shape with respect to the metal pads. The metal pads are squares with the same orientation. The periphery of the via plugs forms a square rotated 45 degrees with respect to the square metal pads.

U.S. Pat. No. 5,707,894 (Hsiao) teaches the formation anchor pads under the pad for better adhesion properties. A structure and a process for forming an improved bonding pad is described which resists bond pad peeling of between the bonding pad layer and the underlying layer. The method comprises forming plurality of anchor pads on said substrate surface in a bonding pad area. Next, a first insulating layer is formed over said substrate surface and the anchor pads. Vias are formed through the first insulating layer. The vias are filled with a second metal layer making a connection to the anchor pads and the first insulating layer is covered in the bonding pad area with the second metal layer. It is important that the via holes have a smaller cross sectional area than the anchor pads so that the combination of the anchor pads and the second metal form small “hooks” into the first insulating layer that hold the second metal (bonding pad layer) to the underlying layer.

U.S. Pat. No. 5,807,767 (Fu et al.) teaches a method of forming a pad with reduced electrical leakage. A method is described for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.

U.S. Pat. No. 5,834,365 (Ming-Tsung et al.) describes a method to form contour stripes under the Al pad layer to create an irregular surface. A structure and a process for forming an improved bonding pad is described which allows for better bonding between a bond wire and a metal bonding pad. Stripes are formed on a substrate. A conformal dielectric layer, a conformal barrier layer and a metal layer are formed over the stripes. A passivation layer with a window is formed defining a bonding pad area. The stripes promote an irregular surface in the barrier and metal layers which reduce stress between the dielectric layer, the barrier layer and the metal layer. Also, the irregular surfaces increase the barrier metal adhesion to the dielectric layer, reduce bond pad peel off, and increase bonding yields.

U.S. Pat. No. 5,309,025 (Bryant et al.) describes conductive lines under the pad which form an irregular pad surface to improve bond pad adhesion. A bond pad structure is formed by depositing a barrier layer over an underlying region of a semiconductor device, and then depositing a first conductive layer over the barrier layer. The barrier layer and conductive layer are then patterned and etched to define a conductive region. In a preferred embodiment, the conductive region is formed in the shape of a grid. A second conductive layer is deposited over the conductive region and a portion of the exposed underlying region. The second conductive layer makes a good adhesive contact with the underlying region, thus preventing bond pad lift off.

U.S. Pat. No. 5,904,565 (Nguyen et al.) describes an interconnect process with multiple conductive and non-conductive barrier layers. A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.

U.S. Pat. No. 5,795,796 (Kim) shows an Al interconnect with a TaN barrier layer. A method of fabricating a metal line includes the steps of preparing a semiconductor substrate, depositing a first metal on the semiconductor substrate, heat-treating the first metal to form a first metal nitride layer. depositing a second metal on the first metal nitride layer. heat treating the second metal. depositing a third metal on the second metal, and heat treating both the third metal and the second metal to form a metal insulating layer in which the second and the third metals are mixed. The method of fabricating increases the area occupied by the metal line in a contact hole, decreases contact resistance, and increases the speed of the device.

U.S. Pat. No. 5,668,411 (Hong at al.) shows a Al/TaN/Al structure with an anneal step. A diffusion barrier trilayer is comprised of a bottom layer, a seed layer and a top layer. The diffusion barrier trilayer prevents reaction of metallization layer with the top layer upon heat treatment, resulting in improved sheet resistance and device speed.

U.S. Pat. No. 5,785,236 (Cheung et al.) shows an Al pad over a Cu interconnect. A process is provided which enables electrical connection to be formed between gold and aluminum wires and copper interconnects. Conventional techniques for wire bonding are ineffective for bonding gold wires or aluminum wires to copper pads or copper interconnects. A process is provided to modify the copper pads so that conventional wire bonding techniques can be employed. In the process of the present invention an aluminum pad is formed over the copper interconnects. The metal wire is then bonded to the aluminum pad using conventional wire bonding techniques. No new hardware and/or technology is required for the metal wire bonding. No new technology is required to integrate the process of the invention into existing IC fabrication processes.

U.S. Pat. No. 5,547,901 (Kim et al.) shows a Cu wire with an Al oxide containing barrier layer. A method for forming a metal wiring of a semiconductor element, which uses an aluminum film as an oxidation prevention film to prevent oxygen from being diffused into copper contained in the metal wiring. An aluminum oxidation prevention film-layer is selectively formed on an exposed surface of the copper metal wiring layer using a selective chemical vapor deposition method. The width of the aluminum layer formed is below 100 Angstroms, and is converted into aluminum oxide with heat treating or under an atmosphere, thereby preventing the copper from oxidation. A diffusion prevention film between the substrate and the copper metal wiring layer is further included for preventing the copper from diffusing into the substrate.

U.S. Pat. No. 5,631,498 titled “Thin Film Metallization Process For Improved Metal To Substrate Adhesion” granted to Anchel, Ormond and Hayunga on May 20, 1997 describes a metallization layer formed on a substrate with improved adhesion thereto, by performing the deposition at an elevated temperature which favors the formation of chemical bonds of the metal to the substrate as well as clusters of metal embedded within the substrate and contiguous with the metallization layer. In polymer substrates the chemical bond is made to carbonyl functional groups such as ketones or aldehydes. The adhesion is enhanced by the removal of moisture from the surface of the substrate at the elevated temperatures employed. A high degree of adhesion is also obtained through the deposition of a mixture of metals including chromium and copper which initially has a high chromium to copper ratio which is decreased during the deposition process. Completion of the process is determined by the reaching of a final desired chromium to copper ratio as observed by optical emission spectroscopy. The process can be carried out on a continuous basis by the use of a multi-chamber vacuum sputtering system, cluster system or in-line system. The process is compatible for wire bond pads, direct solder flip chip attachment (C4s), and direct pin attachment processes.

The present invention is directed to a novel and improved method of fabricating metal pad structures. The method of the present invention requires less processing time, has lower cost than conventional methods and produces robust unique metal pad “interlocking” structures with good adhesion properties, low thermal stress and good conductivity.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a new and improved method for fabricating aluminum metal pad structures wherein a new and improved method and interlocking grid structure is fabricated for improved adhesion through wire bond processing. A “standard” damascene process is used with copper interconnect metallization and large copper pad contacts to tungsten plugs (not shown in Figures). For better adhesion, the “convention” solution is the addition of tantalum nitride, TaN, as a barrier layer and the deposition of an AlCu pad on the surface. However, using this method is only a partial solution to a wire bonding adhesion problem. This invention describes a new method for improved wire bond pad adhesion in which a special via hole interlocking grid structure is fabricated between the TaN barrier layer and Al pad structure.

As background to this invention, provided by Prior Art methods are: a semiconductor silicon substrate (or an IC module) with the first level of metal copper wiring being defined, embedded in the first layer of insulator, typically silicon oxide SiOx. The invention starts with these conventional layers being provided by Prior Art methods. Also provided by Prior Art methods, can be a metal “seed layer” and metal diffusion barrier layer beneath the metal copper wiring layers. (These seed and barrier layers are thin film adhesion layers or layer, not shown in the Figures). In addition, the first level metal is placed on an interlevel dielectric (ILD) insulating layer (an interconnect line layer, or device contact region to P-N junctions), provided by Prior Art methods.

The key embodiments of this present invention, which solve the deleterious adhesion problems, are now presented. As stated above, provided are a substrate, an insulating layer, an underlying copper layer defined as the start of the pad structure. The key process step to this invention is the deposition, patterning and defining of an interlocking grid structure composed of deposited, passivating material. The passivating material is typically defined by patterning photoresist. Spaces are etched by reactive ion etch (RIE) between the interlocking island or structures (an array of these structures are formed).

Referring in more detail to this interlocking grid structure and method for the formation of metal pad structures, more description now follows. These interlocking structures form “islands” of interlocking “grid” structures (an array in three dimensions) to enhance adhesion among the various layer of the metal stack pad structure for improved wire bond strength. The method and structure of said interlocking grid structure is formed by the patterning and etching of a passivation material, e.g., insulating silicon oxide, silicon nitride, polyimide material, etc. The said interlocking grid structure is then formed in a pad via contact region is, approximately 100 by 100 microns square and the size of the island structures are from about 10 to 25 microns in width, approximately 4 microns in height, and from about 4 to 10 in number per contact via pad structure. The said interlocking grid structure, formed in a pad via contact region forms an array in three dimensions said “grid”, group or an array of interlocking structures (“islands”).

The next key step of this invention, in yet another embodiment, is the deposition, patterning and etching of the metal barrier layer directly upon the via contact region, in the formation of the metal pad structure. The barrier layer deposition conforms to the interlocking island grid structures for improved adhesion. The metal barrier layer consists of thin layer of material, i.e., tantalum nitride. Prior to the deposition of the metal barrier layer, the photoresist used to define the interlocking structure is etched-off or “stripped”.

Next in the process sequence, is the completion of the metal pad stack structure with interlocking (islands) grid structure, as the main embodiment of this present invention. For completeness, as described above are provided in the metal stack pad structure: the substrate, an insulating layer, an the underlying copper layer. As stated earlier, the said key process step to this invention is the deposition, patterning and defining of a special passivation interlocking (grid) structures placed directly on top of the underlying copper metallurgy. In addition, in the structure is the patterned and defined barrier metal layer placed directly on top of interlocking structures. A final step in the process is deposition, patterning and definition of the aluminum pad metallurgy to form the top metal pad on top of the interlocking grid structure. This interlocking pad process and structure provides robust pad metal (stack) structures that having good adhesion properties (no metal or interface separation/peel failures, interface fracture failures). Since there are a large statistical number of these structures, failure rates must be very low and reliability very high, as tested by gold wire bond pull tests. Temperature and humidity cycling tests indicate the robustness of the process and structure from stress-crack corrosion, peeling, interface failure, adhesion failures, etc.

A “standard” gold wire bond pull test structure was used to evaluate the present invention's robust pad structures. For a standard pull test of metal adhesion strength (referred to as a manufacturing use test). An end portion of a 1.28 milli-inch diameter gold wire is bonded to the surface of the aluminum metal pad and tension applied thereto, at an angle of 90 degrees to the surface (to prevent shear). The diameter of the wire determines a standardized adhesion strength if the wire is broken first, at the tensile strength of the wire, before the pad is pulled away or peeled from the underlying structure. If the wire breaks (wire necking), it leaves a bonded portion called a nugget attached to the pad. It is considered that sufficient bonding has been achieved to develop adhesion that can withstand repeated thermal, humidity (T&H) and/or mechanical stress of the degree encountered during the testing and manufacturing. However, if a failure occurs between the metal and any interface in the structure (by peeling, fracture, interface failure) at a force less than that required to break the wire adhesion is considered to be of a significantly low value which it will be deleterious to the reliability of the product. Wire (bond) pull tests were conducted to a large numbers of pads, to be statistically significant, to prove the robustness of the invention's process and interlocking grid (islands) structure for good adhesion properties. (Note for completeness and to show diligence, low power wire bonding was performed, so as note to influence the pad structure.)

In summary, the present invention is a new and improved method for fabricating aluminum metal pad structures wherein the formation of aluminum pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by special interlocking grid (“islands”) via structures. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.

The problem of adhesion of metal pad to underlying layers, dielectrics, and polymers in is not unique to the manufacture of multi-layer electronic circuit chips and modules, but is encountered in other technologies involved in other types of electronic elements, e.g., the formation of capacitors or even other technologies entirely unrelated to the fabrication of electrical devices. However, since the problems of loss of adhesion are of substantial economic importance at present in the fabrication of multi-layer chips and modules, the present invention is directed to silicon chip technology and IC modules, but can be easily applied to other technologies using these metal pad materials and special interlocking (“islands”) grid structures.

This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the “DESCRIPTION OF THE PREFERRED EMBODIMENTS” section.

BRIEF DESCRIPTION OF THE DRAWINGS

The object and other advantages of this invention are best described in the preferred embodiments with reference to the attached drawings that include:

FIG. 1, which in cross-sectional representation illustrates a key process step of this invention, the defining and etching of a grid of special interlocking pad structures for improved metal pad stack adhesion.

FIG. 2, which in cross-sectional representation illustrates a another key process step of this invention: the deposition, patterning and defining of a thin barrier metal layer, e.g., tantalum nit-ride over the interlocking special via pad structures.

FIG. 3, which in cross-sectional representation illustrates another key process step of this invention: the completion of the metal pad (stack) structure, the preferred embodiments and preferred material stack with interlocking grid structure.

FIG. 4, which in cross-sectional representation of the metal pad region having the preferred embodiments of this invention with preferred material stack layers with interlocking grid structure, illustrating the gold tensile strength wire (bond) pull test and a gold “nugget”.

FIG. 5, which is a top plan view, depicts a sketch of a cutout section of a chip or die layout, showing multiple bond pads with individual interlocking grid arrays, for each conducting bond pad formed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is a new and improved method for fabricating aluminum metal pad structures. A “standard” damascene process is used with copper interconnect metallization and large copper pad contacts to tungsten plugs (not shown in Figures). For better adhesion, the “convention” solution is the addition of tantalum nitride, TaN, as a barrier layer and the deposition of an AlCu pad on the surface. However, using this method is only a partial solution to the wire bonding problem. This invention describes a new method for improved wire bond pad adhesion in which a special via hole interlocking structure is fabricated between the TaN barrier layer and Al pad structure.

Referring to FIG. 1, which in cross-sectional representation, shows a semiconductor silicon substrate 1 (or an IC module) with the first level of metal copper wiring 3 being defined, embedded in the first layer of insulator 2, typically silicon oxide SiOX. The invention starts with these conventional layers being provided by Prior Art methods. Also provided by Prior Art methods, can be a metal “seed layer” and metal diffusion barrier layer beneath the metal copper wiring layers. (These seed and barrier layers are thin film adhesion layers or layer, not shown in the Figures). In addition, the first level metal 3 is placed on an interlevel dielectric (ILD) insulating layer 2 (an interconnect line layer, or device contact region to P-N junctions), provided by Prior Art methods.

Referring to again to FIG. 1, in cross-sectional enlarged sketch of a microscopic region of the pad structure, the key embodiments of this present invention are presented. Provided are the substrate 1, insulating layer 2. The underlying copper layer 3 is depicted. The key process step to this invention is the deposition, patterning and defining of interlocking “island” structures 6 of deposited, passivating material 4. The passivating material is defined by patterning photoresist 5. Etched spaces 7 between the island structures are shown in FIG. 1. The passivation material (4) is, for example, silicon dioxide and silicon nitride in a thickness range from about 10,000 to 15,000 Angstroms, deposited by chemical vapor deposition (CVD) with deposition conditions of temperature between 300 to 380° C. and at a pressure of between 1 to 100 Torr

Referring again, in more detail to FIG. 1, a method and structure (in the fabrication of metal pad structures) is shown wherein a unique interlocking grid structure is formed. These interlocking structures form “islands” of interlocking “grid” structures (in three dimensions) to enhance adhesion among the various layer of the metal stack pad structure for improved wire bond strength. The method and structure of said interlocking grid structure 6 is formed by the patterning and etching of passivation material 4, e.g., insulating silicon oxide, silicon nitride, polyimide material, etc. The said interlocking grid structure 6 is formed in a pad via contact region is, approximately 100 by 100 microns square and the size of the “island” structures are from about 10 to 25 microns in width, approximately 4 microns in height, and from about 4 to 10 in number per contact via pad structure. The said interlocking grid structure 6, formed in a pad via contact region forms in three dimensions, a “grid”, group or an array of interlocking structures (“islands”).

Referring to FIG. 2, in cross-sectional sketch is shown the next key step of this invention, the deposition, patterning and etching of the metal barrier layer 10 upon the via contact region, in the formation of the metal pad structure. The barrier layer deposition conforms to the interlocking “island” grid structures for improved adhesion. The metal barrier layer consists of thin layer of material, i.e., tantalum nitride. Prior to the deposition of the metal barrier layer, the photoresist used to define the interlocking structure is etched-off or “stripped”.

Referring to FIG. 3, in cross-sectional sketch is shown the completed metal pad (stack) structure with interlocking (islands) grid structure, the main embodiment of in this present invention. As described in the previous figure, FIG. 2. Provided are the substrate 1, insulating layer 2. The underlying copper layer 3 is depicted. The key process step to this invention is the deposition, patterning and defining special passivation interlocking structures 6 placed directly on top of the underlying copper metallurgy. Also shown in FIG. 3 is the patterned and defined barrier metal layer 10, a TaN layer, approximately from 100 to 1,000 Angstroms in thickness, placed directly on top of interlocking structures. Finally, the aluminum pad 12 layer is deposited, patterned and defined to form the top metal pad on top of the interlocking structure 6. This interlocking pad process and structure provides robust pad metal (stack) structures that having good adhesion properties (no metal or interface separation/peel failures, interface fracture failures). Since there are a large statistical number of these structures, failure rates must be very low and reliability very high, as tested by gold wire bond pull tests. Temperature and humidity, cycling tests indicate the robustness of the process and structure from stress-crack corrosion, peeling, interface failure, adhesion failures, etc.

Referring to FIG. 4, in cross-sectional view, is sketched a “standard” gold wire bond pull test structure that was used to evaluate the present invention's robust pad structures. For a standard pull test of metal adhesion strength (referred to as a manufacturing use test), an end portion of a 1.28 milli-inch diameter gold wire 16 was bonded 22 to the surface of the aluminum metal pad 5 and tension 20 applied thereto, at an angle of 90 degrees (18) to the surface . The diameter of the wire determines a standardized adhesion strength if the wire is broken first, at the tensile strength of the wire, before the pad is pulled away or peeled from the underlying structure. If the wire breaks (note wire necking 46) and it leaves bonded a portion called a nugget 14 attached to the pad. It is considered that sufficient bonding has been achieved to develop adhesion that can withstand repeated thermal, humidity (T&H) and/or mechanical stress of the degree encountered during the testing and manufacturing. However, if a failure occurs between the metal and any interface in the structure (by peeling, fracture, interface failure) at a force less than that required to break the wire adhesion is considered to be of a significantly low value which it will be deleterious to the reliability of the product. Wire (bond) pull tests were conducted to a large numbers of pads, to be statistically significant, to prove the robustness of the invention's process and interlocking grid (islands) structure for good adhesion properties. (Note for completeness and diligence, low power wire bonding was performed, so as note to influence the pad structure. Typical, gold wire bonding conditions are: Au wire, 1.28 mils dia., time from 10 to 36 ms, power from 90 to 130 mW, force from 20 to 40 mg, temperature of 150° C.)

Referring to FIG. 5, which is a top plan view, the sketch depicts a cutout section of a chip or die layout 55, showing multiple bond pads 56, 57, 58, and 59 (arrows) with individual interlocking grid arrays 60, for each conducting bond pad formed. The interlocking grid arrays 60 are comprised of a passivating layer selected from the group consisting of silicon oxide, silicon nitride and polyimide and a conductive metal layer, selected from the group consisting of copper and aluminum. A diffusion barrier layer, underneath the conductive metal layer, is comprised of TaN. The bond pad structures, 56, 57, 58 and 59, top views shown, are conducting bond pad formed by the interlocking grid array, and are over bond pad via contact regions (underneath the bond pads), which is approximately 100 by 100 microns square and the size of the structures are from about 10 to 25 microns in width, approximately 4 microns in height, and from about 4 to 10 in number, per conducting bond pad, thus, increasing surface area for improved adhesion. Conducting lines 51, 52, 53 and 54 are underneath the bond pads and are electrically connected to the bond pads through the bond pad via contacts, thus the bond pads are “anchored” to conducting lines, as opposed to being “un-anchored or floating”.

In summary, the present invention is a new and improved method for fabricating aluminum metal pad structures wherein the formation of aluminum pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by special interlocking grid (“islands”) via structures. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.

The problem of adhesion of metal pad to underlying layers, dielectrics, and polymers in is not unique to the manufacture of multi-layer electronic circuit chips and modules, but is encountered in other technologies involved in other types of electronic elements, e.g., the formation of capacitors or even other technologies entirely unrelated to the fabrication of electrical devices. However, since the problems of loss of adhesion are of substantial economic importance at present in the fabrication of multi-layer chips and modules, the present invention is directed to silicon chip technology and IC modules, but can be easily applied to other technologies using these metal pad materials and special interlocking (“islands”) grid structures.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims (9)

1. A bond pad structure, comprising:
a semiconductor substrate;
a passivating layer forming multiple free-standing vertical islands to provide interlocking grid structures over said semiconductor substrate, wherein the vertical islands are separated by openings in said passivating layer;
a continuous barrier layer formed of tantalum nitride over said vertical islands of said passivating layer and in said openings; and
a conducting pad formed within said openings and over said interlocking grid structures and over said barrier layer, whereby an upper surface of said conductive pad provides improved adhesion for subsequently formed bonds.
2. The bond pad structure of claim 1, wherein said conductive pad is formed of copper.
3. The bond pad structure of claim 1, wherein said passivating layer is selected from the group consisting of silicon oxide, silicon nitride and polyimide.
4. A bond pad structure, comprising:
a semiconductor substrate;
comprising interlocking grid structures, formed over said semiconductor substrate;
a passivating layer, forming interlocking grid structures, said passivating layer having multiple openings to said interlocking grid structures to form multiple free-standing vertical islands;
a barrier layer formed of tantalum nitride over said passivating layer and in said openings, wherein said barrier layer is contiguous over said vertical islands;
a conducting pad formed over said interlocking grid structures and over said barrier layer, whereby an upper surface of said conductive pad provides improved adhesion for subsequently formed bonds,
wherein said bond pad forms an interlocking grid array in the bond pad via contact region, which is approximately 100 by 100 microns square and the size of the island structures are from about 10 to 25 microns in width, approximately 4 microns in height, and from about 4 to 10 in number, of interlocking grid structures, increasing surface area for improved adhesion.
5. The bond pad structure of claim 1, wherein said conductive bond pad is formed of aluminum.
6. A bond pad structure for a semiconductor device, the structure comprising:
an insulator layer adjacent to a semiconductor substrate;
a metal wiring layer adjacent to the insulator layer;
a passivation layer adjacent to the metal wiring layer, wherein at least a portion of the passivation layer is configured to provide a plurality of vertical island structures separated by spaces that expose a portion of the underlying metal wiring layer;
a contiguous metal barrier layer formed of tantalum nitride covering the islands of the passivation layer and the exposed portions of the metal wiring layer, wherein the metal barrier layer conforms to a shape provided by the island structures and does not completely fill the spaces between the island structures; and
a metal pad layer covering the metal barrier layer, wherein the metal pad layer fills the spaces between the island structures not filled by the metal barrier layer and rises above the island structures.
7. The bond pad structure of claim 6 wherein the metal barrier layer is substantially the same thickness throughout the bond pad structure.
8. The bond pad structure of claim 6 wherein the passivation layer is selected from the group consisting of silicon oxide, silicon nitride and polyimide.
9. The bond pad structure of claim 6 wherein the metal pad layer is formed of aluminum.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050073058A1 (en) * 2003-10-07 2005-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package bond pad having plurality of conductive members
US20050133894A1 (en) * 2003-12-17 2005-06-23 Bohr Mark T. Method and apparatus for improved power routing
US20060131748A1 (en) * 2000-06-28 2006-06-22 Krishna Seshan Ball limiting metallurgy split into segments
US20070262447A1 (en) * 2006-05-15 2007-11-15 Matsushita Electric Industrial Co., Ltd. Circuit board, method for manufacturing the same, and semiconductor device
US20110140191A1 (en) * 2009-12-15 2011-06-16 Semiconductor Manufacturing International (Shanghai) Corporation Method for manufacturing twin bit structure cell with silicon nitride layer
US20120306084A1 (en) * 2011-06-06 2012-12-06 Micron Technology, Inc. Semiconductor Constructions Having Through-Substrate Interconnects, and Methods of Forming Through-Substrate Interconnects
US8420531B2 (en) 2011-06-21 2013-04-16 International Business Machines Corporation Enhanced diffusion barrier for interconnect structures
US20150041208A1 (en) * 2013-08-07 2015-02-12 Invensas Corporation Micro mechanical anchor for 3d architecture

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413576B1 (en) * 1998-10-05 2002-07-02 Kulicke & Soffa Investments, Inc. Semiconductor copper bond pad surface protection
US7388289B1 (en) * 1999-09-02 2008-06-17 Micron Technology, Inc. Local multilayered metallization
US6803302B2 (en) * 1999-11-22 2004-10-12 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a mechanically robust pad interface
US6365970B1 (en) * 1999-12-10 2002-04-02 Silicon Integrated Systems Corporation Bond pad structure and its method of fabricating
US6790757B1 (en) * 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
JP2001217242A (en) 2000-02-03 2001-08-10 Seiko Epson Corp Semiconductor device and its manufacturing method
JP3659112B2 (en) * 2000-02-03 2005-06-15 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
JP3651765B2 (en) * 2000-03-27 2005-05-25 株式会社東芝 Semiconductor device
JP3700563B2 (en) * 2000-09-04 2005-09-28 セイコーエプソン株式会社 Method for manufacturing a bump forming method and a semiconductor device
JP4248761B2 (en) * 2001-04-27 2009-04-02 新光電気工業株式会社 The semiconductor package and its manufacturing method and a semiconductor device
US6884662B1 (en) 2002-01-28 2005-04-26 Taiwan Semiconductor Manufacturing Company Enhanced adhesion strength between mold resin and polyimide
US7535078B2 (en) 2002-02-14 2009-05-19 Freescale Semiconductor, Inc. Semiconductor device having a fuse and method of forming thereof
US6773532B2 (en) * 2002-02-27 2004-08-10 Jds Uniphase Corporation Method for improving heat dissipation in optical transmitter
KR100480891B1 (en) * 2002-05-16 2005-04-07 매그나칩 반도체 유한회사 Method for forming copper line in semiconductor device
US6864581B1 (en) 2002-08-15 2005-03-08 National Semiconductor Corporation Etched metal trace with reduced RF impendance resulting from the skin effect
US6703710B1 (en) 2002-08-15 2004-03-09 National Semiconductor Corporation Dual damascene metal trace with reduced RF impedance resulting from the skin effect
US6853079B1 (en) 2002-08-15 2005-02-08 National Semiconductor Corporation Conductive trace with reduced RF impedance resulting from the skin effect
US6740956B1 (en) 2002-08-15 2004-05-25 National Semiconductor Corporation Metal trace with reduced RF impedance resulting from the skin effect
KR100448344B1 (en) * 2002-10-22 2004-09-13 삼성전자주식회사 Method for manufacturing wafer level chip scale package
KR100497193B1 (en) * 2002-12-17 2005-06-28 동부아남반도체 주식회사 Bonding pad for semiconductor device and formation method of the same
US7023090B2 (en) 2003-01-29 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad and via structure design
US6864578B2 (en) * 2003-04-03 2005-03-08 International Business Machines Corporation Internally reinforced bond pads
US7701069B2 (en) * 2003-06-30 2010-04-20 Intel Corporation Solder interface locking using unidirectional growth of an intermetallic compound
US6960831B2 (en) * 2003-09-25 2005-11-01 International Business Machines Corporation Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad
US7238285B2 (en) * 2004-03-05 2007-07-03 Donaldson Company, Inc. Liquid filter assembly for use with treatment agent; and, methods
US7833896B2 (en) * 2004-09-23 2010-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Aluminum cap for reducing scratch and wire-bond bridging of bond pads
US7741714B2 (en) * 2004-11-02 2010-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure with stress-buffering layer capping interconnection metal layer
US20060211167A1 (en) * 2005-03-18 2006-09-21 International Business Machines Corporation Methods and systems for improving microelectronic i/o current capabilities
JP2007019473A (en) * 2005-06-10 2007-01-25 Nec Electronics Corp Semiconductor device
DE102005043914B4 (en) * 2005-09-14 2009-08-13 Infineon Technologies Ag A semiconductor device for bonding and methods for preparing
US7504728B2 (en) * 2005-12-09 2009-03-17 Agere Systems Inc. Integrated circuit having bond pad with improved thermal and mechanical properties
US7598620B2 (en) * 2006-05-31 2009-10-06 Hebert Francois Copper bonding compatible bond pad structure and method
KR100933685B1 (en) * 2007-12-18 2009-12-23 주식회사 하이닉스반도체 Bonding pads and a method for preventing peeling
US20100007028A1 (en) * 2008-07-11 2010-01-14 Infineon Technologies Austria Ag Device including an imide layer with non-contact openings and method
FR2959868A1 (en) * 2010-05-06 2011-11-11 St Microelectronics Crolles 2 A semiconductor device has connecting pads provided with inserts
US20130154099A1 (en) 2011-12-16 2013-06-20 Semiconductor Components Industries, Llc Pad over interconnect pad structure design
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US8810024B2 (en) 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
US9837303B2 (en) * 2012-03-23 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US9455226B2 (en) * 2013-02-01 2016-09-27 Mediatek Inc. Semiconductor device allowing metal layer routing formed directly under metal pad
US9536833B2 (en) 2013-02-01 2017-01-03 Mediatek Inc. Semiconductor device allowing metal layer routing formed directly under metal pad
US9852985B1 (en) * 2016-06-27 2017-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive terminal on integrated circuit

Citations (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184121B2 (en) *
US4141030A (en) * 1975-12-17 1979-02-20 Bbc Brown Boveri & Company Limited High-power semiconductor assembly in disk-cell configuration
GB2184288A (en) * 1985-12-16 1987-06-17 Nat Semiconductor Corp Oxidation inhibition of copper bonding pads using palladium
JPH01309340A (en) * 1988-06-07 1989-12-13 Mitsubishi Electric Corp Semiconductor device
JPH0456237A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor device
JPH04124844A (en) * 1990-09-17 1992-04-24 Oki Electric Ind Co Ltd Structure of bonding pad electrode for semiconductor device
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
US5357136A (en) * 1992-04-10 1994-10-18 Oki Electric Industry Co., Ltd. Semiconductor device with anchored interconnection layer
US5547901A (en) 1994-05-24 1996-08-20 Lg Semicon Co., Ltd. Method for forming a copper metal wiring with aluminum containing oxidation barrier
US5631498A (en) 1992-06-04 1997-05-20 International Business Machines Corporation Thin film metallization process for improved metal to substrate adhesion
US5668411A (en) 1995-03-28 1997-09-16 Texas Instruments Incorporated Diffusion barrier trilayer for minimizing reaction between metallization layers of integrated circuits
US5686762A (en) * 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
US5693565A (en) * 1996-07-15 1997-12-02 Dow Corning Corporation Semiconductor chips suitable for known good die testing
US5700735A (en) 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
US5703408A (en) * 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof
US5707894A (en) 1995-10-27 1998-01-13 United Microelectronics Corporation Bonding pad structure and method thereof
US5723822A (en) * 1995-03-24 1998-03-03 Integrated Device Technology, Inc. Structure for fabricating a bonding pad having improved adhesion to an underlying structure
US5736791A (en) * 1995-02-07 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and bonding pad structure therefor
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
US5785236A (en) 1995-11-29 1998-07-28 Advanced Micro Devices, Inc. Advanced copper interconnect system that is compatible with existing IC wire bonding technology
US5795796A (en) 1995-12-26 1998-08-18 Lg Semicon Co., Ltd. Method of fabricating metal line structure
US5807787A (en) 1996-12-02 1998-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation
JPH10256301A (en) * 1997-03-06 1998-09-25 Hitachi Ltd Tape bonding apparatus and manufacture of semiconductor integrated circuit device using the same
US5886414A (en) * 1996-09-20 1999-03-23 Integrated Device Technology, Inc. Removal of extended bond pads using intermetallics
US5900668A (en) * 1995-11-30 1999-05-04 Advanced Micro Devices, Inc. Low capacitance interconnection
US5904565A (en) 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US5936283A (en) * 1996-08-05 1999-08-10 Nec Corporation MOSFET for input/output protective circuit having a multi-layered contact structure with multiple contact holes on a single diffusion layer
US5994762A (en) * 1996-07-26 1999-11-30 Hitachi, Ltd. Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof
US6002179A (en) * 1997-09-15 1999-12-14 Winbond Electronics Corporation Bonding pad structure for integrated circuit (I)
US6033984A (en) * 1997-12-23 2000-03-07 Siemens Aktiengesellschaft Dual damascene with bond pads
US6034439A (en) * 1998-02-07 2000-03-07 Winbond Electronics Corporation Method and structure for preventing bonding pads from peeling caused by plug process
US6081033A (en) * 1997-07-29 2000-06-27 Micron Technology, Inc. Interconnections for semiconductor circuits
US6127266A (en) * 1996-11-26 2000-10-03 Mitel Corporation Stabilization of the interface between tiN and A1 alloys
US6133136A (en) * 1999-05-19 2000-10-17 International Business Machines Corporation Robust interconnect structure
US6184121B1 (en) * 1997-07-10 2001-02-06 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US6207547B1 (en) * 1998-05-04 2001-03-27 Lucent Technologies Inc. Bond pad design for integrated circuits
US6218732B1 (en) * 1998-09-15 2001-04-17 Texas Instruments Incorporated Copper bond pad process
US6232662B1 (en) * 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6249038B1 (en) * 1999-06-04 2001-06-19 International Business Machines Corporation Method and structure for a semiconductor fuse
US6252300B1 (en) * 1999-01-14 2001-06-26 United Microelectronics Corp. Direct contact through hole type wafer structure
US6255586B1 (en) * 1998-09-04 2001-07-03 Samsung Electronics Co., Ltd. Interlocked bonding pad structures and methods of fabrication therefor
US6297563B1 (en) * 1998-10-01 2001-10-02 Yamaha Corporation Bonding pad structure of semiconductor device
US6306750B1 (en) * 2000-01-18 2001-10-23 Taiwan Semiconductor Manufacturing Company Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability
US6320263B1 (en) * 1999-02-18 2001-11-20 Advanced Micro Devices, Inc. Semiconductor metalization barrier and manufacturing method therefor
US6329722B1 (en) * 1999-07-01 2001-12-11 Texas Instruments Incorporated Bonding pads for integrated circuits having copper interconnect metallization
US20010051426A1 (en) * 1999-11-22 2001-12-13 Scott K. Pozder Method for forming a semiconductor device having a mechanically robust pad interface.
US20020005582A1 (en) * 1998-08-11 2002-01-17 Takeshi Nogami Pad structure for copper interconnection and its formation
US6350667B1 (en) * 1999-11-01 2002-02-26 Taiwan Semiconductor Manufacturing Company Method of improving pad metal adhesion
US6358847B1 (en) * 1999-03-31 2002-03-19 Lam Research Corporation Method for enabling conventional wire bonding to copper-based bond pad features
US6362528B2 (en) * 1996-08-21 2002-03-26 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6444295B1 (en) * 1998-12-29 2002-09-03 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
US6448650B1 (en) * 1998-05-18 2002-09-10 Texas Instruments Incorporated Fine pitch system and method for reinforcing bond pads in semiconductor devices
US6448641B2 (en) * 1999-03-19 2002-09-10 Industrial Technology Research Institute Low-capacitance bonding pad for semiconductor device
US6451681B1 (en) * 1999-10-04 2002-09-17 Motorola, Inc. Method of forming copper interconnection utilizing aluminum capping film
US6551916B2 (en) * 1999-06-08 2003-04-22 Winbond Electronics Corp. Bond-pad with pad edge strengthening structure
US6625882B1 (en) * 1997-05-01 2003-09-30 Texas Instruments Incorporated System and method for reinforcing a bond pad

Patent Citations (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362528B1 (en) *
US6184121B2 (en) *
US4141030A (en) * 1975-12-17 1979-02-20 Bbc Brown Boveri & Company Limited High-power semiconductor assembly in disk-cell configuration
GB2184288A (en) * 1985-12-16 1987-06-17 Nat Semiconductor Corp Oxidation inhibition of copper bonding pads using palladium
JPH01309340A (en) * 1988-06-07 1989-12-13 Mitsubishi Electric Corp Semiconductor device
JPH0456237A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor device
JPH04124844A (en) * 1990-09-17 1992-04-24 Oki Electric Ind Co Ltd Structure of bonding pad electrode for semiconductor device
US5357136A (en) * 1992-04-10 1994-10-18 Oki Electric Industry Co., Ltd. Semiconductor device with anchored interconnection layer
US5631498A (en) 1992-06-04 1997-05-20 International Business Machines Corporation Thin film metallization process for improved metal to substrate adhesion
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
US5547901A (en) 1994-05-24 1996-08-20 Lg Semicon Co., Ltd. Method for forming a copper metal wiring with aluminum containing oxidation barrier
US5736791A (en) * 1995-02-07 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and bonding pad structure therefor
US5723822A (en) * 1995-03-24 1998-03-03 Integrated Device Technology, Inc. Structure for fabricating a bonding pad having improved adhesion to an underlying structure
US5668411A (en) 1995-03-28 1997-09-16 Texas Instruments Incorporated Diffusion barrier trilayer for minimizing reaction between metallization layers of integrated circuits
US5703408A (en) * 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof
US5834365A (en) 1995-04-10 1998-11-10 United Microelectronics Corp. Method of forming a bonding pad
US5707894A (en) 1995-10-27 1998-01-13 United Microelectronics Corporation Bonding pad structure and method thereof
US5785236A (en) 1995-11-29 1998-07-28 Advanced Micro Devices, Inc. Advanced copper interconnect system that is compatible with existing IC wire bonding technology
US5900668A (en) * 1995-11-30 1999-05-04 Advanced Micro Devices, Inc. Low capacitance interconnection
US5686762A (en) * 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
US5795796A (en) 1995-12-26 1998-08-18 Lg Semicon Co., Ltd. Method of fabricating metal line structure
US5693565A (en) * 1996-07-15 1997-12-02 Dow Corning Corporation Semiconductor chips suitable for known good die testing
US5994762A (en) * 1996-07-26 1999-11-30 Hitachi, Ltd. Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof
US5936283A (en) * 1996-08-05 1999-08-10 Nec Corporation MOSFET for input/output protective circuit having a multi-layered contact structure with multiple contact holes on a single diffusion layer
US6720658B2 (en) * 1996-08-21 2004-04-13 Kabushiki Kaisha Toshiba Semiconductor device having a plurality of conductive layers
US6362528B2 (en) * 1996-08-21 2002-03-26 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US5700735A (en) 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
US5923088A (en) * 1996-08-22 1999-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure for the via plug process
US5886414A (en) * 1996-09-20 1999-03-23 Integrated Device Technology, Inc. Removal of extended bond pads using intermetallics
US6127266A (en) * 1996-11-26 2000-10-03 Mitel Corporation Stabilization of the interface between tiN and A1 alloys
US5807787A (en) 1996-12-02 1998-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation
JPH10256301A (en) * 1997-03-06 1998-09-25 Hitachi Ltd Tape bonding apparatus and manufacture of semiconductor integrated circuit device using the same
US6625882B1 (en) * 1997-05-01 2003-09-30 Texas Instruments Incorporated System and method for reinforcing a bond pad
US6184121B1 (en) * 1997-07-10 2001-02-06 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US5904565A (en) 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6081033A (en) * 1997-07-29 2000-06-27 Micron Technology, Inc. Interconnections for semiconductor circuits
US6002179A (en) * 1997-09-15 1999-12-14 Winbond Electronics Corporation Bonding pad structure for integrated circuit (I)
US6033984A (en) * 1997-12-23 2000-03-07 Siemens Aktiengesellschaft Dual damascene with bond pads
US6034439A (en) * 1998-02-07 2000-03-07 Winbond Electronics Corporation Method and structure for preventing bonding pads from peeling caused by plug process
US6207547B1 (en) * 1998-05-04 2001-03-27 Lucent Technologies Inc. Bond pad design for integrated circuits
US6448650B1 (en) * 1998-05-18 2002-09-10 Texas Instruments Incorporated Fine pitch system and method for reinforcing bond pads in semiconductor devices
US6232662B1 (en) * 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US20020005582A1 (en) * 1998-08-11 2002-01-17 Takeshi Nogami Pad structure for copper interconnection and its formation
US6255586B1 (en) * 1998-09-04 2001-07-03 Samsung Electronics Co., Ltd. Interlocked bonding pad structures and methods of fabrication therefor
US6218732B1 (en) * 1998-09-15 2001-04-17 Texas Instruments Incorporated Copper bond pad process
US6297563B1 (en) * 1998-10-01 2001-10-02 Yamaha Corporation Bonding pad structure of semiconductor device
US6599578B2 (en) * 1998-12-29 2003-07-29 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
US6444295B1 (en) * 1998-12-29 2002-09-03 Industrial Technology Research Institute Method for improving integrated circuits bonding firmness
US6252300B1 (en) * 1999-01-14 2001-06-26 United Microelectronics Corp. Direct contact through hole type wafer structure
US6320263B1 (en) * 1999-02-18 2001-11-20 Advanced Micro Devices, Inc. Semiconductor metalization barrier and manufacturing method therefor
US6633087B2 (en) * 1999-03-19 2003-10-14 Industrial Technology Research Institute Low-capacitance bonding pad for semiconductor device
US6448641B2 (en) * 1999-03-19 2002-09-10 Industrial Technology Research Institute Low-capacitance bonding pad for semiconductor device
US6358847B1 (en) * 1999-03-31 2002-03-19 Lam Research Corporation Method for enabling conventional wire bonding to copper-based bond pad features
US6133136A (en) * 1999-05-19 2000-10-17 International Business Machines Corporation Robust interconnect structure
US6249038B1 (en) * 1999-06-04 2001-06-19 International Business Machines Corporation Method and structure for a semiconductor fuse
US6551916B2 (en) * 1999-06-08 2003-04-22 Winbond Electronics Corp. Bond-pad with pad edge strengthening structure
US6329722B1 (en) * 1999-07-01 2001-12-11 Texas Instruments Incorporated Bonding pads for integrated circuits having copper interconnect metallization
US6451681B1 (en) * 1999-10-04 2002-09-17 Motorola, Inc. Method of forming copper interconnection utilizing aluminum capping film
US6350667B1 (en) * 1999-11-01 2002-02-26 Taiwan Semiconductor Manufacturing Company Method of improving pad metal adhesion
US20010051426A1 (en) * 1999-11-22 2001-12-13 Scott K. Pozder Method for forming a semiconductor device having a mechanically robust pad interface.
US6306750B1 (en) * 2000-01-18 2001-10-23 Taiwan Semiconductor Manufacturing Company Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060131748A1 (en) * 2000-06-28 2006-06-22 Krishna Seshan Ball limiting metallurgy split into segments
US20050073058A1 (en) * 2003-10-07 2005-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package bond pad having plurality of conductive members
US7372153B2 (en) * 2003-10-07 2008-05-13 Taiwan Semiconductor Manufacturing Co., Ltd Integrated circuit package bond pad having plurality of conductive members
US20050233570A1 (en) * 2003-12-17 2005-10-20 Bohr Mark T Method and apparatus for improved power routing
US7180195B2 (en) * 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
US7208402B2 (en) * 2003-12-17 2007-04-24 Intel Corporation Method and apparatus for improved power routing
US20050133894A1 (en) * 2003-12-17 2005-06-23 Bohr Mark T. Method and apparatus for improved power routing
US20070262447A1 (en) * 2006-05-15 2007-11-15 Matsushita Electric Industrial Co., Ltd. Circuit board, method for manufacturing the same, and semiconductor device
US8063486B2 (en) * 2006-05-15 2011-11-22 Panasonic Corporation Circuit board, method for manufacturing the same, and semiconductor device
US20110140191A1 (en) * 2009-12-15 2011-06-16 Semiconductor Manufacturing International (Shanghai) Corporation Method for manufacturing twin bit structure cell with silicon nitride layer
US9064804B2 (en) * 2009-12-15 2015-06-23 Semiconductor Manufacturing International (Shanghai) Corporation Method for manufacturing twin bit structure cell with silicon nitride layer
US20120306084A1 (en) * 2011-06-06 2012-12-06 Micron Technology, Inc. Semiconductor Constructions Having Through-Substrate Interconnects, and Methods of Forming Through-Substrate Interconnects
CN103582933A (en) * 2011-06-06 2014-02-12 美光科技公司 Semiconductor constructions having through-substrate interconnects, and methods of forming through-substrate interconnects
US9583419B2 (en) * 2011-06-06 2017-02-28 Micron Technology, Inc. Semiconductor constructions having through-substrate interconnects
US8853072B2 (en) * 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
US20170125342A1 (en) * 2011-06-06 2017-05-04 Micron Technology, Inc. Semiconductor Constructions
US20150130029A1 (en) * 2011-06-06 2015-05-14 Micron Technology, Inc. Semiconductor Constructions Having Through-Substrate Interconnects
CN103582933B (en) * 2011-06-06 2017-02-15 美光科技公司 The semiconductor structure having a through-substrate interconnect and method for forming through-substrate interconnect
US8420531B2 (en) 2011-06-21 2013-04-16 International Business Machines Corporation Enhanced diffusion barrier for interconnect structures
US8742581B2 (en) 2011-06-21 2014-06-03 International Business Machines Corporation Enhanced diffusion barrier for interconnect structures
US20150041208A1 (en) * 2013-08-07 2015-02-12 Invensas Corporation Micro mechanical anchor for 3d architecture
US9832887B2 (en) * 2013-08-07 2017-11-28 Invensas Corporation Micro mechanical anchor for 3D architecture

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