US6985055B2 - Transmission line comprised of interconnected parallel line segments - Google Patents

Transmission line comprised of interconnected parallel line segments Download PDF

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Publication number
US6985055B2
US6985055B2 US10403007 US40300703A US6985055B2 US 6985055 B2 US6985055 B2 US 6985055B2 US 10403007 US10403007 US 10403007 US 40300703 A US40300703 A US 40300703A US 6985055 B2 US6985055 B2 US 6985055B2
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line
level
lines
signal lines
signal
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US20040090282A1 (en )
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Fumihiro Minami
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Toshiba Corp
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Toshiba Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/003Coplanar lines
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/02Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08Microstrips; Strip lines
    • H01P3/088Stacked transmission lines
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6627Waveguides, e.g. microstrip line, strip line, coplanar line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transmission line, includes: a first input electrode located in a first level; a plurality of parallel stripe-shaped signal lines in the first level, one end of the signal lines connected to the first input electrode; a first output electrode connected to another end of the signal lines, facing to the first input electrode; a second input electrode adjacent to the first input electrode in a second level facing the first level; a plurality of stripe-shaped ground lines positioned alternately in between and at outer sides of each of the signal lines in the first level, one end of the ground lines connected to the second input electrode; and a second output electrode adjacent to the first output electrode in the second level and connected to another end of the ground lines.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2002-324021 filed on Nov. 7, 2002; the entire contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a transmission line for high-speed signals in semiconductor integrated circuits, and a semiconductor device using the same.

2. Description of the Related Art

In recent years, speeds of semiconductor integrated circuits have been increasing, whereby microprocessors that operate at a clock speed of several GHz and high frequency circuits operating at several GHz have been achieved. The prevention of a cross talk between signal lines and attention for a high frequency signal response including line inductance are necessary for transmitting signals in a semiconductor integrated circuit at a GHz level. A coplanar waveguide or a microstrip line is a representative transmission line for transmitting high frequency signals.

An example of applying the coplanar waveguide to a clock line in a semiconductor integrated circuit has been reported (see F. Ishihara, Proceedings of ASP-DAC2000, pp. 647–652, 2000).

Furthermore, the microstrip line is generally applied to a printed board and the like. There is also an example of a structure of the microstrip line for reducing parasitic capacitance in a semiconductor integrated circuit (see M. Mizuno, IEEE ISSCC 2000, pp. 366–367, 2002).

A line width may be increased in order to decrease the line impedance for ultra high-speed signal transmission. However, by increasing the line width, a coupling effect between signal lines in the upper and lower layers relatively increases, and an effect of cross talk noise becomes a problem. Furthermore, an error may increase in the line impedance of additional signal lines predicted prior to wiring processing.

In the microstrip line, a ground plane that forms a return path requires a large amount of wiring resources, and may be a large obstacle for general signal lines.

SUMMARY OF THE INVENTION

A first aspect of the present invention lies in a transmission line, and includes: a first input electrode located in a first level; a plurality of parallel stripe-shaped signal lines in the first level, one end of the signal lines connected to the first input electrode; a first output electrode connected to another end of the signal lines, facing to the first input electrode; a second input electrode adjacent to the first input electrode in a second level facing the first level; a plurality of stripe-shaped ground lines positioned alternately in between and at outer sides of each of the signal lines in the first level, one end of the ground lines connected to the second input electrode; and a second output electrode adjacent to the first output electrode in the second level and connected to another end of the ground lines.

A second aspect of the present invention lies in a transmission line, and includes: a first signal line located in a first level; a first ground line located in a second level facing the first level, the first ground line parallel to and facing the first signal line, and having a separated section at least at one portion; and bridge ground lines located in the first level on both sides of the first signal line overlaying the separated section, and connected respectively to one separated end and another separated end of the first ground line.

A third aspect of the present invention lies in a semiconductor device, and includes: a route line having a first microstrip line configuration, being connecting a route driver cell to a route relay buffer cell, the route driver cell receiving signals to be supplied to a terminal circuit; a route branch line having a second microstrip line configuration, being branched from the route relay buffer cell and connected to a first relay buffer cell; and a relay branch line having a coplanar waveguide configuration, being branched from the first relay buffer cell and connected to a second relay buffer cell for supplying the signals to the circuit.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram of a coplanar waveguide according to a first embodiment of the present invention;

FIGS. 2A and 2B are cross-sections of the coplanar waveguide according to the first embodiment of the present invention;

FIG. 3 is a schematic diagram of a microstrip line according to a second embodiment of the present invention;

FIG. 4 is a cross-section of the microstrip line according to the second embodiment of the present invention;

FIG. 5 is a schematic diagram describing a transmission line in a semiconductor device according to a third embodiment of the present invention; and

FIG. 6 is a schematic diagram illustrating an example of the transmission line in the semiconductor device according to the third embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.

First Embodiment

A coplanar waveguide according to a first embodiment of the present invention, as shown in FIG. 1, has a plurality of stripe-shaped signal lines 21 a, 21 b, 21 c, 21 d, located in parallel between a plurality of stripe-shaped ground lines 22 a, 22 b, 22 c, 22 d, 22 e in a first level. The signal lines 21 a, 21 b, 21 c, 21 d are, for example, connected at one end to a first input electrode 23 on the left-hand side facing the page of FIG. 1 and connected at another end to a first output electrode 25 on the right-hand side facing the page in the first level. The ground lines 22 a, 22 b, 22 c, 22 d, 22 e are connected at one end to a second input electrode 24, which is positioned adjacent to the first input electrode 23, and at another end to a second output electrode 26, which is positioned adjacent to the first output electrode 25, and in contact with first plugs 32 a, 32 b, 32 c, 32 d, 32 e and second plugs 34 a, 34 b, 34 c, 34 d 34 e, respectively, in a second level that faces the first level where the signal lines 21 a, 21 b, 21 c, 21 d and ground lines 22 a, 22 b, 22 c, 22 d, 22 e are positioned. Furthermore, first and second input terminals 27 and 28 are provided to the first and second input electrodes 23 and 24, respectively; and first and second output terminals 29 and 30 are provided to the first and second output electrodes 25 and 26, respectively. The first and second input terminals 27 and 28 are connected to a circuit on a signal transmission side; and the first and second output terminals 29 and 30 are connected to a circuit on a signal reception side.

The structure of the coplanar waveguide according to the first embodiment of the present invention is described using FIGS. 2A and 2B, which are cross-sections cut along the lines IIA—IIA and IIB—IIB in FIG. 1, respectively. For convenience of description, a second interlayer insulating film 15 is shown as the uppermost layer of multi-level interlayer insulating films provided on a semiconductor substrate 11 as shown in FIGS. 2A and 2B, however, interlayer insulating films may be further provided on the second interlayer insulating film 15. Furthermore, the second input electrode 24 and second output electrode 26 are provided on a surface of a first interlayer insulating film 13, which is an underlying layer adjacent to the second interlayer insulating film 15. Needless to say, however, the second input electrode 24 (FIG. 2A) and second output electrode 26 (not shown in FIG. 2A) may be provided on a surface of another interlayer insulating film further underlying the first interlayer insulating film 13, or the second input electrode 24 and second output electrode 26 may be provided on a surface of an interlayer insulating film provided on an upper layer of the second interlayer insulating film 15.

As shown in FIG. 2B, the plurality of signal lines 21 a, 21 b, 21 c, 21 d of a line width wc and a line thickness t are alternately disposed with the ground lines 22 a, 22 b, 22 c, 22 d, 22 e at intervals of a gap width s on a surface of the second interlayer insulating film 15 that is deposited on the first interlayer insulating film 13. The insulating films may be a silicon oxide (SiO2) film and the like on the semiconductor substrate 11. The signal lines 21 a, 21 b, 21 c, 21 d are connected to the first input electrode 23 and first output electrode 25 at the surface of the second interlayer insulating film 15. On the other hand, the ground lines 22 a, 22 b, 22 c, 22 d, 22 e are connected to the second input electrode 24 and second output electrode 26, which are provided on another surface that faces the surface of the second interlayer insulating film 15 such as the first interlayer insulating film 13, so as to avoid a short circuit with the signal lines 21 a, 21 b, 21 c, 21 d. For example, as shown in FIG. 2A, the ground lines 22 a, 22 b, 22 c, 22 d, 22 e are connected to the second input electrode 24, which is disposed on the surface of the first interlayer insulating film 13, via the first plugs 32 a, 32 b, 32 c, 32 d, 32 e that are buried in contact holes provided in the second interlayer insulating film 15.

In the coplanar waveguide according to the first embodiment of the present invention, the electromagnetic coupling between the parallel signal lines 21 a, 21 b, 21 c, 21 d and ground lines 22 a, 22 b, 22 c, 22 d, 22 e becomes relatively stronger. Accordingly, it is possible to provide a coplanar waveguide which is substantially unaffected by noise due to cross talk from wiring layers underlying the second interlayer insulating film 15 or wiring layers deposited on the second interlayer insulating film 15. Furthermore, in a coplanar waveguide having three coplanar conductors, a current flows mostly near a surface in each of the coplanar conductors due to a skin effect in a high frequency region and the line resistance exponentially may increase. However, in the coplanar waveguide according to the first embodiment of the present invention, since the signal lines 21 a, 21 b, 21 c, 21 d and ground lines 22 a, 22 b, 22 c, 22 d, 22 e are divided into a plurality of parallel transmission lines, increases in line resistance may be avoided. Furthermore, in order to make the most use of the advantages of the coplanar waveguide according to the first embodiment of the present invention and to save as much wiring resources as possible, for the line thickness t of the signal lines 21 a, 21 b, 21 c, 21 d, the line width wc of the signal lines 21 a, 21 b, 21 c, 21 d and the ground lines 22 a, 22 b, 22 c, 22 d, 22 e may be less than twice the line thickness t, and the gap width s less than the line thickness t.

Second Embodiment

As shown in FIG. 3, a microstrip line according to a second embodiment of the present invention has a first signal line 41 located in a first level and separated first ground lines 42 a and 42 b located in a second level which faces the first level. In the first level, bridge ground lines 43 a and 43 b, which are provided on both sides of the first signal line 41, are located such that portions of the bridge ground lines 43 a and 43 b face and overlap the first ground lines 42 a and 42 b. The bridge ground line 43 a is connected to the first ground lines 42 a and 42 b via contact with plugs 44 a, 44 b and plugs 44 e, 44 f respectively, which are provided at portions of the integrated circuit that face and overlap the first ground lines 42 a and 42 b. The bridge ground line 43 b is connected to the first ground lines 42 a and 42 b via contact with plugs 44 c, 44 d and plugs 44 g, 44 h respectively, which are provided at portions of the integrated circuit that face and overlap the first ground lines 42 a and 42 b. Accordingly, a first signal line 47, a second signal line 48 and the like can be located between the first ground lines 42 a and 42 b lying under the bridge ground lines 43 a and 43 b.

The structure of the microstrip line according to the second embodiment of the present invention is described using FIG. 4, which is a cross-section cut along the line of IV—IV in FIG. 3. For convenience of description, a second interlayer insulating film 15 is shown as the uppermost layer of a plurality of interlayer insulating films provided on a semiconductor substrate 11 as shown in FIG. 4. Needless to say, however, interlayer insulating films may be further provided on the second interlayer insulating film 15.

As shown in FIG. 4, the first signal line 41 of a line width w and the bridge ground lines 43 a and 43 b on both sides thereof are located on a surface of the second interlayer insulating film 15, which is deposited on the first interlayer insulating film 13 above the semiconductor substrate 11. The bridge ground lines 43 a and 43 b are connected to the first ground line 42 a, which is provided on the first interlayer insulating film 13, in contact with the plugs 44 a, 44 b and the plugs 44 c, 44 d respectively, which are buried in contact holes provided in the second interlayer insulating film 15. The first signal line 41 is separated from the first ground line 42 a by an interlayer distance h. Furthermore, the first and second signal lines 47 and 48 are provided on the surface of the first interlayer insulating film 13.

With the microstrip line according to the second embodiment of the present invention, the separated first ground lines 42 a and 42 b, which face the first signal line 41 extending along the surface of the second interlayer insulating film 15, are connected by the bridge ground lines 43 a and 43 b, which are located on the same surface of the second interlayer insulating film 15 as the first signal line 41. Accordingly, it is possible to connect circuits, which are disposed on both sides of the first ground lines 42 a and 42 b, by the first and second signal lines 47 and 48 with a shorter distance across the first ground lines 42 a and 42 b without detouring. It should be noted that the first signal line 41 and the bridge ground lines 43 a and 43 b provide a coplanar waveguide having a 3-strip structure.

The first ground lines 42 a and 42 b are used as grounds for the microstrip line according to the second embodiment of the present invention instead of the ground planes generally used for microstrip lines. The line width of the first ground lines 42 a and 42 b is greater than or equal to the line width w of the first signal line 41, and less than a value of (w+20*h). The line width of the first ground lines 42 a and 42 b is set so as to assure a return current of approximately 75% to 95% for the microstrip line. Thus, fluctuations in electrical characteristics such as impedance of a transmission line are kept within 10% of the characteristic impedance, allowing for the saving of wiring resources. Furthermore, when a total length of connecting sections with the bridge ground lines 43 a and 43 b is less than 20% of the length of the first ground lines 42 a and 42 b, it is possible to control fluctuations in the characteristic impedance along the length of the transmission line within ±5%.

An example where the first ground lines 42 a and 42 b underlie the first signal line 41 has been illustrated in the second embodiment of the present invention. However, a first ground line may be in an upper layer, or a microstrip line may alternatively be sandwiched by the first ground lines in both the upper and lower layers.

Third Embodiment

A transmission line used in a semiconductor device according to a third embodiment of the present invention is characterized by using in combination a coplanar waveguide and a microstrip line described in the first and second embodiments. Since other elements are the same as in the first and second embodiments, duplicate descriptions are omitted.

As shown in FIG. 5, the transmission line used in the semiconductor device according to the third embodiment of the present invention is, for example, applied for clock signal lines in a logic circuit and the like. To begin with, a clock signal is provided to a route driver cell 60 from a clock signal source, and relayed to a route relay buffer cell 61 from a route line 71, which is a first microstrip line. The clock signal is further propagated from the route relay buffer cell 61 to first relay buffer cells 62 a, 62 b, 62 c, 62 d from route branch lines 72 a, 72 b, 72 c, 72 d, which are second microstrip lines. The branched clock signals are then further propagated from each of the first relay buffer cells 62 a, 62 b, 62 c, 62 d to each of second relay buffer cells 64 a, 64 b, 64 c, 64 d, 64 e, 64 f, 64 g, 64 h, 64 i, 64 j, 64 k, 64 l, 64 m, 64 n, 64 o, 64 p from relay buffer branch lines 74 a, 74 b, 74 c, 74 d, 74 e, 74 f, 74 g, 74 h, 74 i, 74 j, 74 k, 74 l, 74 m, 74 n, 74 o, 74 p, which are coplanar waveguides.

When supplying a signal to many destinations, such as the clock signal lines in a logic circuit and the like, buffer cells for relaying are inserted along the clock signal line so as to distribute the clock signal. The coplanar waveguide according to the first embodiment of the present invention employs a structure of the signal lines and ground lines that are separated in thin lines and positioned in parallel, thus a parasitic capacitance increases and a line resistance also easily increases. Accordingly, the microstrip line according to the second embodiment of the present invention is advantageous to send high-speed clock signals on a GHz level. However, the wiring resources cannot be sufficiently acquired when the microstrip lines are heavily used.

In the semiconductor device according to the third embodiment of the present invention, as shown in FIG. 6 for example, a microstrip line 104 is used in the region near the clock signal source where a signal line 107 a is sparsely located. On the other hand, a coplanar waveguide 102 is used in the region where signal lines 107 b, 107 c, 107 d, 107 e, 107 f are highly dense at the clock signal supply destination. The micro strip line 104 has a clock input buffer cell 100, which provides the clock signal to one end of a first signal line 141 in a first level. First ground lines 142 a and 142 b, which are located in a second level that faces the first level, in which the first signal line 141 is located, are separated, and bridge ground lines 143 a and 143 b are provided on the first level. The signal line 107 a is located under the bridge ground lines 143 a and 143 b.

Another end of the first signal line 141 is connected to a first input electrode 123 of the coplanar waveguide 102 through contact with a relay buffer cell 103. Furthermore, the first ground line 142 b is connected to a second input electrode 124. Second signal lines 121 a, 121 a, 121 b, 121 c, 121 d and second ground lines 122 a, 122 b, 122 c, 122 d, 122 e of the coplanar waveguide 102 are formed on the first level. Accordingly, multiple signal interconnects 107 b, 107 c, 107 d, 107 e, 107 f may be positioned under the coplanar waveguide 102. The second signal lines 121 a, 121 b, 121 c, 121 d and second ground lines 122 a, 122 b, 122 c, 122 d, 122 e are connected at another end on the opposite side of the microstrip line 104 to a first output electrode 125 and a second output electrode 126. The first output electrode 125 is further connected to a clock output buffer cell 101, supplying the clock signal to other, nearby circuits.

According to the transmission lines of the semiconductor device of the third embodiment of the present invention, deterioration of signal propagation characteristics may be reduced and the wiring resource consumption may be reduced. Here, when the characteristic impedance and the line resistance per unit length of the coplanar waveguide according to the first embodiment are respectively designated as Zc and Ro, the length of the coplanar waveguide may be determined so as to be less than a value of (2*Zc/Ro). The signals to be propagated may drastically attenuate, when the length of the coplanar waveguide become longer than the value of (2*Zc/Ro).

Other Embodiments

The present invention has been described as discussed above, however the descriptions and drawings that constitute a portion of this disclosure should not be perceived as limiting this invention. Various alternative embodiments and operational techniques will become clear to persons skilled in the art from this disclosure

In the first through third embodiments of the present invention, an insulating film such as SiO2 and the like has been illustrated as the first and the second interlayer insulating films 13, 15. However, an insulating film such as a silicon nitride (Si3N4) film or an alumina (Al2O3) film, for example, may be used. Additionally, even with interlayer insulating films having an wiring structure including electrical conducting layers such as polysilicon films, amorphous silicon films, metal films or the like, the same results may be achieved.

Furthermore, the coplanar waveguide according to the first embodiment of the present invention may be applied to a differential signal line. Namely, a pulse signal is provided to one end of the coplanar waveguide, while a differential pulse signal is provided to another end. Since the pulse signals of opposite polarity are transmitted among adjacent lines, electromagnetic coupling is relatively strengthened, making it more difficult to be affected by a noise due to cross talk from other wiring layers.

Claims (2)

1. A transmission line, comprising:
a first input electrode located in a first level;
a plurality of parallel stripe-shaped signal lines positioned in the first level, one end of the signal lines connected to the first input electrode;
a first output electrode connected to an opposite end of the signal lines from the first input electrode;
a second input electrode adjacent to the first input electrode in a second level facing the first level;
a plurality of stripe-shaped ground lines positioned in the first level, the ground lines located alternately in between and at outer sides of each of the signal lines in the first level, one end of the ground lines connected to the second input electrode; and
a second output electrode adjacent to the first output electrode in the second level and connected to another end of the ground lines.
2. The transmission line of claim 1, wherein line widths of the signal lines and the ground lines are respectively less than twice a line thickness of the signal lines, and gap widths between the signal lines and the ground lines are less than the line thickness of the signal lines.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080231393A1 (en) * 2007-03-21 2008-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure design for minimizing on-chip interconnect inductance
US20120313736A1 (en) * 2011-06-09 2012-12-13 International Business Machines Corporation On-chip slow-wave through-silicon via coplanar waveguide structures, method of manufacture and design structure

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* Cited by examiner, † Cited by third party
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3846721A (en) * 1973-08-08 1974-11-05 Amp Inc Transmission line balun
JPH0522001A (en) 1991-07-15 1993-01-29 Fujitsu Ltd Transmission line structure
JPH0725601A (en) 1993-07-12 1995-01-27 Mitsubishi Heavy Ind Ltd Electric oven for decomposing methane and method for decomposing methane
JPH07135407A (en) 1993-11-11 1995-05-23 Nippon Telegr & Teleph Corp <Ntt> High frequency line
JPH10229130A (en) 1997-02-13 1998-08-25 Nec Corp Method and device for layout
US5922650A (en) * 1995-05-01 1999-07-13 Com Dev Ltd. Method and structure for high power HTS transmission lines using strips separated by a gap
JPH11282592A (en) 1998-03-27 1999-10-15 Japan Aviation Electronics Ind Ltd Transmission line for differential signal
JP2001094011A (en) 1999-09-20 2001-04-06 Nec Corp Semiconductor integrated circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3846721A (en) * 1973-08-08 1974-11-05 Amp Inc Transmission line balun
JPH0522001A (en) 1991-07-15 1993-01-29 Fujitsu Ltd Transmission line structure
JPH0725601A (en) 1993-07-12 1995-01-27 Mitsubishi Heavy Ind Ltd Electric oven for decomposing methane and method for decomposing methane
JPH07135407A (en) 1993-11-11 1995-05-23 Nippon Telegr & Teleph Corp <Ntt> High frequency line
US5922650A (en) * 1995-05-01 1999-07-13 Com Dev Ltd. Method and structure for high power HTS transmission lines using strips separated by a gap
JPH10229130A (en) 1997-02-13 1998-08-25 Nec Corp Method and device for layout
JPH11282592A (en) 1998-03-27 1999-10-15 Japan Aviation Electronics Ind Ltd Transmission line for differential signal
JP2001094011A (en) 1999-09-20 2001-04-06 Nec Corp Semiconductor integrated circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Fujio Ishihara, et al., "Clock Design of 300 MHZ 128-BIT 2-Way Superscalar Microprocessor", Proceedings of ASP-DAC, 2000, 4 Pages.
Masayuki Mizuno, et al., "On-Chip Multi-GHZ Clocking With Transmission Lines", IEEE ISSCC, 2000, pp. 366-367.

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080231393A1 (en) * 2007-03-21 2008-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure design for minimizing on-chip interconnect inductance
US7705696B2 (en) * 2007-03-21 2010-04-27 Taiwan Semiconductor Manufacturing Co., Ltd. Structure design for minimizing on-chip interconnect inductance
US20100194501A1 (en) * 2007-03-21 2010-08-05 Taiwan Semiconductor Manufacturing Co., Ltd. Structure design for minimizing on-chip interconnect inductance
CN101271882B (en) 2007-03-21 2010-11-10 台湾积体电路制造股份有限公司 The semiconductor element
US7952453B2 (en) 2007-03-21 2011-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Structure design for minimizing on-chip interconnect inductance
US20120313736A1 (en) * 2011-06-09 2012-12-13 International Business Machines Corporation On-chip slow-wave through-silicon via coplanar waveguide structures, method of manufacture and design structure
US8963657B2 (en) * 2011-06-09 2015-02-24 International Business Machines Corporation On-chip slow-wave through-silicon via coplanar waveguide structures, method of manufacture and design structure

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JP3660338B2 (en) 2005-06-15 grant
JP2004159174A (en) 2004-06-03 application
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