US6929962B1 - System and method for wafer acceptance test configuration - Google Patents

System and method for wafer acceptance test configuration Download PDF

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US6929962B1
US6929962B1 US10/811,190 US81119004A US6929962B1 US 6929962 B1 US6929962 B1 US 6929962B1 US 81119004 A US81119004 A US 81119004A US 6929962 B1 US6929962 B1 US 6929962B1
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wat
model
qualification criteria
preset
test
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Yung-Cheng Chang
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41875—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by quality surveillance of production
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/32—Operator till task planning
    • G05B2219/32201—Build statistical model of past normal proces, compare with actual process
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the invention described herein relates to a Wafer Acceptance Test (WAT) and more specifically to WAT configuration.
  • WAT Wafer Acceptance Test
  • Wafer-level electrical testing plays an important role in wafer manufacture, particularly as the cost for post-processes, such as packaging and testing, has increased rapidly. A defective wafer is identified by the testing and disposed of before it undergoes the post-processes.
  • the WAT includes numerous testing items and is crucial for wafer manufacture.
  • WAT is performed as defined by a preset WAT model, which specifies a constant number of test sites for wafers of specific size. For example, the preset WAT model specifies 5 test sites for an 8-inch wafer, and 9 test sites for a 12-inch wafer.
  • the preset WAT model specifies 5 test sites for an 8-inch wafer, and 9 test sites for a 12-inch wafer.
  • the present invention provides a system and method for configuring WAT (Wafer Acceptance Test) according to customer requirements.
  • a system for WAT configuration comprises an input/output device, a storage device, and a processor.
  • the input/output device receives a first WAT model and qualification criteria.
  • the storage device stores a preset WAT model and qualification criteria.
  • the processor modifies the preset WAT model according to the first WAT model to generate a second WAT model, and modifies the preset qualification criteria according to the first qualification criteria to generate second qualification criteria.
  • the present invention also provides a method, implemented in the aforementioned system, for WAT configuration.
  • a preset WAT model and qualification criteria, and first WAT model and qualification criteria are provided.
  • the preset WAT model is modified according to the first WAT model to generate a second WAT model, which is then transformed into a test program operable on a selected target WAT platform.
  • the preset qualification criteria are modified according to the first qualification criteria to generate second qualification criteria, used for wafer quality control.
  • the above-mentioned method may take the form of program code embodied in a tangible media.
  • the program code When the program code is loaded into and executed by a machine, the machine becomes an apparatus for practicing the invention.
  • FIG. 1 is a schematic view of a WAT configuration system according to the present invention
  • FIG. 2 is a flowchart showing a method for WAT configuration according to the present invention
  • FIGS. 3A to 3C show the data structure according to the present invention.
  • FIG. 4 is a diagram of a storage medium for storing a computer program providing the WAT configuration method.
  • FIGS. 1 to 4 which in general relate to a WAT configuration system.
  • FIG. 1 is a schematic view of a WAT configuration system according to the present invention.
  • the WAT configuration system 10 provides functionality for receiving a WAT requirement and generating a customized WAT configuration accordingly, including a WAT model and corresponding qualification criteria.
  • the WAT configuration system 10 includes an input/output device 101 , a processor 103 , a storage device 105 , a WAT control server 106 , a quality control server 107 , and an engineering support server 108 .
  • the WAT configuration system 10 communicates with an engineering interface 11 and a WAT tool 14 through the input/output device 101 , wherein the engineering interface communicates with a client interface 13 through a network 12 .
  • the engineering interface 11 and the client interface 13 may be personal computers capable of connecting to a network.
  • the network 12 is a data network such as the World Wide Web through which personnel in charge of WAT may communicate with the client interface 13 .
  • the client interface 13 is used to receive original WAT requirements.
  • the client interface 13 in the preferred embodiment, utilizes a graphical user interface (GUI).
  • GUI graphical user interface
  • the engineering interface 11 receives the original WAT requirements from the client interface 13 , modifies the original WAT requirements according to a preset rule, and transfers the modified WAT requirements to the WAT configuration system 10 .
  • the WAT configuration system 10 receives the modified WAT requirements from the engineering interface 11 through the input/output device 101 and transfers it to the processor 103 .
  • the WAT requirements specify a WAT model and qualification criteria of corresponding wafers.
  • the processor 103 retrieves a preset WAT model and qualification criteria from the storage device 105 , modifies them according to the WAT requirements, and generates a customized WAT model and qualification criteria accordingly.
  • the WAT control server 106 generates a WAT program immediately as the customized WAT model is fed in, wherein the WAT program conforms to the WAT model and is operable on a selected target WAT platform.
  • the target WAT platform performs WAT according to the WAT model.
  • the WAT inspects a variety of test sites as defined by the customized WAT model.
  • the quality control server 107 receives the customized qualification criteria and examines the WAT results accordingly to determine whether the wafers conform to the corresponding requirement.
  • the engineering support server 108 receives results of the quality examination and generate
  • FIG. 2 is a flowchart which provides a general description of a method for WAT configuration in the aforementioned WAT configuration system.
  • preset WAT models and qualification criteria are provided (step S 21 ).
  • the preset WAT models specify WAT settings, such as number of test sites. Generally, the number of sites are 5 and 9 for 8-inch and 12-inch, respectively.
  • the preset qualification criteria specify an acceptance quality level of wafers.
  • the above-mentioned preset information is stored in the storage device 105 .
  • first WAT model and qualification criteria are provided.
  • the first WAT model and qualification criteria are derived from original WAT requirements of a client and stored in the storage device 105 .
  • the second WAT model and qualification criteria can be stored in any format to meet particular needs. According to the preferred embodiment, the above-mentioned information is stored in the format illustrated in FIG. 3A .
  • FIG. 3A shows a table 30 , stored in storage device 105 , storing information used to identify the wafer and corresponding WAT configuration, including: client name (field 301 ), product ID (field 302 ), fabricating plant ID (field 303 ), number of test sites (field 304 ), and acceptance criteria of different test items (fields 305 to 308 ).
  • the second WAT model is transformed into a test program operable on a selected target WAT platform (step S 25 ).
  • the second WAT model is derived from the original WAT requirements and used to control a testing tool, thus the WAT is customized (step S 26 ).
  • the WAT is performed as defined by the second WAT model, and the result thereof is used for a quality examination.
  • the WAT result can be stored in any format to meet particular needs. According to the preferred embodiment, the WAT result is stored in the format illustrated in FIG. 3B .
  • FIG. 3B shows a table 31 , stored in storage device 105 , storing identification information of the wafer and corresponding WAT results, including: wafer lot ID (field 311 ), product ID (field 312 ), wafer ID (field 313 ), number of test sites (field 314 ), key parameter of the test item (field 315 ), test result of each test site (fields 316 a to 316 n ).
  • the client can define a specific number of test sites in the original WAT requirement, which can be 5, 9, 13 sites or full map and is confirmed or revised by the engineering interface according to a preset rule.
  • a quality report is generated according to the second qualification criteria, the WAT result, and the quality examination result.
  • the quality report can be stored in any format to meet particular needs. According to the preferred embodiment, the above-mentioned report is stored in the formats illustrated in FIG. 3C .
  • 3C shows a table 33 , stored in storage device 105 , comprising the identification information of the wafer and corresponding qualification levels, including: wafer lot ID (field 331 ), product ID (field 332 ), wafer ID (field 333 ), number of test sites (field 334 ), result of quality examination for different test items (fields 335 a to 335 n ), and final acceptance decision (field 336 ).
  • the final acceptance decision specifies the disposition of wafers according to results of quality examination thereof.
  • a final report is generated and sent to the clients as defined by a preset format (step S 27 ).
  • the final report is generated simultaneously as the results of WAT and quality examination are fed in.
  • the method of the present invention may take the form of program code (i.e. instructions) embodied in a tangible media, such as floppy diskettes, CD-ROMS, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
  • the methods and apparatus of the present invention may also be embodied in the form of program code transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
  • the program code When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to specific logic circuits.
  • FIG. 4 is a diagram of a storage medium for storing a computer program providing the WAT configuration method according to the present invention.
  • the computer program product comprises a computer usable storage medium having computer readable program code embodied in the medium, the computer readable program code comprising computer readable program code 41 receiving information, computer readable program code 43 modifying a preset WAT model according to a first WAT model to generate a second WAT model, and computer readable program code 45 modifying preset qualification criteria according to first qualification criteria to generate second qualification criteria.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Quality & Reliability (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • General Factory Administration (AREA)

Abstract

A system for WAT (Wafer Acceptance Test) configuration. The system comprises an input/output device, a storage device, and a processor. The input/output device receives a first WAT model and qualification criteria. The storage device stores a preset WAT model and qualification criteria. The processor modifies the preset WAT model according to the first WAT model to generate a second WAT model, and modifies the preset qualification criteria according to the first qualification criteria to generate second qualification criteria.

Description

BACKGROUND
The invention described herein relates to a Wafer Acceptance Test (WAT) and more specifically to WAT configuration.
Wafer-level electrical testing plays an important role in wafer manufacture, particularly as the cost for post-processes, such as packaging and testing, has increased rapidly. A defective wafer is identified by the testing and disposed of before it undergoes the post-processes. The WAT includes numerous testing items and is crucial for wafer manufacture.
In conventional foundry service, WAT is performed as defined by a preset WAT model, which specifies a constant number of test sites for wafers of specific size. For example, the preset WAT model specifies 5 test sites for an 8-inch wafer, and 9 test sites for a 12-inch wafer. Recently, great advances have been made in wafer manufacturing, and more specific testing has been required to determine product quality. Different WAT models and acceptance criteria are required for different products. Therefore, the standardized WAT configuration cannot satisfy various test requirements of different products. Whenever specific WAT models or acceptance criteria are required, manual intervention is required to confirm the specific test requirement, modify the standard WAT configuration and generate a customized report after the WAT is accomplished as defined by the customized WAT configuration.
Hence, there is a need for a WAT configuration system that addresses the problems arising from the existing technology.
SUMMARY
It is therefore an object of the invention to provide a system and method performing customized WAT in a foundry. To achieve this and other objects, the present invention provides a system and method for configuring WAT (Wafer Acceptance Test) according to customer requirements.
According to the present invention, a system for WAT configuration is provided. The system comprises an input/output device, a storage device, and a processor. The input/output device receives a first WAT model and qualification criteria. The storage device stores a preset WAT model and qualification criteria. The processor modifies the preset WAT model according to the first WAT model to generate a second WAT model, and modifies the preset qualification criteria according to the first qualification criteria to generate second qualification criteria.
The present invention also provides a method, implemented in the aforementioned system, for WAT configuration. First, a preset WAT model and qualification criteria, and first WAT model and qualification criteria are provided. Then, the preset WAT model is modified according to the first WAT model to generate a second WAT model, which is then transformed into a test program operable on a selected target WAT platform. In addition, the preset qualification criteria are modified according to the first qualification criteria to generate second qualification criteria, used for wafer quality control.
The above-mentioned method may take the form of program code embodied in a tangible media. When the program code is loaded into and executed by a machine, the machine becomes an apparatus for practicing the invention.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 is a schematic view of a WAT configuration system according to the present invention;
FIG. 2 is a flowchart showing a method for WAT configuration according to the present invention;
FIGS. 3A to 3C show the data structure according to the present invention; and
FIG. 4 is a diagram of a storage medium for storing a computer program providing the WAT configuration method.
 DETAILED DESCRIPTION
The present invention will now be described with reference to FIGS. 1 to 4, which in general relate to a WAT configuration system.
FIG. 1 is a schematic view of a WAT configuration system according to the present invention. The WAT configuration system 10 provides functionality for receiving a WAT requirement and generating a customized WAT configuration accordingly, including a WAT model and corresponding qualification criteria.
The WAT configuration system 10 includes an input/output device 101, a processor 103, a storage device 105, a WAT control server 106, a quality control server 107, and an engineering support server 108. The WAT configuration system 10 communicates with an engineering interface 11 and a WAT tool 14 through the input/output device 101, wherein the engineering interface communicates with a client interface 13 through a network 12. The engineering interface 11 and the client interface 13 may be personal computers capable of connecting to a network. The network 12 is a data network such as the World Wide Web through which personnel in charge of WAT may communicate with the client interface 13.
The client interface 13 is used to receive original WAT requirements. The client interface 13, in the preferred embodiment, utilizes a graphical user interface (GUI).
The engineering interface 11 receives the original WAT requirements from the client interface 13, modifies the original WAT requirements according to a preset rule, and transfers the modified WAT requirements to the WAT configuration system 10.
The WAT configuration system 10 receives the modified WAT requirements from the engineering interface 11 through the input/output device 101 and transfers it to the processor 103. The WAT requirements specify a WAT model and qualification criteria of corresponding wafers. The processor 103 retrieves a preset WAT model and qualification criteria from the storage device 105, modifies them according to the WAT requirements, and generates a customized WAT model and qualification criteria accordingly. The WAT control server 106 generates a WAT program immediately as the customized WAT model is fed in, wherein the WAT program conforms to the WAT model and is operable on a selected target WAT platform. The target WAT platform performs WAT according to the WAT model. The WAT inspects a variety of test sites as defined by the customized WAT model. The quality control server 107 receives the customized qualification criteria and examines the WAT results accordingly to determine whether the wafers conform to the corresponding requirement. The engineering support server 108 receives results of the quality examination and generates a report immediately as the qualification results are fed in.
FIG. 2 is a flowchart which provides a general description of a method for WAT configuration in the aforementioned WAT configuration system. First, preset WAT models and qualification criteria are provided (step S21). The preset WAT models specify WAT settings, such as number of test sites. Generally, the number of sites are 5 and 9 for 8-inch and 12-inch, respectively. The preset qualification criteria specify an acceptance quality level of wafers. The above-mentioned preset information is stored in the storage device 105.
Second, first WAT model and qualification criteria are provided. The first WAT model and qualification criteria are derived from original WAT requirements of a client and stored in the storage device 105.
Next, the preset WAT model and qualification criteria are modified according to the first WAT model and qualification criteria to generate a second WAT model and qualification criteria (step S23). The second WAT model and qualification criteria can be stored in any format to meet particular needs. According to the preferred embodiment, the above-mentioned information is stored in the format illustrated in FIG. 3A. FIG. 3A shows a table 30, stored in storage device 105, storing information used to identify the wafer and corresponding WAT configuration, including: client name (field 301), product ID (field 302), fabricating plant ID (field 303), number of test sites (field 304), and acceptance criteria of different test items (fields 305 to 308).
After the second WAT model and qualification criteria are generated, the second WAT model is transformed into a test program operable on a selected target WAT platform (step S25). As mentioned above, the second WAT model is derived from the original WAT requirements and used to control a testing tool, thus the WAT is customized (step S26).
The WAT is performed as defined by the second WAT model, and the result thereof is used for a quality examination. The WAT result can be stored in any format to meet particular needs. According to the preferred embodiment, the WAT result is stored in the format illustrated in FIG. 3B. FIG. 3B shows a table 31, stored in storage device 105, storing identification information of the wafer and corresponding WAT results, including: wafer lot ID (field 311), product ID (field 312), wafer ID (field 313), number of test sites (field 314), key parameter of the test item (field 315), test result of each test site (fields 316 a to 316 n). The client can define a specific number of test sites in the original WAT requirement, which can be 5, 9, 13 sites or full map and is confirmed or revised by the engineering interface according to a preset rule. A quality report is generated according to the second qualification criteria, the WAT result, and the quality examination result. The quality report can be stored in any format to meet particular needs. According to the preferred embodiment, the above-mentioned report is stored in the formats illustrated in FIG. 3C. FIG. 3C shows a table 33, stored in storage device 105, comprising the identification information of the wafer and corresponding qualification levels, including: wafer lot ID (field 331), product ID (field 332), wafer ID (field 333), number of test sites (field 334), result of quality examination for different test items (fields 335 a to 335 n), and final acceptance decision (field 336). The final acceptance decision specifies the disposition of wafers according to results of quality examination thereof.
When wafers are delivered to clients, a final report is generated and sent to the clients as defined by a preset format (step S27). The final report is generated simultaneously as the results of WAT and quality examination are fed in.
The method of the present invention, or certain aspects or portions thereof, may take the form of program code (i.e. instructions) embodied in a tangible media, such as floppy diskettes, CD-ROMS, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. The methods and apparatus of the present invention may also be embodied in the form of program code transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to specific logic circuits.
FIG. 4 is a diagram of a storage medium for storing a computer program providing the WAT configuration method according to the present invention. The computer program product comprises a computer usable storage medium having computer readable program code embodied in the medium, the computer readable program code comprising computer readable program code 41 receiving information, computer readable program code 43 modifying a preset WAT model according to a first WAT model to generate a second WAT model, and computer readable program code 45 modifying preset qualification criteria according to first qualification criteria to generate second qualification criteria.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (21)

1. A system for WAT (Wafer Acceptance Test) configuration, comprising:
an input/output device receiving a first WAT model and qualification criteria;
a storage device storing a preset WAT model and qualification criteria; and
a processor modifying the preset WAT model according to the first WAT model to generate a second WAT model, and modifying the preset qualification criteria according to the first qualification criteria to generate qualification criteria.
2. The system of claim 1, further comprising a WAT control mechanism transforming the second WAT model into a test program operable on a selected target WAT platform.
3. The system of claim 1, further comprising a quality control mechanism performing a quality examination according to the second qualification criteria.
4. The system of claim 1, further comprising an engineering support mechanism generating a report according to the second qualification criteria, WAT results, and quality examination results.
5. The system of claim 1, wherein the WAT model specifies number and arrangement of test sites in a WAT.
6. The system of claim 1, wherein the qualification criteria specifies a key parameter.
7. The system of claim 1, wherein the qualification criteria specifies an acceptable quality level.
8. A method for WAT (Wafer Acceptance Test) configuration, comprising:
providing a preset WAT model and qualification criteria;
providing a first WAT model and qualification criteria;
modifying the preset WAT model according to the first WAT model to generate a second WAT model;
modifying the preset qualification criteria according to the first qualification criteria to generate second qualification criteria.
9. The method of claim 8, further comprising transforming the second WAT model into a test program operable on a selected target WAT platform.
10. A method of claim 8, further comprising performing a quality examination based on the second qualification criteria.
11. The method of claim 8, further comprising generating a quality report according to results of the WAT and the quality examination.
12. The method of claim 8, wherein the WAT model specifies number and arrangement of test sites in WAT.
13. The method of claim 8, wherein the qualification criteria specifies a key parameter.
14. The method of claim 8, wherein the qualification criteria specifies an acceptable quality level.
15. A computer readable storage medium storing a computer program providing a method for WAT (Wafer Acceptance Test) configuration, comprising:
receiving preset test and qualification criteria;
receiving first test and qualification criteria;
modifying the preset WAT model according to the first WAT model to generate a second WAT model;
modifying the preset qualification criteria according to the first qualification criteria to generate second qualification criteria.
16. The storage medium of claim 15, wherein the method further comprises transforming the second WAT model into a test program operable on a selected target WAT platform.
17. The storage medium of claim 15, wherein the method further comprises performing a quality examination based on the second qualification criteria.
18. The storage medium of claim 15, wherein the method further comprises generating a quality report according to results of the WAT and the quality examination.
19. The storage medium of claim 15, wherein the WAT model specifies the number and arrangement of test sites in a WAT.
20. The storage medium of claim 15, wherein the qualification criteria specifies a key parameter.
21. The storage medium of claim 15, wherein the qualification criteria specifies an acceptable quality level.
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7359820B1 (en) 2007-01-03 2008-04-15 International Business Machines Corporation In-cycle system test adaptation
US20080275586A1 (en) * 2007-05-04 2008-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Novel Methodology To Realize Automatic Virtual Metrology
US20090157362A1 (en) * 2007-12-18 2009-06-18 Yu-Lin Wu Model modification method for a semiconductor device
US20090319074A1 (en) * 2008-06-23 2009-12-24 International Business Machines Corporation Method for compensating for tool processing variation in the routing of wafers/lots
US20100250172A1 (en) * 2009-03-26 2010-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for implementing wafer acceptance test ("wat") advanced process control ("apc") with routing model
US7851234B2 (en) 2007-11-29 2010-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for enhanced control of copper trench sheet resistance uniformity
US8095230B2 (en) 2008-06-24 2012-01-10 International Business Machines Corporation Method for optimizing the routing of wafers/lots based on yield
CN103645428A (en) * 2013-11-22 2014-03-19 上海华力微电子有限公司 A system and a method for raising the efficiency of a WAT test
US20150253373A1 (en) * 2014-03-04 2015-09-10 Nvidia Corporation Dynamic yield prediction
DE102016100539A1 (en) * 2016-01-09 2017-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. ON-chip oscilloscope
CN118411128A (en) * 2024-07-01 2024-07-30 一智科技有限公司 Engineering construction acceptance sheet generation method, system and storage medium

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586265B2 (en) * 2001-07-26 2003-07-01 Promos Technologies Inc. Method and apparatus of tool matching for a semiconductor manufacturing process
US6615157B1 (en) * 2000-02-25 2003-09-02 Promos Technologies, Inc. System method and computer program product for automatically assessing experiment results

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615157B1 (en) * 2000-02-25 2003-09-02 Promos Technologies, Inc. System method and computer program product for automatically assessing experiment results
US6586265B2 (en) * 2001-07-26 2003-07-01 Promos Technologies Inc. Method and apparatus of tool matching for a semiconductor manufacturing process

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080162995A1 (en) * 2007-01-03 2008-07-03 International Business Machines Corp. In-cycle system test adaptation
US7359820B1 (en) 2007-01-03 2008-04-15 International Business Machines Corporation In-cycle system test adaptation
US8682466B2 (en) * 2007-05-04 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Automatic virtual metrology for semiconductor wafer result prediction
US20080275586A1 (en) * 2007-05-04 2008-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Novel Methodology To Realize Automatic Virtual Metrology
US7851234B2 (en) 2007-11-29 2010-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for enhanced control of copper trench sheet resistance uniformity
US20090157362A1 (en) * 2007-12-18 2009-06-18 Yu-Lin Wu Model modification method for a semiconductor device
US20090319074A1 (en) * 2008-06-23 2009-12-24 International Business Machines Corporation Method for compensating for tool processing variation in the routing of wafers/lots
US8369976B2 (en) 2008-06-23 2013-02-05 International Business Machines Corporation Method for compensating for tool processing variation in the routing of wafers/lots
US8095230B2 (en) 2008-06-24 2012-01-10 International Business Machines Corporation Method for optimizing the routing of wafers/lots based on yield
US20100250172A1 (en) * 2009-03-26 2010-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for implementing wafer acceptance test ("wat") advanced process control ("apc") with routing model
US8219341B2 (en) 2009-03-26 2012-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) with routing model
CN103645428A (en) * 2013-11-22 2014-03-19 上海华力微电子有限公司 A system and a method for raising the efficiency of a WAT test
US20150253373A1 (en) * 2014-03-04 2015-09-10 Nvidia Corporation Dynamic yield prediction
US9470743B2 (en) * 2014-03-04 2016-10-18 Nvidia Corporation Dynamic yield prediction
DE102016100539A1 (en) * 2016-01-09 2017-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. ON-chip oscilloscope
US10161967B2 (en) 2016-01-09 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. On-chip oscilloscope
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US11035886B2 (en) 2016-01-09 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. On-chip oscilloscope
US11567105B2 (en) 2016-01-09 2023-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. On-chip oscilloscope
US11835551B2 (en) 2016-01-09 2023-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. On-chip oscilloscope
CN118411128A (en) * 2024-07-01 2024-07-30 一智科技有限公司 Engineering construction acceptance sheet generation method, system and storage medium

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