US6503835B1 - Method of making an organic copper diffusion barrier layer - Google Patents
Method of making an organic copper diffusion barrier layer Download PDFInfo
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- US6503835B1 US6503835B1 US09/939,606 US93960601A US6503835B1 US 6503835 B1 US6503835 B1 US 6503835B1 US 93960601 A US93960601 A US 93960601A US 6503835 B1 US6503835 B1 US 6503835B1
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- Prior art keywords
- copper
- layer
- dielectric layer
- organic
- barrier layer
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- 239000010949 copper Substances 0.000 title claims abstract description 122
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 121
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 121
- 230000004888 barrier function Effects 0.000 title claims abstract description 53
- 238000009792 diffusion process Methods 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title description 2
- 229920000642 polymer Polymers 0.000 claims abstract description 14
- 125000000524 functional group Chemical group 0.000 claims abstract description 4
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 abstract description 8
- 238000013508 migration Methods 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 description 37
- 239000002184 metal Substances 0.000 description 37
- 230000008569 process Effects 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- COUNCWOLUGAQQG-UHFFFAOYSA-N copper;hydrogen peroxide Chemical compound [Cu].OO COUNCWOLUGAQQG-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002894 organic compounds Chemical group 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- -1 tantalum (Ta) Chemical class 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Definitions
- the present invention relates to a semiconductor structure and process, and more particularly to an organic copper diffusion barrier layer used in a copper damascene structure, which it can defend copper diffusion.
- High-density integrated circuits such as very large scale integration (VLSI) circuits, are typically formed with two or multiple metal interconnects served as three-dimensional wiring line structures to comply with a very high density of devices.
- a multilevel interconnect structure comprises a first metal wiring layer electrically connecting to a source/drain region in a substrate via a metal plug. The electrical connections between various devices are achieved by the formation of a second or other metal wiring layers. The isolations in one metal wiring layer are achieved by the formation of an inter-metal dielectric (IMD) layer, and the electrical connections between two adjacent wiring layers are achieved by forming a plurality of metal via plugs.
- IMD inter-metal dielectric
- Aluminum (Al) is a popularly used conductive material for connecting various devices in conventional semiconductor process because of high conductivity and low cost, and facility of deposition and etching. As the integrated density increases, the capacitance effect between metal wires increases. Consequently, the resistance-capacitance time delay (RC delay time) increases, and cross talk between the metal wires become more frequent. The metal wires thus carries a current flow in a slower speed.
- the parasitic capacitance can be reduced by insulating metal wiring layers with low k (dielectric constant) materials which they are generally lower than 3.5.
- materials with low resistivity are selected for fabricating the metal wires.
- Copper (Cu) having relative high melting point, low resistance (about 1.7 ⁇ -cm) and high electro-migration gradually becomes a new material for replacing aluminum.
- copper has relative high diffusion coefficient. If the copper layers are contacted with dielectric layers, such as silicon dioxide or organic dielectric materials, copper will diffuse into dielectric layers to damage the characteristic of the dielectric layer, and thus forming a leakage.
- a metal barrier layer is generally formed between the copper layer and dielectric layer in one metal wiring layer to defend copper diffusion.
- a dielectric barrier layer is generally formed between upper and lower metal wiring layers to defend copper diffusion from the lower copper layer into upper dielectric layer.
- silicon nitride is generally selected as the dielectric barrier layer, but the inherent properties of silicon nitride with very high dielectric constant of about 7 and low adhesion to copper layer results in poor improvement of RC time delay.
- the present invention provides an organic copper diffusion barrier layer with low dielectric constant, which has good adhesion to copper layer and dielectric layer and can prevent thermal diffusion or electro-migration problems.
- the present invention provides a copper damascene structure adapted for a semiconductor substrate.
- the copper damascene structure comprises a first dielectric layer having an opening on the semiconductor substrate.
- a first copper layer is located in the opening of the first dielectric layer.
- An organic copper diffusion barrier layer including a benzocyclo polymer is located on the first copper layer and the first dielectric layer.
- a second dielectric layer is located on the organic copper diffusion barrier layer.
- a second copper layer is located in the second copper layer, wherein a portion of the second copper layer is connected to the first copper layer through the organic copper diffusion barrier layer.
- the second copper layer can be a dual damascene structure composed of a copper wiring layer and a copper via plug.
- the copper via plug passing through the organic copper diffusion barrier layer is connected to a portion of the first copper layer.
- the present invention provides a method of forming a copper damascene structure.
- the method comprises the following steps.
- a semiconductor substrate is provided.
- a first dielectric layer having an opening is formed over the semiconductor substrate.
- a first copper layer is formed in the opening of the first dielectric layer.
- An organic copper diffusion barrier layer is formed over the first copper layer and the first dielectric layer.
- a second dielectric layer is formed over the organic copper diffusion barrier layer.
- a second copper layer is formed in the second dielectric layer, wherein a portion of the second copper layer is connected to the first copper layer through the organic copper diffusion barrier layer.
- the present invention provides an organic copper diffusion barrier layer.
- the organic diffusion barrier layer is formed on a copper layer, and a dielectric layer is formed thereon.
- the organic diffusion barrier layer comprises a benzocyclo polymer of which having a benzene ring functional group that can defend copper diffusion from the copper layer to the dielectric layer.
- FIGS. 1A-1I are schematic cross-sectional views according to one preferred embodiment of the present invention.
- the present invention provides an organic copper diffusion barrier layer with low dielectric constant, which has good adhesion to copper layer and dielectric layer, and can prevent thermal diffusion or electro-migration problems.
- FIGS. 1A-1I are schematic cross-sectional views according to one preferred embodiment of the present invention.
- a semiconductor substrate 100 such as a p-type silicon wafer with ⁇ 100> lattice structure.
- a plurality of fabricating procedures have been performed on the substrate 100 , and a plurality of semiconductor devices, such as MOS transistor, etc., have been finished on the substrate 100 .
- a first dielectric layer 110 is formed over the whole substrate 100 .
- the first dielectric layer 110 is made of a low dielectric constant (low k) material, which it comprises spin-on polymer, such as FLARE, SiLk, PAE-II, Velox, etc, or spin-on glass (SOG).
- the first dielectric layer 110 can be formed by chemical vapor deposition (CVD), or spin-on coating technologies, etc.
- the dielectric constant of the first dielectric layer 110 is lower than 3.5, even lower than 3.0.
- the first dielectric layer 110 is then patterned to form trench openings 112 in the first dielectric layer 110 to prepare for subsequently forming copper wiring layers.
- the trench openings 112 are generally fabricated by forming a photoresist layer (not shown) on the first dielectric layer, and then patterning the photoresist layer by conventional photolithography process to obtain desired trench pattern on the photoresist layer.
- the first dielectric layer 110 is then anisotropically etched by using the patterned photoresist layer as a mask until the underlying substrate 100 is exposed, to form desired trench openings 112 in the first dielectric layer 110 .
- the patterned photoresist layer is finally removed.
- a metal barrier layer 114 is conformally formed over the substrate 100 .
- the metal barrier layer 114 is composed of a material having low resistivity selected from metal and metal containing compound, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or tungsten (W), etc.
- the metal barrier layer 114 can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes, etc.
- the metal barrier layer 114 is a thin layer having a thickness of about 30-300 angstroms, and conformally inside the trench openings 112 .
- a first copper layer 116 is formed on the metal barrier layer 114 , and fills up the trench openings 112 .
- the first copper layer 116 can be formed by such as sputtering, chemical vapor deposition, or electro-chemical plating technologies, etc.
- a planarizing process is following performed to remove undesired portion on the first dielectric layer 110 .
- the first copper layer 116 can be planarized by, for example, chemical mechanical polishing (CMP) process to remove the undesired portion on the first dielectric layer 110 until the underlying metal barrier layer 114 is exposed.
- CMP chemical mechanical polishing
- the exposed metal barrier layer 114 is continuously removed until the first dielectric layer 110 is exposed.
- the remaining portions in the trench openings 112 are first copper layers 116 a and metal barrier layers 114 a to serve as first metal wires.
- the exposed surface of the first copper layers 116 a is oxidized to copper dioxide because of existing air.
- a reduction process is performed to reduce copper dioxide to become copper by injecting reduction gas, such as hydrogen gas, to prevent resistance increase of the first copper layer 116 a.
- an organic copper diffusion barrier layer 118 is formed over the substrate 100 and covering the first copper layer 116 a and the first dielectric layer 110 .
- the organic copper diffusion barrier layer 118 at least comprises a benzocyclo polymer.
- the benzocyclo polymer includes a benzene ring functional group that can defend copper diffusion into subsequently formed dielectric layer thereon to prevent leakage problem.
- the benzocyclo polymer is an organic compound with low dielectric constant.
- the benzocyclo polymer for example, can be a polymer of benzocyclobutene, which it has dielectric constant of about 2.7 lower than conventional dielectric barrier layer, such as silicon oxide, silicon nitride, and silicon carbide having dielectric constant of about 4-7.
- the organic copper diffusion barrier layer 118 has good adhesion to copper layer and organic dielectric layer, and thereby a crack issue can be avoided.
- the organic copper diffusion barrier layer 118 is preferably formed by spin-on coating.
- the organic copper diffusion barrier layer 118 has a thickness substantially enough to defend copper diffusion.
- the organic copper diffusion barrier layer 118 has a thickness of about 100-1200 angstroms, and more preferably has a thickness of about 300-900 angstroms, and most preferably has a thickness of about 500 angstroms.
- an organic solvent can be optionally added to control the viscosity during the spin-on coating process.
- a three-step baking process can be chosen, and the baking temperatures can be in the ranges of 90-120 degrees, 120-150 degrees, and 150-180 degrees.
- the baking time for each step can be about 30 seconds to 1-2 minutes. Nitrogen gas can be optionally induced in the baking process to improve baking result.
- the organic copper diffusion barrier layer 118 is preferably formed with a multi-layer structure, which it is stacked layer by layer to obtain better defend result.
- a second dielectric layer is formed on the organic copper diffusion barrier layer 118 .
- the second dielectric layer 120 is made of a low dielectric constant (low k) material, which it comprises spin-on polymer, such as FLARE, SiLk, PAE-II, Velox, etc, or spin-on glass (SOG).
- the second dielectric layer 120 can be formed by chemical vapor deposition (CVD), or spin-on coating technologies, etc.
- dual damascene openings including upper trench openings 124 and lower via openings 122 are formed in the second dielectric layer 120 and organic copper diffusion barrier layer 118 .
- each via opening 122 is located under the bottom of the trench opening 124 , and the bottom of the via opening 122 exposes a portion of the first copper layer 116 a .
- the method of fabricating the dual damascene structure is well known to a person of ordinary skill in the art.
- the trench openings 124 can be formed earlier than the via openings 122 , or be formed later than the via openings 122 , and so that it is not further discussed in detail.
- a thin metal barrier layer 126 can be conformally formed on the over the substrate 100 and inside the via openings 122 and the trench openings 124 .
- the metal barrier layer 126 can use a material as foregoing description of the metal barrier layer 114 .
- a second copper layer 128 is then filled into the via openings 122 and the trench openings 124 to form a dual damascene structure.
- the dual damascene structure can be formed by following steps.
- the second copper layer 128 is formed to fill the via openings 122 and trench openings 124 , and then planarized by CMP to remove undesired portions.
- the remaining portions of the second copper layer 128 and the metal barrier layer 126 in the via openings 122 and trench openings 124 are via plugs 130 and copper wiring layers 132 , respectively, and they constitute a dual damascene structure.
- the copper wiring layers 132 are connected to the underlying first copper layers 116 a through the via plugs 130 .
- the via plugs 130 are in a pillared form, only some portions of the first copper layers 116 a are coupled to the via plugs 130 .
- the uncoupled portions of the first copper layers 116 a are isolated with the organic copper diffusion barrier layer 118 between the first copper layers 116 a and the second dielectric layer 120 , as indicated by the dash circle 200 .
- the copper in the first copper layers 116 a can not diffuse into the second dielectric layer 120 , so that thermal diffusion and electro-migration problems will not be occurred.
- Another organic copper diffusion barrier layer 134 is formed on the second copper layer 128 , and then other fabricating processes are continued.
- the present invention provides an organic copper diffusion barrier layer, which is a low k barrier layer.
- the organic copper diffusion barrier layer can provide good adhesion to metal layer and inter-metal dielectric layer, and can prevent thermal diffusion or electro-migration problems occurred.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (8)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/939,606 US6503835B1 (en) | 2001-08-28 | 2001-08-28 | Method of making an organic copper diffusion barrier layer |
| US10/298,616 US20030067077A1 (en) | 2001-08-28 | 2002-11-19 | Organic copper diffusion barrier layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/939,606 US6503835B1 (en) | 2001-08-28 | 2001-08-28 | Method of making an organic copper diffusion barrier layer |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/298,616 Division US20030067077A1 (en) | 2001-08-28 | 2002-11-19 | Organic copper diffusion barrier layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US6503835B1 true US6503835B1 (en) | 2003-01-07 |
Family
ID=25473445
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/939,606 Expired - Fee Related US6503835B1 (en) | 2001-08-28 | 2001-08-28 | Method of making an organic copper diffusion barrier layer |
| US10/298,616 Abandoned US20030067077A1 (en) | 2001-08-28 | 2002-11-19 | Organic copper diffusion barrier layer |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/298,616 Abandoned US20030067077A1 (en) | 2001-08-28 | 2002-11-19 | Organic copper diffusion barrier layer |
Country Status (1)
| Country | Link |
|---|---|
| US (2) | US6503835B1 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6670715B2 (en) * | 2001-12-05 | 2003-12-30 | United Microelectronics Corp. | Bilayer silicon carbide based barrier |
| US20050001317A1 (en) * | 2003-06-13 | 2005-01-06 | Ramanath Ganapathiraman | Polyelectrolyte nanolayers as diffusion barriers in semiconductor devices |
| US20080124917A1 (en) * | 2006-11-23 | 2008-05-29 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor device having air gaps |
| US20140021612A1 (en) * | 2012-07-19 | 2014-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating process for the same |
| US20140264908A1 (en) * | 2013-03-13 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene gap filling process |
| US8871601B2 (en) | 2012-12-27 | 2014-10-28 | Intermolecular, Inc. | Diffusion barriers |
| US20210384137A1 (en) * | 2020-06-05 | 2021-12-09 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package including the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095865A (en) * | 2002-08-30 | 2004-03-25 | Nec Electronics Corp | Semiconductor device and manufacturing method therefor |
| JP3998609B2 (en) * | 2003-07-28 | 2007-10-31 | 株式会社東芝 | Insulating structure, semiconductor device, and method of manufacturing semiconductor device |
| JP2005268454A (en) * | 2004-03-17 | 2005-09-29 | Nec Electronics Corp | Semiconductor apparatus and manufacturing method therefor |
| EP1760774A4 (en) * | 2004-05-21 | 2011-08-03 | Jsr Corp | LAMINATED BODY AND SEMICONDUCTOR DEVICE |
| TWI244725B (en) * | 2004-05-26 | 2005-12-01 | Advanced Semiconductor Eng | Structure and method of forming metal buffering layer |
| JP5404678B2 (en) * | 2011-03-10 | 2014-02-05 | 株式会社東芝 | Power control device |
| US9030013B2 (en) | 2012-09-21 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures comprising flexible buffer layers |
| US9887126B2 (en) * | 2014-08-26 | 2018-02-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure of dual damascene structures having via hole and trench |
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| US20010009803A1 (en) * | 1999-06-30 | 2001-07-26 | Uglow Jay E. | Methods for making dual-damascene dielectric structures |
| US20010021581A1 (en) * | 1998-09-30 | 2001-09-13 | Peter K Moon | Patterning conductive lines in circuit structures |
| US6323131B1 (en) * | 1998-06-13 | 2001-11-27 | Agere Systems Guardian Corp. | Passivated copper surfaces |
| US20010046783A1 (en) * | 2000-05-25 | 2001-11-29 | Takeshi Furusawa | Semiconductor device and manufacturing method thereof |
| US6326301B1 (en) * | 1999-07-13 | 2001-12-04 | Motorola, Inc. | Method for forming a dual inlaid copper interconnect structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550405A (en) * | 1994-12-21 | 1996-08-27 | Advanced Micro Devices, Incorporated | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
| US5965679A (en) * | 1996-09-10 | 1999-10-12 | The Dow Chemical Company | Polyphenylene oligomers and polymers |
-
2001
- 2001-08-28 US US09/939,606 patent/US6503835B1/en not_active Expired - Fee Related
-
2002
- 2002-11-19 US US10/298,616 patent/US20030067077A1/en not_active Abandoned
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6323131B1 (en) * | 1998-06-13 | 2001-11-27 | Agere Systems Guardian Corp. | Passivated copper surfaces |
| US20010021581A1 (en) * | 1998-09-30 | 2001-09-13 | Peter K Moon | Patterning conductive lines in circuit structures |
| US20010009803A1 (en) * | 1999-06-30 | 2001-07-26 | Uglow Jay E. | Methods for making dual-damascene dielectric structures |
| US20010010970A1 (en) * | 1999-06-30 | 2001-08-02 | Uglow Jay E. | Dual - damascene dielectric structures |
| US6326301B1 (en) * | 1999-07-13 | 2001-12-04 | Motorola, Inc. | Method for forming a dual inlaid copper interconnect structure |
| US20010046783A1 (en) * | 2000-05-25 | 2001-11-29 | Takeshi Furusawa | Semiconductor device and manufacturing method thereof |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6670715B2 (en) * | 2001-12-05 | 2003-12-30 | United Microelectronics Corp. | Bilayer silicon carbide based barrier |
| US20050001317A1 (en) * | 2003-06-13 | 2005-01-06 | Ramanath Ganapathiraman | Polyelectrolyte nanolayers as diffusion barriers in semiconductor devices |
| US7081674B2 (en) | 2003-06-13 | 2006-07-25 | Rensselaer Polytechnic Institute | Polyelectrolyte nanolayers as diffusion barriers in semiconductor devices |
| US20080124917A1 (en) * | 2006-11-23 | 2008-05-29 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor device having air gaps |
| US9735048B2 (en) | 2012-07-19 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating process for the same |
| US9245841B2 (en) * | 2012-07-19 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating process for the same |
| US20140021612A1 (en) * | 2012-07-19 | 2014-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating process for the same |
| US8871601B2 (en) | 2012-12-27 | 2014-10-28 | Intermolecular, Inc. | Diffusion barriers |
| US20140264908A1 (en) * | 2013-03-13 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene gap filling process |
| US9343400B2 (en) * | 2013-03-13 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene gap filling process |
| US20210384137A1 (en) * | 2020-06-05 | 2021-12-09 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package including the same |
| US11664312B2 (en) * | 2020-06-05 | 2023-05-30 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package including the same |
| US12381151B2 (en) | 2020-06-05 | 2025-08-05 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package including the same |
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| US20030067077A1 (en) | 2003-04-10 |
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