US6501685B2 - Channel write/erase flash memory cell and its manufacturing method - Google Patents
Channel write/erase flash memory cell and its manufacturing method Download PDFInfo
- Publication number
- US6501685B2 US6501685B2 US09/683,580 US68358002A US6501685B2 US 6501685 B2 US6501685 B2 US 6501685B2 US 68358002 A US68358002 A US 68358002A US 6501685 B2 US6501685 B2 US 6501685B2
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- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 230000003071 parasitic effect Effects 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims description 8
- 230000003247 decreasing effect Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000011017 operating method Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 description 13
- 239000000758 substrate Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Definitions
- the present invention relates to a nonvolatile memory cell, and more particularly, to a channel write/erase flash memory cell and its manufacturing method.
- FIG. 1 is a cross-sectional view of a conventional flash memory cell 10 . It includes a substrate 11 , a first field oxide layer 12 , a stacked gate 14 , an N-type doping region 16 , a shallow P-type doping region 18 , a deep P-type doping region 20 , and a source region 22 .
- the stacked gate 14 includes a control gate 13 and a floating gate 15 under the control gate 13 .
- the N-type doping region 16 is formed between the first field oxide layer 12 and the stacked gate 14 .
- the shallow P-type doping region 18 is formed next to the N-type doping region 16 and under the stacked gate 14 .
- the deep P-type doping region 20 and the shallow P-type region 18 are doped with the same type of dopants.
- the deep P-type doping region 20 is formed under the N-type doping region 16 and is in contact with the first field oxide layer 12 and also the shallow P-type doping region 18 .
- the deep P-type doping region 20 functions as a P well and its well depth is much deeper than the well depth of the shallow P-type doping region 18 .
- the deep P-type doping region 20 and the N-type doping region 16 are electrically connected which functions as a drain terminal of the flash memory cell 10 .
- the source region 22 functioning as a source terminal of the flash memory cell 10 , is formed next to the shallow P-type region 18 . Additionally, under the source region 22 a lightly doped region 24 is formed which is doped with the same type of dopants like the source region 22 but with a lighter density.
- the programming method of the flash memory cell 10 will be explained below.
- no voltage is applied to the source terminal 22 so as to make it floating.
- electrons will eject from the floating gate 15 to the drain terminal due to the edge Fowler-Nordheim effect thereby achieving the effect of programming the flash memory cell 10 .
- the present invention provides a programming method in which a parasitic capacitor is used to temporally store bit line data to significantly increase the programming speed.
- the present invention provides a method of forming the aforementioned channel write/erase flash memory cell structure.
- the present invention provides a channel write/erase flash memory cell structure capable of providing a pseudo-dynamic programming method.
- the structure includes a substrate of first conductivity type, a deep ion well of second conductivity type, an ion well of first conductivity type, a first oxide layer, a stacked gate, a doping region of first conductivity type, a shallow doping region of second conductivity type, and a deep doping region of second conductivity type.
- the deep ion well of second conductivity type is formed in the substrate.
- the ion well of first conductivity type is positioned above the deep ion well of second conductivity type to create a parasitic capacitor during programming.
- the first oxide layer is formed on the substrate above the ion well of first conductivity type.
- the stacked gate is formed next to the first oxide layer and over the ion well of first conductivity type.
- the doping region of first conductivity type is positioned under the first oxide layer and on one side of the stacked gate to function as a drain.
- the shallow doping region of second conductivity type is formed next to the doping region of first conductivity type and under the stacked gate.
- the deep doping region of second conductivity type is positioned under the doping region of first conductivity type and is in contact with the shallow doping region of second conductivity type.
- the first conductivity type is N type and the second conductivity type is P type.
- the first oxide layer extends into the stacked gate with a decreasing oxide thickness for reducing interference during operation.
- a source doping region is formed next to the shallow doping region of second conductivity type and under the first oxide layer to function as a source terminal.
- the doping region of first conductivity type and the source doping region are doped with VA elements such as phosphorus.
- the shallow doping region of second conductivity type and the deep doping region of second conductivity type are both doped with IIIA elements such as boron.
- the doping region of first conductivity type and the deep doping region of second conductivity type are short-circuited together by using, for example, a metal contact penetrating through the doping region of first conductivity type to the deep doping region of second conductivity type, or, alternatively, by using a metal contact formed across exposed doping region of first conductivity type and the deep doping region of second conductivity type.
- the present invention provides a method of forming a channel write/erase flash memory cell capable of performing a pseudo-dynamic programming method.
- the structure is formed by providing a substrate of first conductivity type, and then forming a deep ion well in the substrate.
- an ion well of first conductivity type is formed in the deep ion well of second conductivity type.
- a first oxide layer is then formed over the ion well of first conductivity type.
- a stacked gate is formed later partially over the first oxide layer.
- a doping region of first conductivity type acting as a drain is formed under the first oxide layer and next to the stacked gate.
- a shallow doping region of second conductivity type is formed next to the doping region of first conductivity type and under the stacked gate.
- a deep doping region of second conductivity type is formed under the doping region of first conductivity type and is in contact with the shallow doping region of second conductivity type.
- the method according to the present invention further includes a source doping region acting as a source terminal formed next to the shallow doping region of conductivity type and under the first oxide layer.
- a metal contact is formed to short-circuit the doping region of first conductivity type and the deep doping region of second conductivity type. Or, a metal contact can be formed across the exposed doping region of first conductivity type and the deep doping region of second conductivity type so that these two regions can be short-circuited together.
- the substrate and the ion well of first conductivity type are both doped with N type dopants, and the deep ion well of second conductivity type is doped with P type dopants.
- the first oxide layer has a thickness that is thinner under the central part of the stacked gate and is thicker at two sides of the stacked gate.
- the present invention provides a pseudo-dynamic programming method for programming the channel write/erase flash memory cell.
- a word line voltage V WL a source line voltage V SL , and a bit line voltage V BL are applied respectively to control gate, source terminal, and drain terminal of the flash memory cell.
- An N well, a deep P well and an N substrate are positioned in order under the flash memory cell.
- a well voltage V P is applied to the deep P well.
- the N well and the deep P well constitute a parasitic capacitor when programming the flash memory cell.
- the word line voltage V WL When performing an erase operation, the word line voltage V WL is in a high voltage level, the source line voltage V SL is in a voltage level relatively lower than the word line voltage V WL , and the bit line voltage V BL is floating.
- the well voltage V P and the source line voltage V SL are the same.
- the word line voltage V WL When performing a programming operation, the word line voltage V WL is in a low voltage level, the bit line voltage V BL is in a voltage level relatively higher than the word line voltage V WL , and the source line voltage V SL is floating.
- the well voltage V P is in a voltage level higher than the word line voltage V WL but lower than the bit line voltage V BL .
- the word line voltage V WL is in a high voltage level
- the source line voltage V SL is in a voltage level relatively lower than the word line voltage V WL
- the bit line voltage V BL is in a voltage level relatively lower than the source line voltage V SL
- the well voltage V P is in a voltage level lower than the source line voltage V SL .
- FIG. 1 is a cross-sectional view of a conventional flash memory cell.
- FIG. 2 is a schematic diagram depicting a series of memory cells.
- FIG. 3 is a cross-sectional view showing the structure of the channel write/erase flash memory cell according to the present invention.
- FIG. 4 is an equivalent circuit of the channel write/erase flash memory cell shown in FIG. 3 .
- FIG. 5 is a circuit diagram showing the pseudo-dynamic operation of the channel write/erase flash memory cell according to the present invention.
- FIG. 3 is a cross-sectional view showing the structure of the channel write/erase flash memory cell 40 and FIG. 4 shows the equivalent circuit of the flash memory cell 40 .
- the flash memory cell 40 is built upon an N substrate 41 which comprises a deep P well 42 above the N substrate 41 and a N well 44 above the deep P well 42 .
- the deep P well 42 and the N well 44 constitute a parasitic capacitor 46 (shown in the equivalent circuit diagram) that facilitates the programming speed of the flash memory cell 40 .
- the parasitic capacitor 46 will be discussed in detail hereinafter.
- a first oxide layer 48 is formed over the N well 44 , and a stacked gate 50 having a control gate 52 and a floating gate 54 is formed partially over the first oxide layer 48 .
- An N doping region 56 acting as a drain terminal is formed under the first oxide layer next to the stacked gate 50 .
- a shallow P doping region 60 is formed under the stacked gate 50 and next to the N doping region 56 .
- a deep P doping region 62 is formed underneath the N doping region 56 and is contiguous with the P doping region 60 .
- An N doping region 64 acting as a source is formed under the first oxide layer 48 and next to the shallow P doping region 60 .
- the thickness of the first oxide layer 48 at the interface between the N doping region 64 and the floating gate 54 is thicker than the thickness near the central part under the stacked gate 50 . That is, the first oxide layer 48 extends into the stacked gate 50 with a decreasing thickness.
- Such a design can avoid electrons ejection from the floating gate 54 to the high voltage source end.
- the N doping region 56 and the deep P doping region 62 are short-circuited together (marked in dash line 66 ) by a metal contact penetrating through the N doping region 56 to the deep P doping region 62 .
- a metal contact may be formed across the exposed N doping region 56 and the deep P doping region 62 to short-circuit these two regions.
- the N doping regions 56 and 64 are doped with VA elements such as phosphorus and the shallow P doping region 60 and the deep P doping region 62 are doped with IIIA elements such as boron.
- Table 1 shows exemplary operating modes of the channel write/erase flash memory cell 40 of this invention.
- a word line voltage V WL a source line voltage V SL , and a bit line voltage V BL are applied, respectively, to the control gate 52 , the source terminal 64 , and the drain terminal 56 of the flash memory cell.
- N well 44 , deep P well 42 and N substrate 41 is positioned in order under the flash memory cell 40 .
- a well voltage V P is applied to the deep P well 42 .
- the N well 44 and the deep P well 42 constitute a parasitic capacitor 46 when programming the flash memory cell.
- the word line voltage V WL (10 V) is in a high voltage level
- the source line voltage V SL ( ⁇ 8 V) is in a voltage level relatively lower than the word line voltage V WL
- the bit line voltage V BL is floating.
- the well voltage V P ( ⁇ 8 V) and the source line voltage V SL are the same.
- the word line voltage V WL (3.3 V) is in a high voltage level
- the source line voltage V SL (1 V) is in a voltage level relatively lower than the word line voltage V WL
- the bit line voltage V BL (0 V) is in a voltage level relatively lower than the source line voltage V SL
- the well voltage V P (0 V) is in a voltage level lower than the source line voltage V SL .
- FIG. 5 is a circuit diagram showing the pseudo-dynamic operation of the channel write/erase flash memory cell according to the present invention.
- a bit line voltage V BL 5 V is controlled by a selecting transistor 70 .
- the transistor 70 When the transistor 70 is turned on, the drain and the parasitic capacitor 74 are charged to 5V in few microseconds ( ⁇ s), typically less than 10 ⁇ s.
- the charged parasitic capacitor 74 is stand-by for subsequently ejecting electrons 76 from the floating gate to the drain.
- the pseudo-dynamic program operation saves a great deal of time.
- the present invention has the following advantages when comparing with the above-mentioned conventional flash memory.
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
TABLE 1 | ||||
VBL | VWL |
selected | nonselected | selected | nonselected | VSL | VP | ||
pro- | 5 V | 0 V | −10 | V | floating | floating | 0 V |
gram | |||||||
erase | floating | floating | 10 | V | floating | −8 V | −8 V |
read | 0 V | floating | 3.3 | V | floating | 1 V | 0 V |
Claims (15)
Priority Applications (1)
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US10/064,365 US6654284B2 (en) | 2001-01-30 | 2002-07-07 | Channel write/erase flash memory cell and its manufacturing method |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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TW090101747A TW477065B (en) | 2001-01-30 | 2001-01-30 | Manufacturing method of flash memory cell structure with dynamic-like write-in/erasing through channel and its operating method |
TW90101747A | 2001-01-30 | ||
TW090101747 | 2001-01-30 |
Related Child Applications (1)
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US10/064,365 Division US6654284B2 (en) | 2001-01-30 | 2002-07-07 | Channel write/erase flash memory cell and its manufacturing method |
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US20020136058A1 US20020136058A1 (en) | 2002-09-26 |
US6501685B2 true US6501685B2 (en) | 2002-12-31 |
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US09/683,580 Expired - Fee Related US6501685B2 (en) | 2001-01-30 | 2002-01-22 | Channel write/erase flash memory cell and its manufacturing method |
US10/064,365 Expired - Fee Related US6654284B2 (en) | 2001-01-30 | 2002-07-07 | Channel write/erase flash memory cell and its manufacturing method |
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JP (1) | JP2002270706A (en) |
TW (1) | TW477065B (en) |
Cited By (13)
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US20030189855A1 (en) * | 2002-04-09 | 2003-10-09 | Powerchip Semiconductor Corp. | Structure, fabrication method and operating method for flash memory |
US6847087B2 (en) * | 2002-10-31 | 2005-01-25 | Ememory Technology Inc. | Bi-directional Fowler-Nordheim tunneling flash memory |
US7119393B1 (en) * | 2003-07-28 | 2006-10-10 | Actel Corporation | Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit |
US20090114972A1 (en) * | 2007-11-01 | 2009-05-07 | Liu David K Y | Integrated Circuit Embedded With Non-Volatile One-Time-Programmable And Multiple-Time Programmable Memory |
US20090124054A1 (en) * | 2007-11-14 | 2009-05-14 | Liu David K Y | Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling |
US20090122603A1 (en) * | 2007-11-14 | 2009-05-14 | Liu David K Y | Integrated circuit embedded with non-volatile programmable memory having variable coupling |
US20090122604A1 (en) * | 2007-11-14 | 2009-05-14 | Liu David K Y | Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data |
US20090122605A1 (en) * | 2007-11-14 | 2009-05-14 | Liu David K Y | Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling |
US20100109066A1 (en) * | 2008-11-03 | 2010-05-06 | Liu David K Y | Common drain non-volatile multiple-time programmable memory |
US20100165698A1 (en) * | 2008-12-30 | 2010-07-01 | Liu David K Y | Non-volatile one-time - programmable and multiple-time programmable memory configuration circuit |
US8471328B2 (en) | 2010-07-26 | 2013-06-25 | United Microelectronics Corp. | Non-volatile memory and manufacturing method thereof |
US8988103B2 (en) | 2010-09-15 | 2015-03-24 | David K. Y. Liu | Capacitively coupled logic gate |
US9305931B2 (en) | 2011-05-10 | 2016-04-05 | Jonker, Llc | Zero cost NVM cell using high voltage devices in analog process |
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US7298646B1 (en) | 2004-08-11 | 2007-11-20 | Altera Corporation | Apparatus for configuring programmable logic devices and associated methods |
US20070247915A1 (en) * | 2006-04-21 | 2007-10-25 | Intersil Americas Inc. | Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide |
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US20030189855A1 (en) * | 2002-04-09 | 2003-10-09 | Powerchip Semiconductor Corp. | Structure, fabrication method and operating method for flash memory |
US6778438B2 (en) * | 2002-04-09 | 2004-08-17 | Powerchip Semiconductor Corp. | Structure, fabrication method and operating method for flash memory |
US20040196714A1 (en) * | 2002-04-09 | 2004-10-07 | Powerchip Seimiconductor Corporation | Structure, fabrication method and operating method for flash memory |
US6834011B2 (en) | 2002-04-09 | 2004-12-21 | Powerchip Semiconductor Corporation | Structure, fabrication method and operating method for flash memory |
US6847087B2 (en) * | 2002-10-31 | 2005-01-25 | Ememory Technology Inc. | Bi-directional Fowler-Nordheim tunneling flash memory |
US7119393B1 (en) * | 2003-07-28 | 2006-10-10 | Actel Corporation | Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit |
US20090116291A1 (en) * | 2007-11-01 | 2009-05-07 | Liu David K Y | Method of making integrated circuit embedded with non-volatile one-time - programmable and multiple-time programmable memory |
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Also Published As
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US20020136058A1 (en) | 2002-09-26 |
TW477065B (en) | 2002-02-21 |
US20020181287A1 (en) | 2002-12-05 |
US6654284B2 (en) | 2003-11-25 |
JP2002270706A (en) | 2002-09-20 |
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