US6431456B2 - IC card - Google Patents

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Publication number
US6431456B2
US6431456B2 US09/810,509 US81050901A US6431456B2 US 6431456 B2 US6431456 B2 US 6431456B2 US 81050901 A US81050901 A US 81050901A US 6431456 B2 US6431456 B2 US 6431456B2
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Prior art keywords
card
terminals
chip
memory chips
data
Prior art date
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US09/810,509
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US20010011766A1 (en
Inventor
Hirotaka Nishizawa
Yosuke Yukawa
Takashi Totsuka
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NEC Electronics Corp
Renesas Electronics Corp
Original Assignee
Hitachi Ltd
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Priority to US09/810,509 priority Critical patent/US6431456B2/en
Publication of US20010011766A1 publication Critical patent/US20010011766A1/en
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Publication of US6431456B2 publication Critical patent/US6431456B2/en
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI, LTD.
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: RENESAS TECHNOLOGY CORP.
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF ADDRESS Assignors: RENESAS ELECTRONICS CORPORATION
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07735—Physical layout of the record carrier the record carrier comprising means for protecting against electrostatic discharge
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
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    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
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    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
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    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07732—Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/922—Active solid-state devices, e.g. transistors, solid-state diodes with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper

Definitions

  • the present invention relates to technology for suppressing ESD (also called electrostatic discharge damage) of a semiconductor integrated circuit chip mounted on an IC card. More particularly, the invention relates to technology that can be effectively adapted to memory cards such as multimedia cards.
  • ESD also called electrostatic discharge damage
  • a variety of memory cards have heretofore been provided for storing multi-media data in compact sizes having decreased weights.
  • a multi-media card having a memory and a memory controller mounted on a card substrate, establishing an interface to a host unit using a small number of signals.
  • the memory card of this type has the connection terminals for connection to the host unit, the connection terminals being exposed on the card substrate, but has no particular mechanism such as cover for protecting the terminals.
  • a semiconductor integrated circuit chip connected to the exposed terminals may be damaged.
  • the semiconductor integrated circuit chip is provided with an input protection circuit for preventing the input circuit from the electrostatic damage.
  • the input protection circuit is constituted by, for example, disposing, between an input terminal and a power source terminal, an element such as a diode whose connection state is reversed relative to the amplitude voltage of the input signal. It is, however, expected that the memory card is carried by itself and is frequently attached to, and detached from, the host unit. Thus, the present inventors have found the importance of reinforcing the prevention of the electrostatic damage.
  • Japanese Patent Laid-Open No. 209379/1998 discloses technology for reinforcing the protection of input against the electrostatic damage.
  • a metal wiring layer is formed maintaining a gap (discharge gap) in which static electricity could be discharged relative to an electrode layer on a semiconductor substrate so that when static electricity has entered into the electrode layer, the static electricity is discharged to the metal wiring layer, preventing the static electricity that has entered into the electrode layer from entering into the semiconductor element.
  • Japanese Patent Laid-Open No. 271937/1995 discloses a circuit employing a gate-source protection diode of a MOSFET that is externally attached to a semiconductor integrated circuit chip to prevent the electrostatic damage.
  • the present inventors have forwarded the following study from the standpoint reinforcing the prevention of electrostatic damage of the IC card such as a memory card having connection terminals that are exposed.
  • the efficiency for preventing the electrostatic damage does not increase unless consideration is given to a relationship between the characteristics and the ability of the overvoltage protection circuit incorporated in the semiconductor integrated circuit chip.
  • the externally attached circuit elements that are large in size or that are large in number, cause an increase in the size and thickness of the IC card.
  • the overvoltage stands for a surge voltage or a transient voltage that generates electrostatically.
  • a countermeasure against the electrostatic damage by the externally attached circuit elements decreases, at least, the vacant region on the card substrate correspondingly. Even in this case, it becomes necessary to avoid concentration of wiring patterns and the concentration of bonding wires that could become a cause of malfunction due to undesired leakage of signal lines. This contrivance is necessary even when the memory capacity of the memory card is to be increased.
  • the present invention provides an IC card capable of reinforcing the prevention of electrostatic damage without driving up the cost of the semiconductor integrated circuit chip.
  • the present invention further provides an IC card capable of reinforcing the prevention of electrostatic damage by attaching overvoltage protection elements to the semiconductor integrated circuit chip without causing a great change in the size and thickness of the card.
  • the invention further provides an IC card which can be expected to prevent electrostatic damage caused by an unexpected handling by a person who is not familiar with.
  • the invention further provides an IC card capable of easily recovering the data in the memory card even when the input circuit of the semiconductor integrated circuit chip is electrostatically damaged, provided the data in the memory remain safe.
  • the invention further provides an IC card capable of avoiding the concentration of wiring patterns and bonding wires that could cause a malfunction due to undesired leakage of signal lines even when the vacant region on the card substrate is decreased by the countermeasure against the electrostatic damage by externally attaching the circuit elements.
  • the invention further provides an IC card having a relatively large storage capacity in a relatively small size.
  • Second overvoltage protection elements capable of reinforcing the prevention of electrostatic damage are externally attached to the semiconductor integrated circuit chip by taking into consideration a relationship to first overvoltage protection elements that are integrated in a semiconductor integrated circuit chip. That is, an IC card has a semiconductor integrated circuit chip mounted on a card substrate and plural connection terminals that are exposed, wherein the connection terminals are connected to predetermined external terminals of the semiconductor integrated circuit chip, the first overvoltage protection elements connected to the external terminals are integrated on the semiconductor integrated circuit chip, and the second overvoltage protection elements connected to the connection terminal are mounted on the card substrate.
  • the second overvoltage protection elements are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.
  • a voltage greater than a rated voltage applied to the second overvoltage protection elements for flowing a specified pulse current is the voltage that enables the first overvoltage protection elements to flow only a current smaller than the above specifued pulse current.
  • the second overvoltage protection elements are variable resistor elements having a breakdown voltage larger than that of the first overvoltage protection elements.
  • the second overvoltage protection elements have a capacity larger than that of the first overvoltage protection elements.
  • the second overvoltage protection elements have a breakdown voltage smaller than a breakdown voltage of the first overvoltage protection elements.
  • the second overvoltage protection elements has a breakdown voltage smaller than a breakdown voltage of a circuit that is protected by the first overvoltage protection elements.
  • the second overvoltage protection elements exhibit the effect for preventing the electrostatic damage, since consideration has been given to a relationship between the characteristics and the ability of the first overvoltage protection elements that are contained in the semiconductor integrated circuit chip.
  • the second overvoltage protection elements may have their ends on one side thereof connected to the power source connection terminals of the card substrate and may have their ends on the other side thereof connected to the signal connection terminals.
  • the signal connection terminals are connected to the corresponding external terminals of the semiconductor integrated circuit chip.
  • the signal propagation distances from the signal connection terminals to the corresponding second overvoltage protection elements are shorter than the signal propagation distances from the signal connection terminals to the corresponding external terminals of the semiconductor integrated circuit chip. This prevents the semiconductor integrated circuit chip from being directly affected destructively by the overvoltage before the second overvoltage protection elements work in response to the overvoltage.
  • the second overvoltage protection elements may be varistors of the surface-mount type comprising chiefly semiconductor ceramics, an array of chip diodes, chip capacitors or chip transistors. This makes it possible to decrease the mounting area or the occupation area of the second overvoltage protection elements.
  • the surface mounting lowers the cost of production.
  • the semiconductor chip is a controller chip, and one or plural memory chips (e.g., nonvolatile memory chips) connected to the controller chip are further mounted on the card substrate.
  • the controller chip has a memory control function for controlling the reading/writing operation for the memory chips according to an instruction from an external unit.
  • the controller chip may employ a privacy protection function for effecting the encryption for the data written into the memory chip and for effecting the decryption for the data read out from the memory chip.
  • the second overvoltage protection elements connected to the connection terminals should be mounted on the card substrate, first, and, then, predetermined external terminals of the semiconductor integrated circuit chip should be connected to the connection terminals. Then, the protection by the second overvoltage protection elements is obtained in a step of connecting the semiconductor integrated circuit chip.
  • the invention is concerned with an IC card having a semiconductor integrated circuit chip mounted on a card substrate, wherein plural connection terminals are exposed, predetermined external terminals of said semiconductor integrated circuit chip are connected to the connection terminals, first overvoltage protection elements connected to the external terminals are integrated on the semiconductor integrated circuit chip, and second overvoltage protection elements connected to the connection terminals are mounted on the card substrate, and wherein the second overvoltage protection elements may be connected by being surface-mounted on the electrically conducting pattern formed on the card substrate. This makes it possible to decrease the cost of mounting the second overvoltage protection elements.
  • the semiconductor chip is a controller chip, and one or plural memory chips connected to the controller chip are further mounted on the card substrate.
  • bonding wires are used for connecting the connection terminals to the external terminals of the controller chip, and bonding wires are used for connecting the controller chip to the memory chips. Therefore, a number of wiring patterns having the same function as the connection by the bonding wires, need not be densely formed on the card substrate. Space on the controller chip or the memory chips can be used for the wiring. Accordingly, this contributes to decreasing the cost of the card substrate.
  • the memory chips When plural memory chips are to be connected in parallel to the controller chip by bonding wires, the memory chips may be mounted on the card substrate in a manner that the chips are stacked one upon the other with their positions being so deviated that the external terminals are exposed, from the standpoint of shortening the lengths of the bonding wires. Therefore, the distance to the controller chip is shortened and the lengths of the bonding wires are shortened compared to when the memory chips are arranged without being stacked one upon the other. This decreases the probability of undesired contact or breakage of the bonding wires. In this case, in particular, a condition should be maintained in that the area on one surface of the card substrate is larger than the total areas of the memory chips and of the controller chip. This is to provide the card substrate with extra space for sufficiently coping with a restrictive condition in that the wiring layer is formed on one surface only of the card substrate. This is not a simple idea of mounting the memory chips in a stacked manner for decreasing the area of the card substrate.
  • the invention is concerned with an IC card in which plural memory chips and the controller chip for controlling the memory chips are mounted on one surface of the card substrate, wherein when the memory chips are mounted on the card substrate in a manner of being stacked one upon the other with their positions being so deviated that the external terminals are exposed, the external terminals of the memory chips that receive the same signals from the controller chip are successively connected in series by bonding the wires.
  • the bonding method of a so-called stitch sewing is employed.
  • the bonding wires can be shortened as a whole compared to when the controller chip is connected to the external terminals through the bonding wires. In this respect, too, the probability of undesired contact or breakage of lines due to the concentration of the bonding wires can be decreased.
  • the invention is concerned with an IC card in which plural memory chips and the controller chip for controlling the memory chips are mounted on one surface of the card substrate, wherein when the memory chips are mounted on the card substrate in a manner of being stacked one upon the other with their positions being so deviated that the external terminals are exposed, the external terminals for receiving chip selection signals of the memory chips are located at the ends of the arrangements of the external terminals of the nonvolatile memory chips, and are connected to the controller chip by bonding the wires.
  • the external terminals for receiving the chip selection signals must be separately connected to the external terminals for outputting the chip selection signal of the controller chip. Therefore, the above stitch-bonding method cannot be employed.
  • the external terminals for selecting the chips are arranged at the ends of the memory chips and work to accomplish necessary connection without hindered by other bonding wires.
  • the memory chips and the controller chip mounted on the card substrate may be arranged in the form of columns. That is, the memory chips are connected to the controller chip, the connection terminals formed on the card substrate are connected to predetermined external terminals of the controller chip, the first overvoltage protection elements connected to the external terminals are integrated on the controller chip, and the second overvoltage protection elements connected to the connection terminals are mounted on the card substrate.
  • the distances from the connection terminals are increased in order of the second overvoltage protection elements, controller chip, and plural memory chips, which are arranged like columns from one side of the card substrate to the opposing side thereof.
  • the second overvoltage protection elements for finally releasing the overvoltage are located closest to the connection terminals to which an overvoltage is applied, and the memory chips storing the data are located remotest, offering a high reliability from the standpoint of preventing electrostatic damage to the semiconductor chip and protecting the data.
  • the memory chips may be mounted on the card substrate in a manner of being stacked one upon the other with their positions being so deviated that the external terminals are exposed.
  • the arrangement of the memory chips and the controller chip mounted on the card substrate is not limited to the column-like arrangement only.
  • the memory controller is arranged with its lengthwise direction in parallel with the other side of the two neighboring sides, and plural memory chips are arranged in parallel in a direction nearly at right angles with the direction in which the connection terminals are arranged.
  • the connection terminals exposed from the card substrate are connected to predetermined external terminals of the controller chip, the first overvoltage protection elements connected to the external terminals are integrated on the controller chip, and the memory chips are connected to the controller chip.
  • connection terminals and the controller chip being arranged along the neighboring two sides of the card substrate, it is allowed to easily increase the density for mounting the memory chips or to increase the number of mounts. If the memory chips are arranged in parallel being divided into a first group in which the memory chips are stacked in a plural number with their positions being so deviated that the external terminals are exposed and a second group in which the memory chips are stacked in a plural number in the same manner, the height of the IC card can be suppressed.
  • the second overvoltage protection elements connected to the connection terminals may be mounted on the card substrate along the direction in which the connection terminals are arranged.
  • the electrically conducting patterns may be connected by using through holes that are penetrating through the card substrate.
  • the through holes are arranged outside the molded region that covers the semiconductor integrated circuit chip and the other surface of the card substrate. The molding that is executed while applying a pressure eliminates the probability in that the molding resin flows into the back side of the card substrate passing through the holes.
  • the through holes are formed for the connection terminals exposed from the IC card, it is desired that the through holes are formed at positions deviated from the slide surfaces of the connection terminals. Even when the IC card is attached to, or detached from, the mounting slot, therefore, the terminals of the slot do not come into slide contact with the through holes and do not receive mechanical force, preventing such a probability that the patterns of the connection terminals are cracked from the through holes and are damaged.
  • the invention is concerned with an IC card in which plural connection terminals are exposed on one surface of a card substrate, a semiconductor integrated circuit chip is mounted on the other surface of the card substrate, predetermined external terminals of the semiconductor integrated circuit chip are connected to the connection terminals, first overvoltage protection elements connected to the external terminals are integrated on the semiconductor integrated circuit chip, and second overvoltage protection elements connected to the connection terminals are mounted on the other surface of the card substrate, and wherein the semiconductor integrated circuit chip, the second overvoltage protection elements and the other surface of the card substrate are covered with a metal cap.
  • the metal cap can be formed by reducing a metal plate, by a forging method or by a die casting method.
  • the resin cap may be blended with an electromagnetic wave-absorbing material such as ferrite, etc.
  • electrically conducting particles such as carbon may be mixed.
  • An electrically conducting shielding pattern may be employed for the card substrate to relax the effect of electrostatic discharge that takes place near the card substrate. That is, the invention is concerned with an IC card in which plural connection terminals are exposed on one surface of a card substrate, and a semiconductor integrated circuit chip is mounted on the other surface of the card substrate, wherein predetermined external terminals of the semiconductor integrated circuit chip are connected to the connection terminals, first overvoltage protection elements connected to the external terminals are integrated on the semiconductor integrated circuit chip, second overvoltage protection elements connected to the connection terminals are mounted on the other surface of the card substrate, and an electrically conducting shielding pattern is formed on one surface of the card substrate except a region of the connection terminals, the electrically conducting shielding pattern being connected to the connection terminal for supplying ground power source or being connected to none of the connection terminals.
  • the electrically conducting shielding pattern disperses the static electricity.
  • the IC card is provided on the surface thereof with an indication indicating a position where the IC card should be held by fingers (figure of a finger printed on a position at where the IC card should be held by fingers at the time of attachment or detachment), the IC card mounting a semiconductor integrated circuit chip permitting plural connection terminals to be exposed. Further, a notice is written on the surface of the IC card warning not to touch the connection terminals. Besides, a notice is written on the packing member packing the IC card warning not to touch the connection terminals of the IC card.
  • the invention deals with a IC card giving attention to recovering the stored data, wherein plural connection terminals are exposed, plural memory chips and a controller chip for controlling the memory chips are mounted on a card substrate, the connection terminals are connected to a first group of external terminals of the controller chip, the memory chips are connected to a second group of external terminals of the controller chip, and data evaluation terminals connected to the second group of external terminals are formed on the card substrate.
  • the card substrate may further be provided with a control terminal for controlling the output terminal included in the second group of external terminals of the controller chip to assume a high output impedance state.
  • the damaged controller chip that is placed in an undesired signal output state, can be easily relieved.
  • the controller chip may often be provided with a privacy protection mechanism for executing the encryption for the data that are written into the memory chips and for executing the decryption for the data read out from the memory chips.
  • the data are recovered by the manufacturer of the IC card or by an authorized person by decrypting the data read out from the memory chips.
  • the simplest method of recovering the data from the IC card having the data evaluation terminals includes a first processing for placing the memory chips in a state where they cannot be controlled by the controller chip, and a second processing for reading out the data from the data evaluation terminals by controlling the memory chips.
  • a data recovery method of when the controller chip has the privacy protection function includes a first processing for controlling the output terminal included in the second group of external terminals of the controller chip to assume a high output impedance state, a second processing for reading out the data from the data evaluation terminals by controlling the memories, a third processing for decrypting the data read out by the second processing, and a fourth processing for writing the data decrypted by the third processing into another IC card.
  • FIG. 1 is a circuit diagram illustrating a connection terminal of an IC card according to the present invention
  • FIG. 2 is an axial sectional view illustrating the structure of a varistor in cross section
  • FIG. 3 is a diagram of an I-V line illustrating the characteristics of the varistor
  • FIG. 4 is a diagram illustrating the connection of the varistors to the connection terminals of a multi-media card
  • FIG. 5 is a diagram illustrating, on a plane, the constitution of the multi-media card chiefly in a state where the circuit elements are mounted;
  • FIG. 6 is a vertical sectional view of the multi-media card of FIG. 5;
  • FIG. 7 is a diagram illustrating a state where a through hole is formed in a deviated manner in a connection terminal of the multi-media card
  • FIG. 8 is a plan view partly illustrating the multi-media card by applying stitch bonding for connecting the nonvolatile memory chips
  • FIG. 9 is a vertical sectional view of a stitch-bonded portion
  • FIG. 10 is a diagram illustrating the wire bondings of when a nail head bonding is utilized and when a wedge bonding is utilized;
  • FIG. 11 is a diagram illustrating, on a plane, the constitution of a multi-media card having a structure in which four pieces of nonvolatile memory chips are stacked;
  • FIG. 12 is a vertical sectional view illustrating the sectional structure of the multi-media card of FIG. 11;
  • FIG. 13 is a plan view illustrating a multi-media card applying a structure for stacking the memory chips in a divided manner and a structure in which the connection terminals and the controller chip are arranged along the two neighboring sides of the card substrate;
  • FIG. 14 is a vertical sectional view illustrating a portion of the multi-media card of FIG. 13;
  • FIG. 15 is a plan view illustrating another multi-media card applying a structure for stacking the memory chips in a divided manner and a structure in which the connection terminals and the controller chip are arranged along the two neighboring sides of the card substrate;
  • FIG. 16 is a plan view illustrating a memory card in which the controller chip is placed on the memory chip to stack both of them;
  • FIG. 17 is a plan view illustrating a folded card by stacking the memory chips and the controller chip by utilizing LOC;
  • FIG. 18 is a plan view illustrating another IC card applying a COB structure
  • FIG. 19 is a vertical sectional view of the IC card of FIG. 18;
  • FIG. 20 is a view illustrating an electrically conducting pattern formed on the bottom surface of a card substrate of the IC card of FIG. 18;
  • FIG. 21 is a view illustrating an IC card describing a notice or a sign of caution for preventing electrostatic damage
  • FIG. 22 is a flowchart illustrating a method of fabricating an IC card mounting varistors
  • FIG. 23 is a plan view of an IC card giving attention to recovering the data
  • FIG. 24 is a flowchart illustrating a procedure of a data recovery processing for an IC card having data evaluation terminals
  • FIG. 25 is a diagram illustrating several kinds of structures of metal caps
  • FIG. 26 is a block diagram illustrating the constitution of a flush memory chip.
  • FIG. 27 is a sectional view schematically illustrating the structure of a nonvolatile memory cell transistor for the flush memory chip.
  • FIG. 1 illustrates a connection terminal of an IC card according to the invention.
  • the IC card that is shown has a semiconductor integrated circuit chip 2 mounted on a card substrate 1 , and, typically, has connection terminals 3 that are exposed.
  • the connection terminals 3 are interface terminals for electrically connecting the IC card to a host unit to which the IC card is detachably attached.
  • the connection terminals 3 are connected to predetermined external terminals 4 of the semiconductor integrated circuit chip 2 .
  • the external terminals are input terminals which are connected to, for example, a CMOS inverter in the initial stage of the input circuit via signal lines 5 .
  • the CMOS inverter is constituted by a p-channel field-effect transistor (often described as unit MOS transistor) Q 1 and an n-channel MOS transistor Q 2 disposed in series between a ground terminal Vss and a power source terminal Vcc of the circuit.
  • diodes 7 , 8 which are first overvoltage protection elements connected to the external terminal 4 , a thyristor 9 and a clamping MOS transistor Q 5 .
  • a varistor 11 which is a second overvoltage protection element connected to the connection terminal 3 .
  • the diodes 7 , 8 , thyristor 9 and clamping MOS transistor Q 5 constitute an input protection circuit 6 .
  • cathode and drain of the MOS transistor is determined depending upon the direction of the operation voltage.
  • the names determined in the state of normal operation by the operation voltages Vss and Vcc are used as the names of terminals.
  • the anode of the diode 7 is connected to the input signal line 4 , the cathode thereof is connected to the power source terminal Vcc, the cathode of another diode 8 is connected to the input signal line 4 and the anode thereof is connected to the ground terminal Vss.
  • the thyristor 9 is equivalently constituted by a pnp transistor Q 3 and an npn transistor Q 4 , and the anode thereof is connected to the input signal line 4 , and the cathode thereof is connected to the ground terminal Vss.
  • the MOS transistor Q 5 is a clamping MOS transistor of the form of a so-called diode connection of which the gate and source are connected to the ground terminal Vss and of which the drain is connected to the input signal line 4 .
  • Reference numerals 12 and 13 are input protection resistors.
  • Symbols Q 6 and Q 7 are a p-channel clamping MOS transistor of the form of a so-called diode connection of which the gate and source are connected together and an n-channel clamping MOS transistor.
  • the clamping MOS transistors Q 6 and Q 7 are circuit elements having an auxiliary function to cope with the case where an overvoltage has leaked from the input protection circuit 6 . When used alone, they cannot work as the first overvoltage protection element but work as the overvoltage protection element in cooperation with other circuit element.
  • connection terminal 3 receives a signal having a voltage amplitude between the ground voltage Vss and the power source voltage Vcc.
  • the diodes 7 , 8 , thyristor 9 , and clamping MOS transistors Q 5 , Q 6 and Q 7 are all connected in a reversed manner.
  • the diode 7 When an overvoltage of a positive polarity is applied to the connection terminal 3 due to electrostatic discharge, the diode 7 is connected in the forward direction, the anode of the thyristor 9 is turned on in excess of the element voltage in the forward direction, whereby the overvoltage flows into the power source voltage Vcc and the ground voltage Vss, and is blocked from flowing into the succeeding stages or flows in a decreased amount.
  • the clamping MOS transistor Q 6 is turned on when the overvoltage of the positive polarity leaks even by a small amount, and permits the overvoltage to flow into the power source voltage Vcc.
  • the diode 8 is connected in the forward direction and the clamping MOS transistor Q 5 is turned on, whereby the overvoltage flows into the ground voltage Vss, and is blocked from flowing into the succeeding stages or flows in a decreased amount.
  • the clamping MOS transistor Q 7 is turned on when the overvoltage of the negative polarity leaks even by a small amount, and permits the overvoltage to flow into the ground voltage Vss.
  • the varistor 11 is a circuit element which assumes the overvoltage element operation before the overvoltage element operation of the input protection circuit 6 reaches its limit, and reinforces the function for preventing electrostatic damage or reinforces the overvoltage protection function.
  • the varistor 11 is equivalent to a circuit in which the Zener diodes are connected back to back, or can be replaced thereby.
  • the varistor 11 is a laminated chip varistor using semiconductor ceramics.
  • the varistor 11 has the shape of a small chip that can be surface-mounted, has electrically conducting side electrodes 20 and 21 at both ends, the one side electrode 20 being provided with a pair of interlayer electrodes 22 and 23 extending toward the other side electrode 21 , the other side electrode 21 being provided with another interlayer electrode 24 located between the pair of interlayer electrodes 22 and 23 , and extending toward the one side electrode 20 , and the gaps among the side electrodes 20 , 21 and the interlayer electrodes 22 , 23 , 24 being filled with semiconductor ceramics 25 .
  • FIG. 3 illustrates characteristics of the varistor 11 .
  • the varistor 11 is a variable resistor element having current-voltage (I-V) characteristics as shown in FIG. 3, operates on a leakage current of not larger than 50 ⁇ A in a state where it is normally used, and does not affect the input of signals through the connection terminal 3 in a state where the device is practically used. This state is obtained by using the device at a voltage which is not higher than a rated voltage (also called use voltage) Vwm specific to the varistor as described in a data sheet thereof.
  • Vwm rated voltage
  • the current tolerating ability of the overvoltage protection element such as diode in the input protection circuit becomes no longer sufficient for the overvoltage, and the current saturates. Accordingly, the operation current starts flowing into the varistor 11 . Then, as the overvoltage reaches near the breakdown voltage (Vb), the resistance so decreases that the voltage becomes almost constant irrespective of the current. For larger transient voltage, the varistor prevents the electrostatic damage to the semiconductor integrated circuit chip owing to its high energy allowance value with the clamp voltage (Vc) as a theoretical upper limit.
  • the clamp voltage Vc can be specified to be a prescriptive pulse current, i.e., as a terminal voltage (voltage across the side electrodes) of when a current of 1 A is supplied for 8.20 seconds
  • the breakdown voltage Vb can be specified to be a terminal voltage of when, for example, a current of 1 mA is supplied. If described qualitatively, the breakdown voltage Vb can be defined as a voltage which easily enables the I-V characteristics to be reversed even when a direct current is applied within the range.
  • the clamp voltage can be defined to be a voltage that is very likely to lead to the breakage when it is exceeded several times.
  • the characteristics of the varistor 11 can be specified to be as described below by taking into consideration the characteristics of the overvoltage protection element of the input protection circuit 6 .
  • the varistor 11 can be specified to be a variable resistance element having an current tolerating ability in excess of that of the diodes 7 , 8 , thyristor 9 and clamping MOS transistor Q 5 in the input protection circuit 6 , or in excess of that of the clamping MOS transistors Q 6 and Q 7 .
  • a voltage such as a breakdown voltage Vb or a voltage close thereto larger than a rated voltage applied to the varistor 11 for flowing a specified pulse current, is the voltage that enables the diodes 7 , 8 , thyristor 9 , clamping MOS transistor Q 5 in the input protection circuit 6 , and the clamping MOS transistors Q 6 and Q 7 to flow only a current smaller than the above specified pulse current, if they are not broken.
  • the varistor 11 is a variable resistance element having a breakdown voltage larger than those of the diodes 7 , 8 , thyristor 9 and clamping MOS transistor Q 5 in the input protection circuit 6 , and than those of the clamping MOS transistors Q 6 and Q 7 .
  • the varistor 11 is a variable resistance element having a stray capacity larger than those of the diodes 7 , 8 , thyristor 9 and clamping MOS transistor Q 5 in the input protection circuit 6 , and than those of the clamping MOS transistors Q 6 and Q 7 .
  • the semiconductor ceramics when used for the power source terminal, it is obvious that the semiconductor ceramics has a relatively large capacitive component though it is not a dielectric.
  • the stray capacity works to relax the change in the transient voltage, and is effective for preventing the electrostatic damage when the stray capacity is large.
  • the capacity When used for signal terminals, the capacity must be decreased to lie within a permissible range so as to respond to high-speed signals.
  • the breakdown voltage of the varistor 11 is smaller than the breakdown voltages of the diodes 7 , 8 , thyristor 9 and clamping MOS transistor Q 5 in the input protection circuit 6 , and than those of the clamping MOS transistors Q 6 and Q 7 .
  • the varistor 11 breaks down before the input protection circuit 6 is damaged to let the overvoltage be released.
  • the breakdown voltage of the varistor 11 is smaller than the breakdown voltages of the diodes 7 , 8 , thyristor 9 and clamping MOS transistor Q 5 in the input protection circuit 6 , and than that of a circuit protected by the clamping MOS transistors Q 6 and Q 7 , such as of a CMOS inverter circuit constituted by MOS transistors Q 1 and Q 2 .
  • the varistor 11 has been selected by taking into consideration the relationship between the characteristics and the ability of the overvoltage protection elements such as diodes 7 , 8 constituting the input protection circuit 6 contained in the semiconductor integrated circuit chip 2 . Accordingly, the varistor 11 efficiently exhibits the effect for preventing the electrostatic damage.
  • the signal propagation distance from the connection terminal 3 to the varistor 11 is shorter than the signal propagation distance of from the connection terminal 3 to a corresponding external terminal 4 of the semiconductor integrated circuit chip 2 . This makes it possible to prevent the semiconductor integrated circuit chip 2 from directly receiving destructive effect due to an overvoltage before the varistor 11 functions in response to the overvoltage.
  • the varistor 11 is of the source-mounting type comprising chiefly semiconductor ceramics. Therefore, the mounting area or the occupation area of the varistor 11 can be decreased.
  • the surface mounting helps decrease the cost of producing the IC card.
  • IC card using the varistor 11 is applied to a multi-media card.
  • FIG. 4 is a diagram illustrating the connection of the varistors to the connection terminals of the multi-media card.
  • the multi-media card has a size measuring 24 mm ⁇ 32 mm ⁇ 1.4 mm.
  • the card substrate 1 has connection terminals, i.e., a connection terminal 3 a for receiving a chip select signal CS, a connection terminal 3 b for receiving a command CMD, a connection terminal 3 c for receiving a clock signal CLK, a connection terminal 3 d for inputting and outputting data DAT, a connection terminal 3 e served with a power source voltage Vcc, and two connection terminals 3 f and 3 g served with ground voltage Vss.
  • connection terminals 3 a to 3 g are connected to the controller chip and to the nonvolatile memory chips that are not shown but that are mounted on a region designated at 30 in the drawing.
  • the arrangement of the connection terminals 3 a to 3 g is different from that of the practical multi-media card.
  • Varistors 11 a to 11 e are mounted on the card substrate 1 among the connection terminals 3 a to 3 e and between the connection terminals 3 e and 3 g.
  • the varistor is provided in a number of one for each corresponding terminal.
  • the varistors may be provided in a plural number being connected in series.
  • the varistor lie disposed for the connection terminal 3 e that receives the power source voltage Vcc, works as a by-pass capacitor. Therefore, the varistor 11 e may be replaced by a by-pass capacitor, or a by-pass capacitor 31 may be arranged in parallel as shown in FIG. 4 .
  • FIG. 5 illustrates on a plane the constitution of the multi-media card mounting chiefly the circuit elements
  • FIG. 6 is a vertical sectional view thereof.
  • the card substrate 1 is constituted by a glass epoxy resin, and has, on the back surface thereof, the connection terminals 3 a to 3 g formed as electrically conducting patterns.
  • the varistors 11 a to 11 e On the surface of the card substrate 1 are mounted the varistors 11 a to 11 e, a controller chip 33 and nonvolatile memory chips 34 a, 34 b via wiring patterns and electrically conducting patterns.
  • FIG. 5 illustrates on a plane the constitution of the multi-media card mounting chiefly the circuit elements
  • FIG. 6 is a vertical sectional view thereof.
  • the card substrate 1 is constituted by a glass epoxy resin, and has, on the back surface thereof, the connection terminals 3 a to 3 g formed as electrically conducting patterns.
  • the varistors 11 a to 11 e On the surface of the card substrate 1 are mounted the varistors 11
  • reference numeral 36 denotes electrically conducting patterns connected to the corresponding connection terminals 3 a to 3 g via the through holes 40
  • reference numeral 35 denotes a wiring pattern for connecting the ends of the varistors 11 a to 11 e to the ground voltage Vss.
  • the varistors 11 a to 11 e are surface-mounted spanning across the wiring pattern 35 and the connection terminals 3 a to 3 e.
  • reference numerals 38 and 39 denote bonding patterns
  • 37 denotes wiring patterns connecting the bonding patterns 38 to the electrically conducting patterns 36 .
  • the electrically conducting patterns 38 are connected to the corresponding external terminals 50 of the controller chip 33 through bonding wires 41
  • the external terminals 51 of the controller chip 33 are connected to the corresponding bonding patterns 39 through bonding wires 42 .
  • the bonding patterns 39 are connected to the corresponding external terminals 52 a of one nonvolatile memory chip 34 a by bonding wires 43 a
  • the bonding patterns 39 are connected to the corresponding external terminals 52 b of the other nonvolatile memory chip 34 b by bonding wires 43 b.
  • the semiconductor integrated circuit chip is a so-called bear chip, and the external terminals 50 , 51 , 52 a and 52 b are the bonding pads formed of aluminum, aluminum alloy, copper or the like.
  • the nonvolatile memory chips 34 a and 34 b are, for example, electrically rewritable flush memory chips.
  • the flush memory chip has a memory cell array in which are arranged, like a matrix, nonvolatile memory cell transistors having a control gate, a floating gate, a source and a drain, and executes such operations as reading the data, erasing the data, writing the data and verifying the data according to commands and addresses fed from an external unit.
  • the nonvolatile memory chips 34 a and 34 b comprising the flush memory chips have external terminals 52 a and 52 b, which are terminals for receiving a chip enable signal (also called chip selection signal) /CE for instructing the selection of chip, terminals for receiving a write enable signal /WE for instructing the writing operation, input/output terminals I/O 0 to I/O 7 , terminals for receiving a command/data enable signal /CDE for instructing whether the input/output terminals I/O 0 to I/O 7 be used for inputting/outputting the command/data or for receiving the address, terminals for receiving an output enable signal /OE for instructing the output operation, terminals for receiving a clock signal /SC for instructing the data latch timing, a terminal for outputting a ready/busy signal R/B for instructing to an external unit whether the writing operation is being executed, and terminals for receiving a reset signal /RES.
  • a chip enable signal also called chip selection signal
  • /CE for instructing the
  • the controller chip 33 has a privacy protection function which controls the reading/writing operation for the nonvolatile memory chips 34 a, 34 b according to an instruction from an external unit, executes the encryption for the data to be written into the nonvolatile memory chips 34 a, 34 b by taking into consideration the data security or the copyright protection, and executes the decryption for the data read out from the nonvolatile memory chips 34 a and 34 b.
  • the external terminals 50 of the controller chip 33 are corresponded to the input/output functions of the connection terminals 3 a to 3 g, and include a terminal for receiving a select signal CS for instructing the selection operation of the multi-media card, a terminal for serially receiving the command CMD for instructing the operation of the multi-media card, a terminal for receiving a clock signal CLK that is regarded to be in synchronism with the signal input/output operation of the external terminal 50 , a terminal for serially inputting/outputting the data DAT, and a terminal for receiving a power source voltage Vcc and ground voltage Vss.
  • the controller chip 33 are integrated the input protection circuit 6 and clamping MOS transistors Q 6 and Q 7 that are described with reference to FIG. 1 concerning the input terminals that are among the external terminals 50 .
  • the controller chip 33 has external terminals 51 for making access to the memories, i.e., a terminal for sending a chip selection signal /CEO to the nonvolatile memory chip 34 a, a terminal for sending a chip selection signal /CE 1 to the nonvolatile memory chip 34 b, and external terminals corresponding to the external terminals of the nonvolatile memory chips 34 a and 34 b but having an input/output direction opposite thereto.
  • bonding wires 41 are used for connecting the connection terminals 3 a to 3 g to the external terminals 50 of the controller chip 33
  • bonding wires 43 a and 43 b are used for connecting the controller chip 33 to the nonvolatile memory chips 34 a, 34 b.
  • Space on the controller chip 33 and on the nonvolatile memory chips 34 a, 34 b can be utilized for the wiring.
  • the aerial wiring of the bonding wires makes it possible to simplify the wiring on the substrate. Therefore, this contributes to decreasing the cost of the card substrate 1 .
  • the two nonvolatile memory chips 34 a and 34 b are connected using the bonding wires in parallel with the controller chip 33 .
  • the nonvolatile memory chips 34 a and 34 b are mounted on the card substrate 1 in a state of being stacked one upon the other with their positions being so deviated that the external terminals 52 a, 52 b are exposed. Therefore, the distances to the controller chip 33 can be shortened compared to when the nonvolatile memory chips 34 a, 34 b are arranged without being stacked, and the lengths of the bonding wires 43 a, 43 b can be shortened. This decreases undesired contact or breakage of the bonding wires.
  • the amount of deviation may be determined within such a range that a chip of the lower layer exits under the external terminals for bonding of the chip of the upper layer.
  • the chip of the lower layer is not existing under the external terminals for bonding, the chip is likely to be damaged due to mechanical force at the time of bonding.
  • a condition is satisfied in that the area on one surface of the card substrate 1 is larger than the total areas of the nonvolatile memory chips 34 a, 34 b and the controller chip 33 .
  • This is a contrivance for providing the card substrate 1 with an extra space to cope with such a restrictive condition that the wiring layer is formed on one surface only of the card substrate. This is different from a simple idea of mounting the nonvolatile memory chips in a stacked manner to decrease the area of the card substrate 1 .
  • the nonvolatile memory chips 34 a, 34 b and the controller chip 33 are mounted on the card substrate 1 being arranged like columns. That is, the distance from the connection terminals 3 a to 3 g of the multi-media card is increased in order of the varistors 11 a to 11 e, the controller chip 33 and the plural memory chips 34 a, 34 b, and they are arranged like columns from one side of the card substrate 1 toward the opposing side thereof.
  • the second varistors 11 a to 11 e for finally releasing the overvoltage are closest to the connection terminals 3 a to 3 g to which the overvoltage will be applied, and the nonvolatile memory chips 34 a, 34 b storing the data are the remotest, producing the effect for absorbing the surge of high-speed pulses. Therefore, a high reliability is obtained in regard to reinforcing the prevention of electrostatic damage to the controller chip 33 owing to the varistors 11 a to 11 e, and to protecting the data stored in the nonvolatile memory chips 34 a and 34 b.
  • the through holes 40 are formed at deviated positions in the connection terminals 3 a to 3 g. That is, as shown in detail in FIG. 7 (A), the through hole 40 is formed in the connection terminal 3 a exposed from the IC card at a position deviated from the slide surface of the connection terminal 3 a. The position of deviation may be as shown in FIG. 7 (B). Then, even when the IC card is attached to, or detached from, the mounting slot, the terminal 40 A of the slot does not come into slide contact with the through hole 40 and does not exert a mechanical force to the through hole 40 . This prevents a probability in that the pattern of the connection terminal 3 a is cracked starting from the through hole 40 , or the periphery of the through hole is worn out causing a damage thereto.
  • the controller chip 33 and the nonvolatile memory chips 34 a, 34 b as a whole are molded with a thermosetting resin 55 .
  • the varistor element may be provided inside the mold or outside the mold.
  • no through hole 40 is included in the region molded with the thermosetting resin 55 . This precludes such a probability that the molding resin 55 flows to the back side of the card substrate 1 through the holes 40 to cause defective molding when the molding is effected with the application of pressure.
  • a metal cap 56 is covering the surface of the card substrate 1 on where there are mounted varistors 11 a to 11 e, controller chip 33 and nonvolatile memory chips 34 a, 34 b outside the mold. This provides a countermeasure against EMI (electro magnetic interference) as compared with the resin cap, accomplishing the sealing by mechanical fastening or the sealing of cap at a high temperature.
  • EMI electro magnetic interference
  • FIG. 25 illustrates several kinds of structures of the metal caps 56 .
  • FIG. 25 (A) illustrates a metal cap formed by forging piece by piece in an isolated manner and having a small step for sticking a label
  • FIG. 25 (B) illustrates a metal cap formed by forging followed by blanking piece by piece in an isolated manner
  • FIG. 25 (C) illustrates a metal cap formed by reducing a metal plate.
  • FIG. 25 (D) is a perspective view of when the metal cap obtained by reducing the metal plate of FIG. 25 (C) is viewed from the back side. Corner portions have been cut way in advance to avoid wrinkles at the time of reduction.
  • FIG. 8 illustrates a portion of the multi-media card in which the nonvolatile memory chips are connected by stitch bonding.
  • FIG. 9 is a vertical sectional view illustrating the stitch-bonded portions.
  • the nonvolatile memory chips 34 a and 34 b are mounted on the card substrate 1 in a manner of being stacked in a plural number but with their positions being so deviated that their external terminals 52 a, 52 b are exposed.
  • the external terminals 52 a, 52 b of the nonvolatile memory chips that receive the same signals from the controller chip 33 are successively connected in series with the bonding wires 57 .
  • a bonding method like a so-called stitch-sewing, i.e., a stitch-bonding method.
  • the bonding wires can be shortened as a whole compared to the case of connecting the controller chip 33 to the external terminals 52 a, 52 b using separate bonding wires 43 a, 43 b as is done in FIG. 5 .
  • the number of the bonding wires can be decreased in the region of bonding patterns. In this respect, too, it is allowed to decrease the probability of undesired contact or breakage of the contact wires that occurs when they are arranged too densely.
  • the nonvolatile memory chips 34 a, 34 b must be selected separately.
  • the stitch-bonding cannot be employed for the bonding wires 43 a, 43 b for transmitting the chip selection signals /CE 0 , /CE 1 ; i.e., the wires 43 a, 43 b are bonded in the same manner as in FIG. 5 .
  • FIG. 10 (A) illustrates the case of when the nail head bonding is utilized.
  • the end of the bonding wire is torn away like a crescent. Therefore, the next bonding point must be another place from the end point. Namely, the stitch bonding is completed with bonding wires 57 , 57 that are inevitably cut into plural pieces.
  • FIG. 10 (B) illustrates a case of utilizing the wedge bonding.
  • FIG. 11 illustrates on a plane the constitution of the multi-media card having a structure in which four pieces of nonvolatile memory chips are stacked.
  • FIG. 12 is a vertical sectional view thereof.
  • the four pieces of nonvolatile memory chips 34 a to 34 d are mounted on the card substrate 1 being stacked with their positions being so deviated that the external terminals 52 a to 52 d are exposed.
  • the external terminals 52 a to 52 d of the nonvolatile memory chips 34 a to 34 d that receive the same signals from the controller chip 33 are successively connected in series using the bonding wires 60 like the stitch-bonding.
  • the nonvolatile memory chips 34 a to 34 d must be separately selected.
  • the stitch-bonding is not employed-for the bonding wires 43 a to 43 d for transmitting the chip selection signals /CE 0 to /CE 3 ; i.e., the wires 43 a to 43 d are bonded in the same manner as in FIG. 5 .
  • the stitch-bonding can be effected if the chip selection signal is generated in the form of an ID command.
  • FIG. 11 employs an electrically conducting shielding pattern 61 shown in FIG. 12 for the card substrate 1 in order to further relax the effect of electrostatic discharge taking place near the card substrate. That is, the wide electrically conducting shielding pattern 61 is formed on the exposed surfaces of the connection terminals 3 a to 3 g of the card substrate 1 . Though there is no particular limitation, the electrically conducting shielding pattern 61 may be connected to the connection terminals 3 f, 3 g for supplying ground power source Vss, or may be floated since it has a relatively large surface area. The electrically conducting shielding pattern 61 disperses the static electricity.
  • the terminals for receiving the chip selection signals CE 0 to /CE 3 among the external terminals 52 a to 52 d of the nonvolatile memory chips 34 a to 34 d are located at the ends of the arrangements of the external terminals, and are separately connected to the external terminals 51 of the controller chip 33 through the bonding wires 43 a to 43 d. Quite the same holds even for the stacked structure of FIG. 8 .
  • the plural nonvolatile memory chips are separately selected as shown in FIGS.
  • the terminals for receiving the chip selection signal among the external terminals of the nonvolatile memory chips must be separately connected to the external terminals 51 for producing a chip selection signal of the controller chip 33 . Even if the stitch-bonding method cannot be adapted to these portions, therefore, a necessary connection can be accomplished without hindered by other bonding wires since the external terminals for receiving he chip selection signal have been disposed at the ends of the nonvolatile memory chips. The effect appears conspicuously as the number of the nonvolatile memory chips that are stacked increases. When two pieces of nonvolatile memory chips are stacked as shown in FIG. 5, two bonding wires can be easily drawn in parallel from a single bonding pattern by using a wire bonder having a high degree of precision. In this case, too, no inconvenience occurs even when the external terminal for receiving the chip selection signal is disposed at an end of the chip though the stitch-bonding is not employed.
  • FIG. 13 is a view illustrating another example of the multi-media card
  • FIG. 14 is a vertical sectional view illustrating a portion thereof.
  • two sets of nonvolatile memory chips are mounted on the card substrate 1 , each set comprising two pieces of nonvolatile memory chips that are stacked, and a single-phase wiring is formed on one surface only of the card substrate 1 , the single-phase wiring including wiring patterns and bonding patterns together with the connection terminals.
  • COB chip-on-board
  • connection terminals 3 a to 3 g, wiring patterns 35 , 37 , bonding pattern 38 , bonding patterns 39 A, 39 C, and wiring pattern 39 B are all formed on the mounting side of the card substrate 1 .
  • the connection terminals 3 a to 3 g and the wiring pattern 35 are exposed on the surface through openings formed in the card substrate 1 , enabling the varistors 11 a to 11 e to be connected.
  • the bonding patterns 38 , 39 A and 39 C are exposed on the surface through openings formed in the card substrate 1 , so as to be bonded to the external terminals 50 , 51 of the controller chip 33 and to the external terminals 52 a to 52 d of the nonvolatile memory chips 34 a to 34 d.
  • FIG. 13 the connection terminals 3 a to 3 g, wiring patterns 35 , 37 , bonding pattern 38 , bonding patterns 39 A, 39 C, and wiring pattern 39 B are all formed on the mounting side of the card substrate 1 .
  • the stitch-bonding is employed to neither the bonding between the bonding pattern 39 A and the external terminals 52 a, 52 b of the nonvolatile memory chips 34 a, 34 b nor to the bonding between the bonding pattern 39 C and the external terminals 52 c, 52 d of the nonvolatile memory chips 34 c, 34 d.
  • the stitch-bonding same as that of FIG. 8 may be employed except for the chip selection signals.
  • each set comprising two pieces of nonvolatile memory chips that are stacked as shown in FIG. 13
  • the thickness can be decreased compared to when four pieces are stacked as in FIG. 11 . Therefore, when two sets of the nonvolatile memory chips are mounted on the card substrate 1 , each set comprising four pieces of nonvolatile memory chips that are stacked, then, the storage capacity of two folds as great can be obtained with the same height as that of the four-piece-stacked structure of FIG. 11 .
  • the card controller 33 may be arranged with its lengthwise direction in parallel with the neighboring side and the nonvolatile memory chip may be arranged in a direction nearly at right angles with the direction of arrangement of the connection terminals 3 a to 3 g. Then, the nonvolatile memory chips can be efficiently mounted on the surface of the card substrate 1 .
  • the divisional stacked structure and the structure for arranging the connection terminals 3 a to 3 g and the controller chip 33 along the two sides of the card substrate 1 make it easy to mount the nonvolatile memory chips on the card substrate of a specified size maintaining an increased density or to mount the nonvolatile memory chips in a increased number.
  • FIG. 15 illustrates a further multi-media card employing the above divisional stacked structure and a structure in which the connection terminals and the controller chip are arranged along the two neighboring sides of the card substrate.
  • This example is different from that of FIG. 13 in regard to that the connection terminals, wiring patterns and bonding patterns are formed on both surfaces of the card substrate 1 and that the directions of the stacked nonvolatile memory chips are oriented.
  • connection terminals 3 a to 3 g and the wiring patterns 39 B are formed on the back surface of the card substrate, and the wiring patterns 35 , 37 , bonding pattern 38 , and bonding patterns 39 A, 39 C are formed on the surface of the card substrate 1 .
  • Through holes 40 A are used for connecting the wiring pattern 39 B to the bonding patterns 39 A, 39 C.
  • FIG. 15 does not employ the stitch bonding, either. However, the stitch bonding like that of FIG. 8 may be employed except for the chip selection signals.
  • the divisional stacked structure and the structure for arranging the connection terminals 3 a to 3 g and the controller chip 33 along the two sides of the card substrate 1 in the multi-media card of FIG. 15, make it easy to mount the nonvolatile memory chips on the card substrate of a specified size maintaining an increased density or to mount the nonvolatile memory chips in an increased number.
  • the through holes in the mold may be filled with an electrically conducting paste or a solder resist to prevent the leakage of the molding resin.
  • FIGS. 16 and 17 illustrate examples in which the controller chip is mounted and stacked on the memory chip.
  • the external terminals 51 of the controller chip 33 are connected to the external terminals 52 of the nonvolatile memory chip 34 based on the direct interchip bonding by using the bonding wires 70 .
  • power source wiring patterns 71 A, 72 A are formed on the back surface of the card substrate 1 , and the bonding patterns 71 B, 72 B connected through the holes 71 D, 72 D are connected to the nonvolatile memory chip 34 through the bonding wires 71 C, 72 C.
  • the power sources Vcc, Vss may be fed through the terminals 51 and 52 .
  • the structure for mounting the varistors 11 a to 11 e is the same as the one described above, and the circuit elements having the same functions as those of FIG. 15 are denoted by the same reference numerals but their description is not repeated.
  • FIG. 17 illustrates a structure in which the memory chip and the controller chip are stacked by utilizing an LOC (lead-on-chip).
  • Reference numerals 73 a to 73 g denote some of the leads of a lead frame for the LOC.
  • the leads 73 e and 73 f for the power sources Vcc, Vss are extending like hooks and are forming path bars 74 A and 74 B.
  • the nonvolatile memory chip 34 is secured to the path bars 74 A, 74 B, and the controller chip 33 is secured to the nonvolatile memory chip 34 .
  • the external terminals 50 of the controller chip 33 are connected to the leads 73 a to 73 g through the bonding wires 4 .
  • the external terminals 51 of the controller chip 33 are connected to the external terminals 52 of the nonvolatile memory chip 34 by the direct interchip bonding method using the bonding wires 70 .
  • the path bars 74 A and 74 B are connected to the nonvolatile memory chip 34 through the bonding wires 75 , 75 .
  • the varistors 11 a to 11 e are surface-mounted on the corresponding leads using an electrically conducting paste such as Ag paste.
  • FIG. 18 illustrates a still further IC card employing the COB structure.
  • FIG. 19 is a vertical sectional view of the IC card
  • FIG. 20 is a view illustrating the electrically conducting pattern formed on the bottom surface of the card substrate of the IC card of FIG. 18 .
  • Electrically conducting patterns 80 a to 80 g are formed on the bottom surface of the card substrate 84 , and openings 81 a to 81 g are formed in the card substrate 84 being corresponded thereto.
  • the electrically conducting patterns 80 a to 80 f constitute connection terminals exposed from the IC card.
  • the semiconductor integrated circuit chip 83 is connected to the electrically conducting pattern 80 f via the opening 81 g and is served with ground voltage Vss as a substrate potential.
  • Bonding pads 85 a to 85 f constituting the external terminals of the semiconductor integrated circuit chip 83 are connected to the connection electrodes 80 a to 80 f using the bonding wires 86 through the openings 81 a to 81 f.
  • varistors 82 a to 82 e comprising chiefly semiconductor ceramics are surface-mounted across the connection terminals 80 a to 80 g and the electrically conducting patterns 80 g through the openings 81 a to 81 g using an electrically conducting paste such as Ag paste in order to reinforce the prevention of electrostatic damage to the semiconductor integrated circuit chip 83 in the same manner as described above.
  • FIG. 21 illustrates an IC card having a notice for preventing the electrostatic damage.
  • An IC card such as the multi-media card mounting the semiconductor integrated circuit chip with plural connection terminals being exposed, is provided on its surface with a notice 90 , such as “DON'T TOUCH THE CONNECTION TERMINALS” as shown in FIG. 21 (A) so that the user will not touch the connection terminals 3 a to 3 g. On this region may further be written a production management code.
  • FIG. 21 (B) further, an indication is provided to clearly indicate the position for holding the IC card by fingers, such as notice indication 91 in the form of a finger printed on a position where the IC card should be held by fingers at the time of attachment or detachment.
  • notice indication 91 in the form of a finger printed on a position where the IC card should be held by fingers at the time of attachment or detachment.
  • a packing material 92 such as a laminated film, a paper box or a plastic casing packing the IC card may be provided with a notice 93 warning not to touch the-connection terminals 3 a to 3 g of the IC card.
  • the notices 90 , 93 and indication 91 are helpful for preventing the IC card from being electrostatically damaged due to unexpected handling by a person who is not familiar with the IC card.
  • FIG. 22 illustrates a method of fabricating the IC card shown in FIGS. 4 and 5.
  • varistors are mounted on the predetermined electrically conducting patterns of the card substrate such as a PCB substrate or a tape substrate (S 1 ).
  • a solder paste or a silver paste is used.
  • the paste is cured (baked) (S 2 ), and a required number of the semiconductor integrated circuit chips are die-bonded to the electrically conducting pattern on the card substrate (S 3 ).
  • the surface of the card substrate is cleaned with a plasma (S 4 ).
  • the bonding pads of the semiconductor integrated circuit chips that are die-bonded are bonded to the electrically conducting pattern by thermal ultrasonic method using gold bonding wires (S 5 ).
  • the semiconductor integrated circuit chips and the bonding wires are then sealed by potting the resin (S 6 ) which is then cured by baking (S 7 ).
  • a metal cap is secured onto the card substrate by adhesion or by plastic insert molding.
  • the varistors are first mounted on the card substrate and, then, the semiconductor integrated circuit chips are die-bonded or wire-bonded. Therefore, the protection by the varistors is accomplished at the time of assembling the IC card, contributing to improving the yield of the IC card.
  • the varistors may be mounted afterwards depending upon the convenience in the production, such as temperature conditions, etc.
  • FIG. 23 illustrates an IC card giving attention to recovering the data.
  • the basic constitution is the same as FIG. 5, and the difference is the possession of plural data recovery terminals.
  • the connection between the control latch 33 and the nonvolatile memory chips 34 a, 34 b is simplified in order to emphasize the connection to the data recovery terminals.
  • the circuit elements having the same functions as those of FIG. 5 are denoted by the same reference numerals, but their detailed description is not repeated.
  • the controller latch 33 has an input terminal (also simply written as test terminal /TEST) for receiving a test signal /TEST pulled up in the circuit as one of the external terminals 51 .
  • the test terminal /TEST controls the interface terminal to the nonvolatile memory chips 34 a, 34 b and, controls, particularly, the output terminal and the input/output terminal to assume a state of a high output impedance or to assume a state in which the input/output operation cannot be executed.
  • data recovery terminals 92 On the card substrate 1 are formed data recovery terminals 92 that are connected to all external terminals 51 of the controller chip 33 on the side of the memory interface in a one-to-one manner through wirings 91 . There are further provided a ground terminal 96 for recovering the data that is connected, through a wire 95 , to an external terminal for the ground power source Vss among the external terminals 50 of the controller chip 33 on the side of the cathode interface, and a power source terminal 94 for recovering the data that is connected, through a wire 93 , to an external terminal for the power source voltage Vcc among the external terminals 50 of the controller chip 33 on the side of the card interface.
  • reference numeral 90 denotes a guard ring added to the card substrate 1 for preventing the electrostatic damage. The guard ring 90 surrounds the card substrate 1 and is connected to the ground power source terminal of the circuit.
  • the data evaluation terminals 92 , 94 and 96 have been formed on the card substrate 1 .
  • access can be made directly to the nonvolatile memory chips 34 a, 34 b from an external unit through the data evaluation terminals 92 , 94 and 96 . Therefore, even when the controller chip 33 is damaged, the data that are remaining in the nonvolatile memory chips 34 a, 34 b can be easily recovered.
  • the controller chip 33 may have a privacy protection function that executes the encryption for the data to be written into the nonvolatile memory and executes the decryption for the data read out from the nonvolatile memory.
  • the data are recovered by the manufacturer of the IC card or by an authorized person by decrypting the data read out from the nonvolatile memory chips.
  • FIG. 24 illustrates a procedure of a data recovery processing for the IC card equipped with the data evaluation terminals.
  • the data are recovered from a multi-media card (MMC) of which the controller became defective due to electrostatic damage that could not be prevented by the input protection circuit or the varistors (S 10 ).
  • the data can further be recovered from those multi-media cards (MMC) of which the connection terminals were physically damaged.
  • the cap 56 is removed from the object MMC (S 11 ), and a probe such as a tester is brought into contact with the data evaluation terminals 92 , 94 , 96 (S 12 ).
  • the terminal for receiving the test signal /TEST is fixed to the low level, and the memory interface terminal of the controller chip 33 is controlled to assume a high impedance state (state in which the input/output operation cannot be executed) (S 13 ).
  • the nonvolatile memory chip contained in the MMC is released from the control operation by the controller chip, and becomes accessible directly through the data evaluation terminals 92 , 94 , 96 .
  • the data are read out from the nonvolatile memory chip (S 14 ).
  • the controller chip 33 has the privacy protection function that executes the encryption for the data that are written into the nonvolatile memory chip and executes the decryption for the data read out from the nonvolatile memory. Therefore, the data that are read out are decrypted without passing through the controller chip 33 .
  • the thus decrypted data are written into a new MMC in an ordinary manner through the connection terminals 3 a to 3 g (S 15 ).
  • the new MMC having the recovered data is offered to the user (S 16 ).
  • the specifications of encryption of the controller chip can be confirmed by a production trace code of the card or by a production code written in the nonvolatile memory.
  • FIG. 26 illustrates a flush memory chip.
  • reference numeral 103 denotes a memory array which includes a memory mat, a data latch circuit and a sense latch circuit.
  • the memory mat 103 has many electrically erasable and writable nonvolatile memory cell transistors.
  • the memory cell transistor is constituted by a source S and a drain D formed in the semiconductor substrate or in a memory well SUB, a floating gate FG formed in the channel region via a tunnel oxide film, and a control gate CG overlapped on the floating gate via an interlayer-insulating film.
  • the control gate CG is connected to a word line 106
  • the drain D is connected to a bit line 105
  • the source S is connected to a source line that is not shown.
  • the external input/output terminals I/O 0 to I/O 7 are also used as an address input terminal, a data input terminal, a data output terminal and a command input terminal.
  • An X-address signal input through the external input/output terminals I/O 0 to I/O 7 is fed to an X-address buffer 108 through a multiplexer 107 .
  • An X-address decoder 109 decodes internal complementary address signals output from the X-address buffer 108 to drive the word line.
  • a sense latch circuit that is not shown is provided on one end side of the bit line 105 , and a data latch circuit that is not shown is provided on the other side thereof.
  • the bit line 105 is selected by a Y-gate array circuit 113 based on a selection signal output from a Y-address decoder 111 .
  • a Y-address signal input through the external input/output terminals I/O 0 to I/O 7 is preset to a Y-address counter 112 , and an address signal which gradually increases starting from the preset value is given to the Y-address decoder 111 .
  • the bit line selected by the Y-gate array circuit 113 is rendered conductive to the input terminal of the output buffer 15 .
  • the bit line selected by the Y-gate array circuit 113 is rendered conductive to the output terminal of the input buffer 117 through a data control circuit 116 .
  • the connection among the output buffer 115 , input buffer 117 and the input/output terminals I/O 0 to I/O 7 is controlled by the multiplexer 107 .
  • a command fed through the input/output terminals I/O 0 to I/O 7 is given to a mode control circuit 118 via the multiplexer 107 and the input buffer 117 .
  • the data control circuit 116 feeds data of a logical value controlled by the mode control circuit 118 to the memory array 103 .
  • a control signal buffer circuit 119 receives, as access control signals, the chip enable signal /CE, an output enable signal /OE, a write enable signal /WE, and a signal /SC for instructing the data latch timing, as well as a reset signal /RES and a command/data enable signal /CDE.
  • the mode control circuit 118 controls a signal interface function to the external unit depending on the state of the signals, and further controls the internal operation according to a command code. When a command or a data is input to the input/output terminal I/O 0 to I/O 7 , the signal /CDE is asserted. When it is a command, a signal /WE is asserted and when it is a data, the signal /WE is negated.
  • the mode control circuit 118 distinguishes the command, data and address that are input in a multiplex manner through the external input/output terminals I/O 0 to I/O 7 .
  • the mode control circuit 118 asserts a ready/busy signal R/B during the erasing or writing operation, and informs an external unit of the state thereof.
  • An internal power source circuit 120 forms various operation sources 121 for writing, erasing, verifying and reading, and feeds them to the X-address decoder 109 and to the memory cell array 103 .
  • the mode control circuit 118 controls the flush memory as a whole according to the command.
  • the operation of the flush memory is basically determined by the command.
  • the command assigned to the flush memory is read out, erased or written.
  • the flush memory has a status register 122 for indicating the internal state, and its content can be read out through the input/output terminal I/O 0 to I/O 7 by asserting the signal /OE.
  • the present invention can be applied to the memory cards other than the multi-media card, such as a compact flush memory and the like.
  • the structure in which the memory chips are stacked in a deviated manner the structure in which the through holes are deviated from the connection terminals of the IC card, the structure in which the through holes are formed outside the molding region, the structure for stitch-bonding the stacked semiconductor integrated circuit chips and arranging the CS input terminals at the end of the chips, the IC card in which the stacked nonvolatile memories are mounted being divided into plural groups, and the IC card having note and data recovery terminals, are not necessarily limited to those constitutions having varistors.
  • the memory mounted on the IC card of the present invention is not limited to the nonvolatile memory but may be a volatile memory (SRAM, DRAM, etc.). Further, the IC card may be the one mounting both the nonvolatile memory and the volatile memory.
  • an IC card is provided that is capable of reinforcing the prevention of the electrostatic damage without increasing the cost of the semiconductor integrated circuit chip.
  • an IC card capable of easily recovering the data in the memory card when the data remain safe in the memory even when the input circuit of the semiconductor integrated circuit chip is electrostatically damaged.

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Abstract

An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements. The varistors have been selected by taking into consideration a relationship between the characteristics and the ability of the first overvoltage protection elements contained in the semiconductor integrated circuit chip, and exhibit the effect for preventing the electrostatic damage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a division of application Ser. No. 09/689,663 filed Oct. 13, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to technology for suppressing ESD (also called electrostatic discharge damage) of a semiconductor integrated circuit chip mounted on an IC card. More particularly, the invention relates to technology that can be effectively adapted to memory cards such as multimedia cards.
2. Prior Art
A variety of memory cards have heretofore been provided for storing multi-media data in compact sizes having decreased weights. For example, there has been provided a multi-media card having a memory and a memory controller mounted on a card substrate, establishing an interface to a host unit using a small number of signals.
Giving priority to a small size and reduced weight, the memory card of this type has the connection terminals for connection to the host unit, the connection terminals being exposed on the card substrate, but has no particular mechanism such as cover for protecting the terminals. When the exposed terminals are touched at the time when the memory card is removed from the host unit, therefore, a semiconductor integrated circuit chip connected to the exposed terminals may be damaged. Usually, the semiconductor integrated circuit chip is provided with an input protection circuit for preventing the input circuit from the electrostatic damage. The input protection circuit is constituted by, for example, disposing, between an input terminal and a power source terminal, an element such as a diode whose connection state is reversed relative to the amplitude voltage of the input signal. It is, however, expected that the memory card is carried by itself and is frequently attached to, and detached from, the host unit. Thus, the present inventors have found the importance of reinforcing the prevention of the electrostatic damage.
Though the technical field is different from the above memory card, Japanese Patent Laid-Open No. 209379/1998 discloses technology for reinforcing the protection of input against the electrostatic damage. According to this technology, a metal wiring layer is formed maintaining a gap (discharge gap) in which static electricity could be discharged relative to an electrode layer on a semiconductor substrate so that when static electricity has entered into the electrode layer, the static electricity is discharged to the metal wiring layer, preventing the static electricity that has entered into the electrode layer from entering into the semiconductor element. Further, Japanese Patent Laid-Open No. 271937/1995 discloses a circuit employing a gate-source protection diode of a MOSFET that is externally attached to a semiconductor integrated circuit chip to prevent the electrostatic damage.
There has further been provided a varistor of semiconductor ceramics from the standpoint of protecting the circuitry from an overvoltage.
SUMMARY OF THE INVENTION
The present inventors have forwarded the following study from the standpoint reinforcing the prevention of electrostatic damage of the IC card such as a memory card having connection terminals that are exposed.
First, it became obvious that when Zener diodes of a large size are integrated on a semiconductor integrated circuit chip to obtain an energy withstand amount that helps reinforce the prevention of electrostatic damage, the area efficiency decreases in the midst of fine circuit elements, driving up the cost to a conspicuous degree.
Second, when an element for protection from an overvoltage is attached to the semiconductor integrated circuit chip to reinforce the prevention of electrostatic damage, the efficiency for preventing the electrostatic damage does not increase unless consideration is given to a relationship between the characteristics and the ability of the overvoltage protection circuit incorporated in the semiconductor integrated circuit chip. Besides, the externally attached circuit elements that are large in size or that are large in number, cause an increase in the size and thickness of the IC card. Such a viewpoint has not been taught by the above prior art. In this specification, the overvoltage stands for a surge voltage or a transient voltage that generates electrostatically.
Third, even when the countermeasure against the electrostatic damage is taken by using the externally attached circuit elements, there is no guarantee that the device is absolutely safe from the damage when it is handled in an unexpected manner by a person who is not familiar with. It is therefore necessary to make perfection more perfect.
Fourth, even when the input circuit of the semiconductor integrated circuit is electrostatically damaged, it can be expected that the data in the memory remain safe. In such a case, recovering the data from the memory card gives an excellent feature relieving the data and offering an increased safety of the memory card as a storage medium.
Fifth, a countermeasure against the electrostatic damage by the externally attached circuit elements, decreases, at least, the vacant region on the card substrate correspondingly. Even in this case, it becomes necessary to avoid concentration of wiring patterns and the concentration of bonding wires that could become a cause of malfunction due to undesired leakage of signal lines. This contrivance is necessary even when the memory capacity of the memory card is to be increased.
The present invention provides an IC card capable of reinforcing the prevention of electrostatic damage without driving up the cost of the semiconductor integrated circuit chip.
The present invention further provides an IC card capable of reinforcing the prevention of electrostatic damage by attaching overvoltage protection elements to the semiconductor integrated circuit chip without causing a great change in the size and thickness of the card.
The invention further provides an IC card which can be expected to prevent electrostatic damage caused by an unexpected handling by a person who is not familiar with.
The invention further provides an IC card capable of easily recovering the data in the memory card even when the input circuit of the semiconductor integrated circuit chip is electrostatically damaged, provided the data in the memory remain safe.
The invention further provides an IC card capable of avoiding the concentration of wiring patterns and bonding wires that could cause a malfunction due to undesired leakage of signal lines even when the vacant region on the card substrate is decreased by the countermeasure against the electrostatic damage by externally attaching the circuit elements.
The invention further provides an IC card having a relatively large storage capacity in a relatively small size.
The above and other objects as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.
Briefly described below are representative examples of the invention disclosed in this application.
[1] Second overvoltage protection elements capable of reinforcing the prevention of electrostatic damage are externally attached to the semiconductor integrated circuit chip by taking into consideration a relationship to first overvoltage protection elements that are integrated in a semiconductor integrated circuit chip. That is, an IC card has a semiconductor integrated circuit chip mounted on a card substrate and plural connection terminals that are exposed, wherein the connection terminals are connected to predetermined external terminals of the semiconductor integrated circuit chip, the first overvoltage protection elements connected to the external terminals are integrated on the semiconductor integrated circuit chip, and the second overvoltage protection elements connected to the connection terminal are mounted on the card substrate.
According to a first aspect, the second overvoltage protection elements are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.
According to a second aspect, a voltage greater than a rated voltage applied to the second overvoltage protection elements for flowing a specified pulse current, is the voltage that enables the first overvoltage protection elements to flow only a current smaller than the above specifued pulse current.
According to a third aspect, the second overvoltage protection elements are variable resistor elements having a breakdown voltage larger than that of the first overvoltage protection elements.
According to a fourth aspect, the second overvoltage protection elements have a capacity larger than that of the first overvoltage protection elements.
This enables a high-speed surge pulse to be by-passed through a low resistance.
According to a fifth aspect, the second overvoltage protection elements have a breakdown voltage smaller than a breakdown voltage of the first overvoltage protection elements.
According to a sixth aspect, the second overvoltage protection elements has a breakdown voltage smaller than a breakdown voltage of a circuit that is protected by the first overvoltage protection elements.
In any aspect, it can be said that the second overvoltage protection elements exhibit the effect for preventing the electrostatic damage, since consideration has been given to a relationship between the characteristics and the ability of the first overvoltage protection elements that are contained in the semiconductor integrated circuit chip.
The second overvoltage protection elements may have their ends on one side thereof connected to the power source connection terminals of the card substrate and may have their ends on the other side thereof connected to the signal connection terminals. The signal connection terminals are connected to the corresponding external terminals of the semiconductor integrated circuit chip. Here, the signal propagation distances from the signal connection terminals to the corresponding second overvoltage protection elements are shorter than the signal propagation distances from the signal connection terminals to the corresponding external terminals of the semiconductor integrated circuit chip. This prevents the semiconductor integrated circuit chip from being directly affected destructively by the overvoltage before the second overvoltage protection elements work in response to the overvoltage.
The second overvoltage protection elements may be varistors of the surface-mount type comprising chiefly semiconductor ceramics, an array of chip diodes, chip capacitors or chip transistors. This makes it possible to decrease the mounting area or the occupation area of the second overvoltage protection elements. The surface mounting lowers the cost of production.
When a memory card such as a multi-media card is used as an IC card, the semiconductor chip is a controller chip, and one or plural memory chips (e.g., nonvolatile memory chips) connected to the controller chip are further mounted on the card substrate. The controller chip has a memory control function for controlling the reading/writing operation for the memory chips according to an instruction from an external unit.
When a consideration is given to data security and copyright, the controller chip may employ a privacy protection function for effecting the encryption for the data written into the memory chip and for effecting the decryption for the data read out from the memory chip.
When a consideration is given to preventing the electrostatic damage even during the steps of manufacturing the IC card, the second overvoltage protection elements connected to the connection terminals should be mounted on the card substrate, first, and, then, predetermined external terminals of the semiconductor integrated circuit chip should be connected to the connection terminals. Then, the protection by the second overvoltage protection elements is obtained in a step of connecting the semiconductor integrated circuit chip.
[2] The invention is concerned with an IC card having a semiconductor integrated circuit chip mounted on a card substrate, wherein plural connection terminals are exposed, predetermined external terminals of said semiconductor integrated circuit chip are connected to the connection terminals, first overvoltage protection elements connected to the external terminals are integrated on the semiconductor integrated circuit chip, and second overvoltage protection elements connected to the connection terminals are mounted on the card substrate, and wherein the second overvoltage protection elements may be connected by being surface-mounted on the electrically conducting pattern formed on the card substrate. This makes it possible to decrease the cost of mounting the second overvoltage protection elements.
When a memory card such as a multi-media card is used as the IC card, the semiconductor chip is a controller chip, and one or plural memory chips connected to the controller chip are further mounted on the card substrate. Here, bonding wires are used for connecting the connection terminals to the external terminals of the controller chip, and bonding wires are used for connecting the controller chip to the memory chips. Therefore, a number of wiring patterns having the same function as the connection by the bonding wires, need not be densely formed on the card substrate. Space on the controller chip or the memory chips can be used for the wiring. Accordingly, this contributes to decreasing the cost of the card substrate.
When plural memory chips are to be connected in parallel to the controller chip by bonding wires, the memory chips may be mounted on the card substrate in a manner that the chips are stacked one upon the other with their positions being so deviated that the external terminals are exposed, from the standpoint of shortening the lengths of the bonding wires. Therefore, the distance to the controller chip is shortened and the lengths of the bonding wires are shortened compared to when the memory chips are arranged without being stacked one upon the other. This decreases the probability of undesired contact or breakage of the bonding wires. In this case, in particular, a condition should be maintained in that the area on one surface of the card substrate is larger than the total areas of the memory chips and of the controller chip. This is to provide the card substrate with extra space for sufficiently coping with a restrictive condition in that the wiring layer is formed on one surface only of the card substrate. This is not a simple idea of mounting the memory chips in a stacked manner for decreasing the area of the card substrate.
[3] The invention is concerned with an IC card in which plural memory chips and the controller chip for controlling the memory chips are mounted on one surface of the card substrate, wherein when the memory chips are mounted on the card substrate in a manner of being stacked one upon the other with their positions being so deviated that the external terminals are exposed, the external terminals of the memory chips that receive the same signals from the controller chip are successively connected in series by bonding the wires. The bonding method of a so-called stitch sewing is employed. The bonding wires can be shortened as a whole compared to when the controller chip is connected to the external terminals through the bonding wires. In this respect, too, the probability of undesired contact or breakage of lines due to the concentration of the bonding wires can be decreased.
The invention is concerned with an IC card in which plural memory chips and the controller chip for controlling the memory chips are mounted on one surface of the card substrate, wherein when the memory chips are mounted on the card substrate in a manner of being stacked one upon the other with their positions being so deviated that the external terminals are exposed, the external terminals for receiving chip selection signals of the memory chips are located at the ends of the arrangements of the external terminals of the nonvolatile memory chips, and are connected to the controller chip by bonding the wires. In a constitution for separately selecting the plural memory chips, the external terminals for receiving the chip selection signals must be separately connected to the external terminals for outputting the chip selection signal of the controller chip. Therefore, the above stitch-bonding method cannot be employed. However, the external terminals for selecting the chips are arranged at the ends of the memory chips and work to accomplish necessary connection without hindered by other bonding wires.
[4] The memory chips and the controller chip mounted on the card substrate may be arranged in the form of columns. That is, the memory chips are connected to the controller chip, the connection terminals formed on the card substrate are connected to predetermined external terminals of the controller chip, the first overvoltage protection elements connected to the external terminals are integrated on the controller chip, and the second overvoltage protection elements connected to the connection terminals are mounted on the card substrate. The distances from the connection terminals are increased in order of the second overvoltage protection elements, controller chip, and plural memory chips, which are arranged like columns from one side of the card substrate to the opposing side thereof. Owing to this column-like arrangement, the second overvoltage protection elements for finally releasing the overvoltage are located closest to the connection terminals to which an overvoltage is applied, and the memory chips storing the data are located remotest, offering a high reliability from the standpoint of preventing electrostatic damage to the semiconductor chip and protecting the data.
In this case, too, the memory chips may be mounted on the card substrate in a manner of being stacked one upon the other with their positions being so deviated that the external terminals are exposed.
The arrangement of the memory chips and the controller chip mounted on the card substrate is not limited to the column-like arrangement only. When plural connection terminals are arranged along one side between the two neighboring sides of the card substrate, the memory controller is arranged with its lengthwise direction in parallel with the other side of the two neighboring sides, and plural memory chips are arranged in parallel in a direction nearly at right angles with the direction in which the connection terminals are arranged. The connection terminals exposed from the card substrate are connected to predetermined external terminals of the controller chip, the first overvoltage protection elements connected to the external terminals are integrated on the controller chip, and the memory chips are connected to the controller chip. With the connection terminals and the controller chip being arranged along the neighboring two sides of the card substrate, it is allowed to easily increase the density for mounting the memory chips or to increase the number of mounts. If the memory chips are arranged in parallel being divided into a first group in which the memory chips are stacked in a plural number with their positions being so deviated that the external terminals are exposed and a second group in which the memory chips are stacked in a plural number in the same manner, the height of the IC card can be suppressed. The second overvoltage protection elements connected to the connection terminals may be mounted on the card substrate along the direction in which the connection terminals are arranged.
[5] When an IC card is constituted by forming electrically conducting patterns on both surfaces of the card substrate, the electrically conducting patterns may be connected by using through holes that are penetrating through the card substrate. In this case, it is desired that the through holes are arranged outside the molded region that covers the semiconductor integrated circuit chip and the other surface of the card substrate. The molding that is executed while applying a pressure eliminates the probability in that the molding resin flows into the back side of the card substrate passing through the holes.
When the through holes are formed for the connection terminals exposed from the IC card, it is desired that the through holes are formed at positions deviated from the slide surfaces of the connection terminals. Even when the IC card is attached to, or detached from, the mounting slot, therefore, the terminals of the slot do not come into slide contact with the through holes and do not receive mechanical force, preventing such a probability that the patterns of the connection terminals are cracked from the through holes and are damaged.
The invention is concerned with an IC card in which plural connection terminals are exposed on one surface of a card substrate, a semiconductor integrated circuit chip is mounted on the other surface of the card substrate, predetermined external terminals of the semiconductor integrated circuit chip are connected to the connection terminals, first overvoltage protection elements connected to the external terminals are integrated on the semiconductor integrated circuit chip, and second overvoltage protection elements connected to the connection terminals are mounted on the other surface of the card substrate, and wherein the semiconductor integrated circuit chip, the second overvoltage protection elements and the other surface of the card substrate are covered with a metal cap. The metal cap can be formed by reducing a metal plate, by a forging method or by a die casting method. This provides a countermeasure against EMI (electromagnetic interference) compared to the resin cap, and helps accomplish the sealing by mechanical fastening and accomplish the cap-sealing at a high temperature. The resin cap may be blended with an electromagnetic wave-absorbing material such as ferrite, etc. To cope with ESD, electrically conducting particles such as carbon may be mixed.
An electrically conducting shielding pattern may be employed for the card substrate to relax the effect of electrostatic discharge that takes place near the card substrate. That is, the invention is concerned with an IC card in which plural connection terminals are exposed on one surface of a card substrate, and a semiconductor integrated circuit chip is mounted on the other surface of the card substrate, wherein predetermined external terminals of the semiconductor integrated circuit chip are connected to the connection terminals, first overvoltage protection elements connected to the external terminals are integrated on the semiconductor integrated circuit chip, second overvoltage protection elements connected to the connection terminals are mounted on the other surface of the card substrate, and an electrically conducting shielding pattern is formed on one surface of the card substrate except a region of the connection terminals, the electrically conducting shielding pattern being connected to the connection terminal for supplying ground power source or being connected to none of the connection terminals. The electrically conducting shielding pattern disperses the static electricity.
[6] From the standpoint of preventing electrostatic damage of when the IC card is handled in an unexpected manner by a person who is not familiar with, the IC card is provided on the surface thereof with an indication indicating a position where the IC card should be held by fingers (figure of a finger printed on a position at where the IC card should be held by fingers at the time of attachment or detachment), the IC card mounting a semiconductor integrated circuit chip permitting plural connection terminals to be exposed. Further, a notice is written on the surface of the IC card warning not to touch the connection terminals. Besides, a notice is written on the packing member packing the IC card warning not to touch the connection terminals of the IC card.
[7] The invention deals with a IC card giving attention to recovering the stored data, wherein plural connection terminals are exposed, plural memory chips and a controller chip for controlling the memory chips are mounted on a card substrate, the connection terminals are connected to a first group of external terminals of the controller chip, the memory chips are connected to a second group of external terminals of the controller chip, and data evaluation terminals connected to the second group of external terminals are formed on the card substrate.
In case the controller chip becomes no longer capable of executing the memory control due to electrostatic damage, access can be made directly to the memory chips from an external unit through the data evaluation terminals. Therefore, even when the controller chip is destroyed, the data remaining in the memory chips can be easily recovered.
The card substrate may further be provided with a control terminal for controlling the output terminal included in the second group of external terminals of the controller chip to assume a high output impedance state. The damaged controller chip that is placed in an undesired signal output state, can be easily relieved.
The controller chip may often be provided with a privacy protection mechanism for executing the encryption for the data that are written into the memory chips and for executing the decryption for the data read out from the memory chips. In this case, the data are recovered by the manufacturer of the IC card or by an authorized person by decrypting the data read out from the memory chips.
[8] The simplest method of recovering the data from the IC card having the data evaluation terminals, includes a first processing for placing the memory chips in a state where they cannot be controlled by the controller chip, and a second processing for reading out the data from the data evaluation terminals by controlling the memory chips. A data recovery method of when the controller chip has the privacy protection function, includes a first processing for controlling the output terminal included in the second group of external terminals of the controller chip to assume a high output impedance state, a second processing for reading out the data from the data evaluation terminals by controlling the memories, a third processing for decrypting the data read out by the second processing, and a fourth processing for writing the data decrypted by the third processing into another IC card.
Therefore, even in case the input circuit of the semiconductor integrated circuit chip is electrostatically damaged, the data that remain safe in the memory can be easily recovered.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram illustrating a connection terminal of an IC card according to the present invention;
FIG. 2 is an axial sectional view illustrating the structure of a varistor in cross section;
FIG. 3 is a diagram of an I-V line illustrating the characteristics of the varistor;
FIG. 4 is a diagram illustrating the connection of the varistors to the connection terminals of a multi-media card;
FIG. 5 is a diagram illustrating, on a plane, the constitution of the multi-media card chiefly in a state where the circuit elements are mounted;
FIG. 6 is a vertical sectional view of the multi-media card of FIG. 5;
FIG. 7 is a diagram illustrating a state where a through hole is formed in a deviated manner in a connection terminal of the multi-media card;
FIG. 8 is a plan view partly illustrating the multi-media card by applying stitch bonding for connecting the nonvolatile memory chips;
FIG. 9 is a vertical sectional view of a stitch-bonded portion;
FIG. 10 is a diagram illustrating the wire bondings of when a nail head bonding is utilized and when a wedge bonding is utilized;
FIG. 11 is a diagram illustrating, on a plane, the constitution of a multi-media card having a structure in which four pieces of nonvolatile memory chips are stacked;
FIG. 12 is a vertical sectional view illustrating the sectional structure of the multi-media card of FIG. 11;
FIG. 13 is a plan view illustrating a multi-media card applying a structure for stacking the memory chips in a divided manner and a structure in which the connection terminals and the controller chip are arranged along the two neighboring sides of the card substrate;
FIG. 14 is a vertical sectional view illustrating a portion of the multi-media card of FIG. 13;
FIG. 15 is a plan view illustrating another multi-media card applying a structure for stacking the memory chips in a divided manner and a structure in which the connection terminals and the controller chip are arranged along the two neighboring sides of the card substrate;
FIG. 16 is a plan view illustrating a memory card in which the controller chip is placed on the memory chip to stack both of them;
FIG. 17 is a plan view illustrating a folded card by stacking the memory chips and the controller chip by utilizing LOC;
FIG. 18 is a plan view illustrating another IC card applying a COB structure;
FIG. 19 is a vertical sectional view of the IC card of FIG. 18;
FIG. 20 is a view illustrating an electrically conducting pattern formed on the bottom surface of a card substrate of the IC card of FIG. 18;
FIG. 21 is a view illustrating an IC card describing a notice or a sign of caution for preventing electrostatic damage;
FIG. 22 is a flowchart illustrating a method of fabricating an IC card mounting varistors;
FIG. 23 is a plan view of an IC card giving attention to recovering the data;
FIG. 24 is a flowchart illustrating a procedure of a data recovery processing for an IC card having data evaluation terminals;
FIG. 25 is a diagram illustrating several kinds of structures of metal caps;
FIG. 26 is a block diagram illustrating the constitution of a flush memory chip; and
FIG. 27 is a sectional view schematically illustrating the structure of a nonvolatile memory cell transistor for the flush memory chip.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
<Reinforcing the Function for Preventing Electrostatic Damage by Using Varistors>
First, described below is a principle for reinforcing the function for preventing electrostatic damage to the semiconductor integrated circuit by using externally attached circuit elements such as varistors.
FIG. 1 illustrates a connection terminal of an IC card according to the invention. The IC card that is shown has a semiconductor integrated circuit chip 2 mounted on a card substrate 1, and, typically, has connection terminals 3 that are exposed. The connection terminals 3 are interface terminals for electrically connecting the IC card to a host unit to which the IC card is detachably attached.
The connection terminals 3 are connected to predetermined external terminals 4 of the semiconductor integrated circuit chip 2. The external terminals are input terminals which are connected to, for example, a CMOS inverter in the initial stage of the input circuit via signal lines 5. The CMOS inverter is constituted by a p-channel field-effect transistor (often described as unit MOS transistor) Q1 and an n-channel MOS transistor Q2 disposed in series between a ground terminal Vss and a power source terminal Vcc of the circuit. In the semiconductor integrated circuit chip 2 are integrated diodes 7, 8 which are first overvoltage protection elements connected to the external terminal 4, a thyristor 9 and a clamping MOS transistor Q5. On the card substrate 1 is mounted a varistor 11 which is a second overvoltage protection element connected to the connection terminal 3. The diodes 7, 8, thyristor 9 and clamping MOS transistor Q5 constitute an input protection circuit 6.
The concept of cathode and drain of the MOS transistor is determined depending upon the direction of the operation voltage. In this specification, for convenience, the names determined in the state of normal operation by the operation voltages Vss and Vcc are used as the names of terminals.
The anode of the diode 7 is connected to the input signal line 4, the cathode thereof is connected to the power source terminal Vcc, the cathode of another diode 8 is connected to the input signal line 4 and the anode thereof is connected to the ground terminal Vss. The thyristor 9 is equivalently constituted by a pnp transistor Q3 and an npn transistor Q4, and the anode thereof is connected to the input signal line 4, and the cathode thereof is connected to the ground terminal Vss. The MOS transistor Q5 is a clamping MOS transistor of the form of a so-called diode connection of which the gate and source are connected to the ground terminal Vss and of which the drain is connected to the input signal line 4.
Reference numerals 12 and 13 are input protection resistors. Symbols Q6 and Q7 are a p-channel clamping MOS transistor of the form of a so-called diode connection of which the gate and source are connected together and an n-channel clamping MOS transistor. The clamping MOS transistors Q6 and Q7 are circuit elements having an auxiliary function to cope with the case where an overvoltage has leaked from the input protection circuit 6. When used alone, they cannot work as the first overvoltage protection element but work as the overvoltage protection element in cooperation with other circuit element.
In a normal state, the connection terminal 3 receives a signal having a voltage amplitude between the ground voltage Vss and the power source voltage Vcc. In this case, the diodes 7, 8, thyristor 9, and clamping MOS transistors Q5, Q6 and Q7 are all connected in a reversed manner.
When an overvoltage of a positive polarity is applied to the connection terminal 3 due to electrostatic discharge, the diode 7 is connected in the forward direction, the anode of the thyristor 9 is turned on in excess of the element voltage in the forward direction, whereby the overvoltage flows into the power source voltage Vcc and the ground voltage Vss, and is blocked from flowing into the succeeding stages or flows in a decreased amount. The clamping MOS transistor Q6 is turned on when the overvoltage of the positive polarity leaks even by a small amount, and permits the overvoltage to flow into the power source voltage Vcc.
On the other hand, when an overvoltage of a negative polarity is applied to the connection terminal 3 due to electrostatic discharge, the diode 8 is connected in the forward direction and the clamping MOS transistor Q5 is turned on, whereby the overvoltage flows into the ground voltage Vss, and is blocked from flowing into the succeeding stages or flows in a decreased amount. The clamping MOS transistor Q7 is turned on when the overvoltage of the negative polarity leaks even by a small amount, and permits the overvoltage to flow into the ground voltage Vss.
The varistor 11 is a circuit element which assumes the overvoltage element operation before the overvoltage element operation of the input protection circuit 6 reaches its limit, and reinforces the function for preventing electrostatic damage or reinforces the overvoltage protection function. The varistor 11 is equivalent to a circuit in which the Zener diodes are connected back to back, or can be replaced thereby.
Here, the varistor 11 is a laminated chip varistor using semiconductor ceramics. Referring to an axial sectional view of FIG. 2, the varistor 11 has the shape of a small chip that can be surface-mounted, has electrically conducting side electrodes 20 and 21 at both ends, the one side electrode 20 being provided with a pair of interlayer electrodes 22 and 23 extending toward the other side electrode 21, the other side electrode 21 being provided with another interlayer electrode 24 located between the pair of interlayer electrodes 22 and 23, and extending toward the one side electrode 20, and the gaps among the side electrodes 20, 21 and the interlayer electrodes 22, 23, 24 being filled with semiconductor ceramics 25.
FIG. 3 illustrates characteristics of the varistor 11. The varistor 11 is a variable resistor element having current-voltage (I-V) characteristics as shown in FIG. 3, operates on a leakage current of not larger than 50 μA in a state where it is normally used, and does not affect the input of signals through the connection terminal 3 in a state where the device is practically used. This state is obtained by using the device at a voltage which is not higher than a rated voltage (also called use voltage) Vwm specific to the varistor as described in a data sheet thereof. When an abnormally high voltage enters into the semiconductor integrated circuit chip, the input protection circuit in the semiconductor integrated circuit chip starts working at a relatively low voltage. However, the current tolerating ability of the overvoltage protection element such as diode in the input protection circuit becomes no longer sufficient for the overvoltage, and the current saturates. Accordingly, the operation current starts flowing into the varistor 11. Then, as the overvoltage reaches near the breakdown voltage (Vb), the resistance so decreases that the voltage becomes almost constant irrespective of the current. For larger transient voltage, the varistor prevents the electrostatic damage to the semiconductor integrated circuit chip owing to its high energy allowance value with the clamp voltage (Vc) as a theoretical upper limit.
Let it now be presumed a case where a voltage of 10 kilovolts which is far greater than an electrostatic breakdown voltage of several hundred volts to 2 kilovolts of the semiconductor integrated circuit chip, is applied at a current of 1000 A for 10 nanoseconds (10 nS) to the IC card to which a varistor 11 having an energy withstand level of 0.2 J (Joule) is attached. In this case, the amount of energy is 10 kV×1000 A×10 nS=0.1 J. This amount of energy is smaller than the above energy withstand level of the varistor 11, and the electrostatic damage is prevented.
In FIG. 3, the clamp voltage Vc can be specified to be a prescriptive pulse current, i.e., as a terminal voltage (voltage across the side electrodes) of when a current of 1 A is supplied for 8.20 seconds, and the breakdown voltage Vb can be specified to be a terminal voltage of when, for example, a current of 1 mA is supplied. If described qualitatively, the breakdown voltage Vb can be defined as a voltage which easily enables the I-V characteristics to be reversed even when a direct current is applied within the range. The clamp voltage can be defined to be a voltage that is very likely to lead to the breakage when it is exceeded several times.
The characteristics of the varistor 11 can be specified to be as described below by taking into consideration the characteristics of the overvoltage protection element of the input protection circuit 6.
First, the varistor 11 can be specified to be a variable resistance element having an current tolerating ability in excess of that of the diodes 7, 8, thyristor 9 and clamping MOS transistor Q5 in the input protection circuit 6, or in excess of that of the clamping MOS transistors Q6 and Q7.
Second, a voltage such as a breakdown voltage Vb or a voltage close thereto larger than a rated voltage applied to the varistor 11 for flowing a specified pulse current, is the voltage that enables the diodes 7, 8, thyristor 9, clamping MOS transistor Q5 in the input protection circuit 6, and the clamping MOS transistors Q6 and Q7 to flow only a current smaller than the above specified pulse current, if they are not broken.
Third, the varistor 11 is a variable resistance element having a breakdown voltage larger than those of the diodes 7, 8, thyristor 9 and clamping MOS transistor Q5 in the input protection circuit 6, and than those of the clamping MOS transistors Q6 and Q7.
Fourth, the varistor 11 is a variable resistance element having a stray capacity larger than those of the diodes 7, 8, thyristor 9 and clamping MOS transistor Q5 in the input protection circuit 6, and than those of the clamping MOS transistors Q6 and Q7. As will be understood from the structure of FIG. 2, when used for the power source terminal, it is obvious that the semiconductor ceramics has a relatively large capacitive component though it is not a dielectric. Thus, the stray capacity works to relax the change in the transient voltage, and is effective for preventing the electrostatic damage when the stray capacity is large. When used for signal terminals, the capacity must be decreased to lie within a permissible range so as to respond to high-speed signals.
Fifth, the breakdown voltage of the varistor 11 is smaller than the breakdown voltages of the diodes 7, 8, thyristor 9 and clamping MOS transistor Q5 in the input protection circuit 6, and than those of the clamping MOS transistors Q6 and Q7. The varistor 11 breaks down before the input protection circuit 6 is damaged to let the overvoltage be released.
Sixth, the breakdown voltage of the varistor 11 is smaller than the breakdown voltages of the diodes 7, 8, thyristor 9 and clamping MOS transistor Q5 in the input protection circuit 6, and than that of a circuit protected by the clamping MOS transistors Q6 and Q7, such as of a CMOS inverter circuit constituted by MOS transistors Q1 and Q2.
As described above, the varistor 11 has been selected by taking into consideration the relationship between the characteristics and the ability of the overvoltage protection elements such as diodes 7, 8 constituting the input protection circuit 6 contained in the semiconductor integrated circuit chip 2. Accordingly, the varistor 11 efficiently exhibits the effect for preventing the electrostatic damage.
The signal propagation distance from the connection terminal 3 to the varistor 11 is shorter than the signal propagation distance of from the connection terminal 3 to a corresponding external terminal 4 of the semiconductor integrated circuit chip 2. This makes it possible to prevent the semiconductor integrated circuit chip 2 from directly receiving destructive effect due to an overvoltage before the varistor 11 functions in response to the overvoltage.
The varistor 11 is of the source-mounting type comprising chiefly semiconductor ceramics. Therefore, the mounting area or the occupation area of the varistor 11 can be decreased. The surface mounting helps decrease the cost of producing the IC card.
<Application to a Multi-media Card>
Described below is an embodiment in which the IC card using the varistor 11 is applied to a multi-media card.
FIG. 4 is a diagram illustrating the connection of the varistors to the connection terminals of the multi-media card. According to the specifications by the Group of Standardization, the multi-media card has a size measuring 24 mm×32 mm×1.4 mm. The card substrate 1 has connection terminals, i.e., a connection terminal 3 a for receiving a chip select signal CS, a connection terminal 3 b for receiving a command CMD, a connection terminal 3 c for receiving a clock signal CLK, a connection terminal 3 d for inputting and outputting data DAT, a connection terminal 3 e served with a power source voltage Vcc, and two connection terminals 3 f and 3 g served with ground voltage Vss. The connection terminals 3 a to 3 g are connected to the controller chip and to the nonvolatile memory chips that are not shown but that are mounted on a region designated at 30 in the drawing. In FIG. 4, the arrangement of the connection terminals 3 a to 3 g is different from that of the practical multi-media card.
Varistors 11 a to 11 e are mounted on the card substrate 1 among the connection terminals 3 a to 3 e and between the connection terminals 3 e and 3 g. In FIG. 4, the varistor is provided in a number of one for each corresponding terminal. The varistors, however, may be provided in a plural number being connected in series.
In particular, the varistor lie disposed for the connection terminal 3 e that receives the power source voltage Vcc, works as a by-pass capacitor. Therefore, the varistor 11 e may be replaced by a by-pass capacitor, or a by-pass capacitor 31 may be arranged in parallel as shown in FIG. 4.
FIG. 5 illustrates on a plane the constitution of the multi-media card mounting chiefly the circuit elements, and FIG. 6 is a vertical sectional view thereof. The card substrate 1 is constituted by a glass epoxy resin, and has, on the back surface thereof, the connection terminals 3 a to 3 g formed as electrically conducting patterns. On the surface of the card substrate 1 are mounted the varistors 11 a to 11 e, a controller chip 33 and nonvolatile memory chips 34 a, 34 b via wiring patterns and electrically conducting patterns. In FIG. 5, reference numeral 36 denotes electrically conducting patterns connected to the corresponding connection terminals 3 a to 3 g via the through holes 40, and reference numeral 35 denotes a wiring pattern for connecting the ends of the varistors 11 a to 11 e to the ground voltage Vss. The varistors 11 a to 11 e are surface-mounted spanning across the wiring pattern 35 and the connection terminals 3 a to 3 e.
In FIG. 5, reference numerals 38 and 39 denote bonding patterns, and 37 denotes wiring patterns connecting the bonding patterns 38 to the electrically conducting patterns 36. The electrically conducting patterns 38 are connected to the corresponding external terminals 50 of the controller chip 33 through bonding wires 41, and the external terminals 51 of the controller chip 33 are connected to the corresponding bonding patterns 39 through bonding wires 42. The bonding patterns 39 are connected to the corresponding external terminals 52 a of one nonvolatile memory chip 34 a by bonding wires 43 a, and the bonding patterns 39 are connected to the corresponding external terminals 52 b of the other nonvolatile memory chip 34 b by bonding wires 43 b. The semiconductor integrated circuit chip is a so-called bear chip, and the external terminals 50, 51, 52 a and 52 b are the bonding pads formed of aluminum, aluminum alloy, copper or the like.
The nonvolatile memory chips 34 a and 34 b are, for example, electrically rewritable flush memory chips. The flush memory chip has a memory cell array in which are arranged, like a matrix, nonvolatile memory cell transistors having a control gate, a floating gate, a source and a drain, and executes such operations as reading the data, erasing the data, writing the data and verifying the data according to commands and addresses fed from an external unit. The nonvolatile memory chips 34 a and 34 b comprising the flush memory chips have external terminals 52 a and 52 b, which are terminals for receiving a chip enable signal (also called chip selection signal) /CE for instructing the selection of chip, terminals for receiving a write enable signal /WE for instructing the writing operation, input/output terminals I/O0 to I/O7, terminals for receiving a command/data enable signal /CDE for instructing whether the input/output terminals I/O0 to I/O7 be used for inputting/outputting the command/data or for receiving the address, terminals for receiving an output enable signal /OE for instructing the output operation, terminals for receiving a clock signal /SC for instructing the data latch timing, a terminal for outputting a ready/busy signal R/B for instructing to an external unit whether the writing operation is being executed, and terminals for receiving a reset signal /RES.
The controller chip 33 has a privacy protection function which controls the reading/writing operation for the nonvolatile memory chips 34 a, 34 b according to an instruction from an external unit, executes the encryption for the data to be written into the nonvolatile memory chips 34 a, 34 b by taking into consideration the data security or the copyright protection, and executes the decryption for the data read out from the nonvolatile memory chips 34 a and 34 b.
The external terminals 50 of the controller chip 33 are corresponded to the input/output functions of the connection terminals 3 a to 3 g, and include a terminal for receiving a select signal CS for instructing the selection operation of the multi-media card, a terminal for serially receiving the command CMD for instructing the operation of the multi-media card, a terminal for receiving a clock signal CLK that is regarded to be in synchronism with the signal input/output operation of the external terminal 50, a terminal for serially inputting/outputting the data DAT, and a terminal for receiving a power source voltage Vcc and ground voltage Vss. In the controller chip 33 are integrated the input protection circuit 6 and clamping MOS transistors Q6 and Q7 that are described with reference to FIG. 1 concerning the input terminals that are among the external terminals 50.
The controller chip 33 has external terminals 51 for making access to the memories, i.e., a terminal for sending a chip selection signal /CEO to the nonvolatile memory chip 34 a, a terminal for sending a chip selection signal /CE1 to the nonvolatile memory chip 34 b, and external terminals corresponding to the external terminals of the nonvolatile memory chips 34 a and 34 b but having an input/output direction opposite thereto.
<Connection of the Bonding Wires>
As described above, bonding wires 41 are used for connecting the connection terminals 3 a to 3 g to the external terminals 50 of the controller chip 33, and bonding wires 43 a and 43 b are used for connecting the controller chip 33 to the nonvolatile memory chips 34 a, 34 b. This eliminates the need of forming a number of wiring patterns having the same function as the connection by the above bonding wires in a concentrated manner on the card substrate 1. Space on the controller chip 33 and on the nonvolatile memory chips 34 a, 34 b can be utilized for the wiring. In effect, the aerial wiring of the bonding wires makes it possible to simplify the wiring on the substrate. Therefore, this contributes to decreasing the cost of the card substrate 1.
<Stacked Mounting in a Deviated Manner>
In the constitution of FIG. 2, the two nonvolatile memory chips 34 a and 34 b are connected using the bonding wires in parallel with the controller chip 33. Here, the nonvolatile memory chips 34 a and 34 b are mounted on the card substrate 1 in a state of being stacked one upon the other with their positions being so deviated that the external terminals 52 a, 52 b are exposed. Therefore, the distances to the controller chip 33 can be shortened compared to when the nonvolatile memory chips 34 a, 34 b are arranged without being stacked, and the lengths of the bonding wires 43 a, 43 b can be shortened. This decreases undesired contact or breakage of the bonding wires. When plural nonvolatile memory chips are stacked, the amount of deviation may be determined within such a range that a chip of the lower layer exits under the external terminals for bonding of the chip of the upper layer. When the chip of the lower layer is not existing under the external terminals for bonding, the chip is likely to be damaged due to mechanical force at the time of bonding.
At this moment, in particular, a condition is satisfied in that the area on one surface of the card substrate 1 is larger than the total areas of the nonvolatile memory chips 34 a, 34 b and the controller chip 33. This is a contrivance for providing the card substrate 1 with an extra space to cope with such a restrictive condition that the wiring layer is formed on one surface only of the card substrate. This is different from a simple idea of mounting the nonvolatile memory chips in a stacked manner to decrease the area of the card substrate 1.
<Column-like Layout>
In the example of FIG. 5, the nonvolatile memory chips 34 a, 34 b and the controller chip 33 are mounted on the card substrate 1 being arranged like columns. That is, the distance from the connection terminals 3 a to 3 g of the multi-media card is increased in order of the varistors 11 a to 11 e, the controller chip 33 and the plural memory chips 34 a, 34 b, and they are arranged like columns from one side of the card substrate 1 toward the opposing side thereof. Owing to this column-like arrangement, the second varistors 11 a to 11 e for finally releasing the overvoltage are closest to the connection terminals 3 a to 3 g to which the overvoltage will be applied, and the nonvolatile memory chips 34 a, 34 b storing the data are the remotest, producing the effect for absorbing the surge of high-speed pulses. Therefore, a high reliability is obtained in regard to reinforcing the prevention of electrostatic damage to the controller chip 33 owing to the varistors 11 a to 11 e, and to protecting the data stored in the nonvolatile memory chips 34 a and 34 b.
<Deviation of Through Holes from the Connection Terminals>
As shown in FIG. 5, the through holes 40 are formed at deviated positions in the connection terminals 3 a to 3 g. That is, as shown in detail in FIG. 7(A), the through hole 40 is formed in the connection terminal 3 a exposed from the IC card at a position deviated from the slide surface of the connection terminal 3 a. The position of deviation may be as shown in FIG. 7(B). Then, even when the IC card is attached to, or detached from, the mounting slot, the terminal 40A of the slot does not come into slide contact with the through hole 40 and does not exert a mechanical force to the through hole 40. This prevents a probability in that the pattern of the connection terminal 3 a is cracked starting from the through hole 40, or the periphery of the through hole is worn out causing a damage thereto.
<Formation of Through Holes Outside the Molding Region>
Referring to FIG. 6, the controller chip 33 and the nonvolatile memory chips 34 a, 34 b as a whole are molded with a thermosetting resin 55. The varistor element may be provided inside the mold or outside the mold. Here, no through hole 40 is included in the region molded with the thermosetting resin 55. This precludes such a probability that the molding resin 55 flows to the back side of the card substrate 1 through the holes 40 to cause defective molding when the molding is effected with the application of pressure.
<Metal Cap>
In FIG. 6, a metal cap 56 is covering the surface of the card substrate 1 on where there are mounted varistors 11 a to 11 e, controller chip 33 and nonvolatile memory chips 34 a, 34 b outside the mold. This provides a countermeasure against EMI (electro magnetic interference) as compared with the resin cap, accomplishing the sealing by mechanical fastening or the sealing of cap at a high temperature.
FIG. 25 illustrates several kinds of structures of the metal caps 56. FIG. 25(A) illustrates a metal cap formed by forging piece by piece in an isolated manner and having a small step for sticking a label, FIG. 25(B) illustrates a metal cap formed by forging followed by blanking piece by piece in an isolated manner, and FIG. 25(C) illustrates a metal cap formed by reducing a metal plate. FIG. 25(D) is a perspective view of when the metal cap obtained by reducing the metal plate of FIG. 25(C) is viewed from the back side. Corner portions have been cut way in advance to avoid wrinkles at the time of reduction.
<Stitch Bonding>
FIG. 8 illustrates a portion of the multi-media card in which the nonvolatile memory chips are connected by stitch bonding. FIG. 9 is a vertical sectional view illustrating the stitch-bonded portions. Like in FIG. 5, the nonvolatile memory chips 34 a and 34 b are mounted on the card substrate 1 in a manner of being stacked in a plural number but with their positions being so deviated that their external terminals 52 a, 52 b are exposed. Here, the external terminals 52 a, 52 b of the nonvolatile memory chips that receive the same signals from the controller chip 33 are successively connected in series with the bonding wires 57. Thus, there is employed a bonding method like a so-called stitch-sewing, i.e., a stitch-bonding method. The bonding wires can be shortened as a whole compared to the case of connecting the controller chip 33 to the external terminals 52 a, 52 b using separate bonding wires 43 a, 43 b as is done in FIG. 5. Besides, the number of the bonding wires can be decreased in the region of bonding patterns. In this respect, too, it is allowed to decrease the probability of undesired contact or breakage of the contact wires that occurs when they are arranged too densely. The nonvolatile memory chips 34 a, 34 b must be selected separately. The stitch-bonding cannot be employed for the bonding wires 43 a, 43 b for transmitting the chip selection signals /CE0, /CE1; i.e., the wires 43 a, 43 b are bonded in the same manner as in FIG. 5.
When the stitch-bonding is employed, the method of bonding the bonding pads 52 a may differ depending upon the form of bonding by a wire bonder that is used. FIG. 10(A) illustrates the case of when the nail head bonding is utilized. In this case, due to the structure of the wire bonder, the end of the bonding wire is torn away like a crescent. Therefore, the next bonding point must be another place from the end point. Namely, the stitch bonding is completed with bonding wires 57, 57 that are inevitably cut into plural pieces. FIG. 10(B), on the other hand, illustrates a case of utilizing the wedge bonding. By using a wire bonder which supports this method, the bonding can be successively effected to the subsequent positions without cutting the bonding wire. According to this system, therefore, the stitch-bonding can be effected by using a single bonding wire 57.
FIG. 11 illustrates on a plane the constitution of the multi-media card having a structure in which four pieces of nonvolatile memory chips are stacked. FIG. 12 is a vertical sectional view thereof. The four pieces of nonvolatile memory chips 34 a to 34 d are mounted on the card substrate 1 being stacked with their positions being so deviated that the external terminals 52 a to 52 d are exposed. Here, the external terminals 52 a to 52 d of the nonvolatile memory chips 34 a to 34 d that receive the same signals from the controller chip 33 are successively connected in series using the bonding wires 60 like the stitch-bonding. The nonvolatile memory chips 34 a to 34 d must be separately selected. Therefore, the stitch-bonding is not employed-for the bonding wires 43 a to 43 d for transmitting the chip selection signals /CE0 to /CE3; i.e., the wires 43 a to 43 d are bonded in the same manner as in FIG. 5. However, the stitch-bonding can be effected if the chip selection signal is generated in the form of an ID command.
<Shielding Pattern>
The constitution of FIG. 11 employs an electrically conducting shielding pattern 61 shown in FIG. 12 for the card substrate 1 in order to further relax the effect of electrostatic discharge taking place near the card substrate. That is, the wide electrically conducting shielding pattern 61 is formed on the exposed surfaces of the connection terminals 3 a to 3 g of the card substrate 1. Though there is no particular limitation, the electrically conducting shielding pattern 61 may be connected to the connection terminals 3 f, 3 g for supplying ground power source Vss, or may be floated since it has a relatively large surface area. The electrically conducting shielding pattern 61 disperses the static electricity.
<CS Input Terminal at an End of the Chip>
In the structure in which the plural nonvolatile memory chips 34 a to 34 d are stacked being deviated as shown in FIG. 11, the terminals for receiving the chip selection signals CE0 to /CE3 among the external terminals 52 a to 52 d of the nonvolatile memory chips 34 a to 34 d, are located at the ends of the arrangements of the external terminals, and are separately connected to the external terminals 51 of the controller chip 33 through the bonding wires 43 a to 43 d. Quite the same holds even for the stacked structure of FIG. 8. In the constitution in which the plural nonvolatile memory chips are separately selected as shown in FIGS. 8 and 11, the terminals for receiving the chip selection signal among the external terminals of the nonvolatile memory chips must be separately connected to the external terminals 51 for producing a chip selection signal of the controller chip 33. Even if the stitch-bonding method cannot be adapted to these portions, therefore, a necessary connection can be accomplished without hindered by other bonding wires since the external terminals for receiving he chip selection signal have been disposed at the ends of the nonvolatile memory chips. The effect appears conspicuously as the number of the nonvolatile memory chips that are stacked increases. When two pieces of nonvolatile memory chips are stacked as shown in FIG. 5, two bonding wires can be easily drawn in parallel from a single bonding pattern by using a wire bonder having a high degree of precision. In this case, too, no inconvenience occurs even when the external terminal for receiving the chip selection signal is disposed at an end of the chip though the stitch-bonding is not employed.
<Mounting the Stacked Nonvolatile Memory Chips in Plural Groups>
FIG. 13 is a view illustrating another example of the multi-media card, and FIG. 14 is a vertical sectional view illustrating a portion thereof. In the multi-media card shown in FIG. 13, two sets of nonvolatile memory chips are mounted on the card substrate 1, each set comprising two pieces of nonvolatile memory chips that are stacked, and a single-phase wiring is formed on one surface only of the card substrate 1, the single-phase wiring including wiring patterns and bonding patterns together with the connection terminals. This is the so-called COB (chip-on-board) structure mounting a semiconductor bear chip on the substrate.
In FIG. 13, the connection terminals 3 a to 3 g, wiring patterns 35, 37, bonding pattern 38, bonding patterns 39A, 39C, and wiring pattern 39B are all formed on the mounting side of the card substrate 1. The connection terminals 3 a to 3 g and the wiring pattern 35 are exposed on the surface through openings formed in the card substrate 1, enabling the varistors 11 a to 11 e to be connected. Similarly, the bonding patterns 38, 39A and 39C are exposed on the surface through openings formed in the card substrate 1, so as to be bonded to the external terminals 50, 51 of the controller chip 33 and to the external terminals 52 a to 52 d of the nonvolatile memory chips 34 a to 34 d. In FIG. 13, the stitch-bonding is employed to neither the bonding between the bonding pattern 39A and the external terminals 52 a, 52 b of the nonvolatile memory chips 34 a, 34 b nor to the bonding between the bonding pattern 39C and the external terminals 52 c, 52 d of the nonvolatile memory chips 34 c, 34 d. However, the stitch-bonding same as that of FIG. 8 may be employed except for the chip selection signals.
When two sets of the nonvolatile memory chips are mounted on the card substrate 1, each set comprising two pieces of nonvolatile memory chips that are stacked as shown in FIG. 13, the thickness can be decreased compared to when four pieces are stacked as in FIG. 11. Therefore, when two sets of the nonvolatile memory chips are mounted on the card substrate 1, each set comprising four pieces of nonvolatile memory chips that are stacked, then, the storage capacity of two folds as great can be obtained with the same height as that of the four-piece-stacked structure of FIG. 11.
When plural connection terminals 3 a to 3 g are arranged along a side of the card substrate 1, the card controller 33 may be arranged with its lengthwise direction in parallel with the neighboring side and the nonvolatile memory chip may be arranged in a direction nearly at right angles with the direction of arrangement of the connection terminals 3 a to 3 g. Then, the nonvolatile memory chips can be efficiently mounted on the surface of the card substrate 1.
The divisional stacked structure and the structure for arranging the connection terminals 3 a to 3 g and the controller chip 33 along the two sides of the card substrate 1, make it easy to mount the nonvolatile memory chips on the card substrate of a specified size maintaining an increased density or to mount the nonvolatile memory chips in a increased number.
FIG. 15 illustrates a further multi-media card employing the above divisional stacked structure and a structure in which the connection terminals and the controller chip are arranged along the two neighboring sides of the card substrate. This example is different from that of FIG. 13 in regard to that the connection terminals, wiring patterns and bonding patterns are formed on both surfaces of the card substrate 1 and that the directions of the stacked nonvolatile memory chips are oriented.
In FIG. 15, the connection terminals 3 a to 3 g and the wiring patterns 39B are formed on the back surface of the card substrate, and the wiring patterns 35, 37, bonding pattern 38, and bonding patterns 39A, 39C are formed on the surface of the card substrate 1. Through holes 40A are used for connecting the wiring pattern 39B to the bonding patterns 39A, 39C. Like in FIG. 13, FIG. 15 does not employ the stitch bonding, either. However, the stitch bonding like that of FIG. 8 may be employed except for the chip selection signals.
Like that of FIG. 13, the divisional stacked structure and the structure for arranging the connection terminals 3 a to 3 g and the controller chip 33 along the two sides of the card substrate 1 in the multi-media card of FIG. 15, make it easy to mount the nonvolatile memory chips on the card substrate of a specified size maintaining an increased density or to mount the nonvolatile memory chips in an increased number.
Here, the through holes in the mold may be filled with an electrically conducting paste or a solder resist to prevent the leakage of the molding resin.
<Structure for Stacking the Memory Chips and the Controller Chip>
FIGS. 16 and 17 illustrate examples in which the controller chip is mounted and stacked on the memory chip. In FIG. 16, the external terminals 51 of the controller chip 33 are connected to the external terminals 52 of the nonvolatile memory chip 34 based on the direct interchip bonding by using the bonding wires 70. In order to decrease the resistance for feeding the operation power sources Vss, Vcc to the nonvolatile memory chip 34, however, power source wiring patterns 71A, 72A are formed on the back surface of the card substrate 1, and the bonding patterns 71B, 72B connected through the holes 71D, 72D are connected to the nonvolatile memory chip 34 through the bonding wires 71C, 72C. When the resistance for feeding the power to the nonvolatile memory chip 34 is very small, however, the power sources Vcc, Vss may be fed through the terminals 51 and 52. The structure for mounting the varistors 11 a to 11 e is the same as the one described above, and the circuit elements having the same functions as those of FIG. 15 are denoted by the same reference numerals but their description is not repeated.
FIG. 17 illustrates a structure in which the memory chip and the controller chip are stacked by utilizing an LOC (lead-on-chip). Reference numerals 73 a to 73 g denote some of the leads of a lead frame for the LOC. The leads 73 e and 73 f for the power sources Vcc, Vss are extending like hooks and are forming path bars 74A and 74B. The nonvolatile memory chip 34 is secured to the path bars 74A, 74B, and the controller chip 33 is secured to the nonvolatile memory chip 34. The external terminals 50 of the controller chip 33 are connected to the leads 73 a to 73 g through the bonding wires 4. Further, the external terminals 51 of the controller chip 33 are connected to the external terminals 52 of the nonvolatile memory chip 34 by the direct interchip bonding method using the bonding wires 70. In order to decrease the resistance for feeding the operation power sources Vss, Vcc to the nonvolatile memory chip 34, however, the path bars 74A and 74B are connected to the nonvolatile memory chip 34 through the bonding wires 75, 75. The varistors 11 a to 11 e are surface-mounted on the corresponding leads using an electrically conducting paste such as Ag paste.
FIG. 18 illustrates a still further IC card employing the COB structure. FIG. 19 is a vertical sectional view of the IC card, and FIG. 20 is a view illustrating the electrically conducting pattern formed on the bottom surface of the card substrate of the IC card of FIG. 18. Electrically conducting patterns 80 a to 80 g are formed on the bottom surface of the card substrate 84, and openings 81 a to 81 g are formed in the card substrate 84 being corresponded thereto. The electrically conducting patterns 80 a to 80 f constitute connection terminals exposed from the IC card. The semiconductor integrated circuit chip 83 is connected to the electrically conducting pattern 80 f via the opening 81 g and is served with ground voltage Vss as a substrate potential. Bonding pads 85 a to 85 f constituting the external terminals of the semiconductor integrated circuit chip 83 are connected to the connection electrodes 80 a to 80 f using the bonding wires 86 through the openings 81 a to 81 f. Then, varistors 82 a to 82 e comprising chiefly semiconductor ceramics are surface-mounted across the connection terminals 80 a to 80 g and the electrically conducting patterns 80 g through the openings 81 a to 81 g using an electrically conducting paste such as Ag paste in order to reinforce the prevention of electrostatic damage to the semiconductor integrated circuit chip 83 in the same manner as described above.
<Notice>
FIG. 21 illustrates an IC card having a notice for preventing the electrostatic damage. An IC card such as the multi-media card mounting the semiconductor integrated circuit chip with plural connection terminals being exposed, is provided on its surface with a notice 90, such as “DON'T TOUCH THE CONNECTION TERMINALS” as shown in FIG. 21(A) so that the user will not touch the connection terminals 3 a to 3 g. On this region may further be written a production management code. As shown in FIG. 21(B), further, an indication is provided to clearly indicate the position for holding the IC card by fingers, such as notice indication 91 in the form of a finger printed on a position where the IC card should be held by fingers at the time of attachment or detachment. As shown in FIG. 21(B), further, a packing material 92 such as a laminated film, a paper box or a plastic casing packing the IC card may be provided with a notice 93 warning not to touch the-connection terminals 3 a to 3 g of the IC card.
The notices 90, 93 and indication 91 are helpful for preventing the IC card from being electrostatically damaged due to unexpected handling by a person who is not familiar with the IC card.
<How to Fabricate the IC Card>
FIG. 22 illustrates a method of fabricating the IC card shown in FIGS. 4 and 5. First, varistors are mounted on the predetermined electrically conducting patterns of the card substrate such as a PCB substrate or a tape substrate (S1). In practice, a solder paste or a silver paste is used. Thereafter, the paste is cured (baked) (S2), and a required number of the semiconductor integrated circuit chips are die-bonded to the electrically conducting pattern on the card substrate (S3). Then, the surface of the card substrate is cleaned with a plasma (S4). Then, the bonding pads of the semiconductor integrated circuit chips that are die-bonded are bonded to the electrically conducting pattern by thermal ultrasonic method using gold bonding wires (S5). The semiconductor integrated circuit chips and the bonding wires are then sealed by potting the resin (S6) which is then cured by baking (S7). Finally, a metal cap is secured onto the card substrate by adhesion or by plastic insert molding.
As described above, the varistors are first mounted on the card substrate and, then, the semiconductor integrated circuit chips are die-bonded or wire-bonded. Therefore, the protection by the varistors is accomplished at the time of assembling the IC card, contributing to improving the yield of the IC card. The varistors, however, may be mounted afterwards depending upon the convenience in the production, such as temperature conditions, etc.
<Data Recovery Terminals>
FIG. 23 illustrates an IC card giving attention to recovering the data. The basic constitution is the same as FIG. 5, and the difference is the possession of plural data recovery terminals. In FIG. 23, the connection between the control latch 33 and the nonvolatile memory chips 34 a, 34 b is simplified in order to emphasize the connection to the data recovery terminals. In FIG. 23, the circuit elements having the same functions as those of FIG. 5 are denoted by the same reference numerals, but their detailed description is not repeated.
Though not diagramed in FIG. 5, the controller latch 33 has an input terminal (also simply written as test terminal /TEST) for receiving a test signal /TEST pulled up in the circuit as one of the external terminals 51. When a low level is input, the test terminal /TEST controls the interface terminal to the nonvolatile memory chips 34 a, 34 b and, controls, particularly, the output terminal and the input/output terminal to assume a state of a high output impedance or to assume a state in which the input/output operation cannot be executed.
On the card substrate 1 are formed data recovery terminals 92 that are connected to all external terminals 51 of the controller chip 33 on the side of the memory interface in a one-to-one manner through wirings 91. There are further provided a ground terminal 96 for recovering the data that is connected, through a wire 95, to an external terminal for the ground power source Vss among the external terminals 50 of the controller chip 33 on the side of the cathode interface, and a power source terminal 94 for recovering the data that is connected, through a wire 93, to an external terminal for the power source voltage Vcc among the external terminals 50 of the controller chip 33 on the side of the card interface. In FIG. 23, reference numeral 90 denotes a guard ring added to the card substrate 1 for preventing the electrostatic damage. The guard ring 90 surrounds the card substrate 1 and is connected to the ground power source terminal of the circuit.
The data evaluation terminals 92, 94 and 96 have been formed on the card substrate 1. When the memory control operation cannot be executed for the controller chip 33 due to the electrostatic damage, therefore, access can be made directly to the nonvolatile memory chips 34 a, 34 b from an external unit through the data evaluation terminals 92, 94 and 96. Therefore, even when the controller chip 33 is damaged, the data that are remaining in the nonvolatile memory chips 34 a, 34 b can be easily recovered.
The controller chip 33 may have a privacy protection function that executes the encryption for the data to be written into the nonvolatile memory and executes the decryption for the data read out from the nonvolatile memory. In this case, the data are recovered by the manufacturer of the IC card or by an authorized person by decrypting the data read out from the nonvolatile memory chips.
<Method of Recovering the Data>
FIG. 24 illustrates a procedure of a data recovery processing for the IC card equipped with the data evaluation terminals.
The data are recovered from a multi-media card (MMC) of which the controller became defective due to electrostatic damage that could not be prevented by the input protection circuit or the varistors (S10). The data can further be recovered from those multi-media cards (MMC) of which the connection terminals were physically damaged. First, the cap 56 is removed from the object MMC (S11), and a probe such as a tester is brought into contact with the data evaluation terminals 92, 94, 96 (S12). Then, the terminal for receiving the test signal /TEST is fixed to the low level, and the memory interface terminal of the controller chip 33 is controlled to assume a high impedance state (state in which the input/output operation cannot be executed) (S13). Thus, the nonvolatile memory chip contained in the MMC is released from the control operation by the controller chip, and becomes accessible directly through the data evaluation terminals 92, 94, 96. In this state, the data are read out from the nonvolatile memory chip (S14). Here, the controller chip 33 has the privacy protection function that executes the encryption for the data that are written into the nonvolatile memory chip and executes the decryption for the data read out from the nonvolatile memory. Therefore, the data that are read out are decrypted without passing through the controller chip 33. The thus decrypted data are written into a new MMC in an ordinary manner through the connection terminals 3 a to 3 g (S15). Thus, the new MMC having the recovered data is offered to the user (S16). Here, the specifications of encryption of the controller chip can be confirmed by a production trace code of the card or by a production code written in the nonvolatile memory.
Thus, even in case the input circuit of the controller chip 33 is electrostatically damaged, the data that remain safe in the nonvolatile memory chips 34 a, 34 b can be easily recovered.
<Flush Memory Chip>
Here, the flush memory chip will be described. FIG. 26 illustrates a flush memory chip. In FIG. 26, reference numeral 103 denotes a memory array which includes a memory mat, a data latch circuit and a sense latch circuit. The memory mat 103 has many electrically erasable and writable nonvolatile memory cell transistors. As shown in FIG. 27, the memory cell transistor is constituted by a source S and a drain D formed in the semiconductor substrate or in a memory well SUB, a floating gate FG formed in the channel region via a tunnel oxide film, and a control gate CG overlapped on the floating gate via an interlayer-insulating film. The control gate CG is connected to a word line 106, the drain D is connected to a bit line 105, and the source S is connected to a source line that is not shown.
The external input/output terminals I/O0 to I/O7 are also used as an address input terminal, a data input terminal, a data output terminal and a command input terminal. An X-address signal input through the external input/output terminals I/O0 to I/O7 is fed to an X-address buffer 108 through a multiplexer 107. An X-address decoder 109 decodes internal complementary address signals output from the X-address buffer 108 to drive the word line.
A sense latch circuit that is not shown is provided on one end side of the bit line 105, and a data latch circuit that is not shown is provided on the other side thereof. The bit line 105 is selected by a Y-gate array circuit 113 based on a selection signal output from a Y-address decoder 111. A Y-address signal input through the external input/output terminals I/O0 to I/O7 is preset to a Y-address counter 112, and an address signal which gradually increases starting from the preset value is given to the Y-address decoder 111.
When the data is being output, the bit line selected by the Y-gate array circuit 113 is rendered conductive to the input terminal of the output buffer 15. When the data is being input, the bit line selected by the Y-gate array circuit 113 is rendered conductive to the output terminal of the input buffer 117 through a data control circuit 116. The connection among the output buffer 115, input buffer 117 and the input/output terminals I/O0 to I/O7, is controlled by the multiplexer 107. A command fed through the input/output terminals I/O0 to I/O7 is given to a mode control circuit 118 via the multiplexer 107 and the input buffer 117. In addition to feeding the data through the input/output terminals I/O0 to I/O7, the data control circuit 116 feeds data of a logical value controlled by the mode control circuit 118 to the memory array 103.
A control signal buffer circuit 119 receives, as access control signals, the chip enable signal /CE, an output enable signal /OE, a write enable signal /WE, and a signal /SC for instructing the data latch timing, as well as a reset signal /RES and a command/data enable signal /CDE. The mode control circuit 118 controls a signal interface function to the external unit depending on the state of the signals, and further controls the internal operation according to a command code. When a command or a data is input to the input/output terminal I/O0 to I/O7, the signal /CDE is asserted. When it is a command, a signal /WE is asserted and when it is a data, the signal /WE is negated. When an address is input, the signal /CDE is negated and the signal /WE is asserted. Accordingly, the mode control circuit 118 distinguishes the command, data and address that are input in a multiplex manner through the external input/output terminals I/O0 to I/O7. The mode control circuit 118 asserts a ready/busy signal R/B during the erasing or writing operation, and informs an external unit of the state thereof.
An internal power source circuit 120 forms various operation sources 121 for writing, erasing, verifying and reading, and feeds them to the X-address decoder 109 and to the memory cell array 103.
The mode control circuit 118 controls the flush memory as a whole according to the command. The operation of the flush memory is basically determined by the command. The command assigned to the flush memory is read out, erased or written.
The flush memory has a status register 122 for indicating the internal state, and its content can be read out through the input/output terminal I/O0 to I/O7 by asserting the signal /OE.
In the foregoing were concretely described the invention accomplished by the present inventors by way of an embodiment. It should, however, be noted that the invention is in no way limited thereto only but can be modified in a variety of ways without departing the spirit and scope of the invention.
For example, the present invention can be applied to the memory cards other than the multi-media card, such as a compact flush memory and the like. Further, the structure in which the memory chips are stacked in a deviated manner, the structure in which the through holes are deviated from the connection terminals of the IC card, the structure in which the through holes are formed outside the molding region, the structure for stitch-bonding the stacked semiconductor integrated circuit chips and arranging the CS input terminals at the end of the chips, the IC card in which the stacked nonvolatile memories are mounted being divided into plural groups, and the IC card having note and data recovery terminals, are not necessarily limited to those constitutions having varistors. The memory mounted on the IC card of the present invention is not limited to the nonvolatile memory but may be a volatile memory (SRAM, DRAM, etc.). Further, the IC card may be the one mounting both the nonvolatile memory and the volatile memory.
The foregoing description has dealt with the case where the invention accomplished by the present inventors was adapted to a memory card in a field of art that served as the background of the invention. The present invention, however, is in no way limited thereto only, but can be applied to IC cards such as a bankbook, a credit card, an ID card, etc.
Briefly described below are the effects obtained by representative examples of the invention disclosed in this application.
That is, an IC card is provided that is capable of reinforcing the prevention of the electrostatic damage without increasing the cost of the semiconductor integrated circuit chip.
It is allowed to reinforce the prevention of the electrostatic damage by externally attaching the overvoltage protection elements to the semiconductor integrated circuit chip without causing a great change in the size and thickness of the IC card.
It is expected to prevent the electrostatic damage to the IC card due to unexpected handling by a person who is not familiar with.
There is provided an IC card capable of easily recovering the data in the memory card when the data remain safe in the memory even when the input circuit of the semiconductor integrated circuit chip is electrostatically damaged.
It is allowed to avoid the wiring patterns or the bonding wires from being densely concentrated, that could become a cause of malfunction due to undesired leakage of the signal lines even though a vacant region is decreased on the card substrate of the IC card due to the countermeasure against the electrostatic damage by externally attaching circuit elements such as varistors or the like.
It is allowed to realize an IC card having a relatively large storage capacity despite of its relatively small size.

Claims (2)

What is claimed is:
1. A method of recovering data from an IC card in which plural connection terminals are exposed, memory chips and a controller chip for controlling the memory chips are mounted on a card substrate, the connection terminals are connected to a first group of external terminals of the controller chip, the memory chips are connected to a second group of external terminals of the controller chip, and data evaluation terminals connected to the second group of external terminals are formed on the card substrate, the method including:
a first processing for placing the memory chips in a state in which the memory chips cannot be controlled by the controller chip; and
a second processing for reading the data from the data evaluation terminals by controlling the memory chips.
2. A method of recovering data from an IC card in which plural connection terminals are exposed, memory chips and a controller chip for controlling the memory chips are mounted on a card substrate, the controller chip having a privacy protection function that executes the encryption for the data that are written into the memory chips and the decryption for the data read out from the memory chips, and wherein the connection terminals are connected to a first group of external terminals of the controller chip, the memory chips are connected to a second group of external terminals of the controller chip, and data evaluation terminals connected to the second group of external terminals are formed on the card substrate, the method including:
a first processing for controlling the output terminal included in the second group of external terminals of the controller chip so as to assume a state of high output impedance;
a second processing for reading the data from the data evaluation terminals by controlling the memory;
a third processing for decrypting the data read out in the second processing; and
a fourth processing for writing the data decrypted in the third processing into another IC card.
US09/810,509 1999-12-03 2001-03-19 IC card Expired - Lifetime US6431456B2 (en)

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Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030029920A1 (en) * 2001-08-13 2003-02-13 Chhor Khushrav S. Molded memory module and method of making the module absent a substrate support
US20030034552A1 (en) * 2001-04-02 2003-02-20 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20030071296A1 (en) * 2001-10-17 2003-04-17 Peng Jack Zezhong Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric
WO2003034331A1 (en) * 2001-10-17 2003-04-24 Kilopass Technologies, Inc. Smart card having a memory using a ultra-thin dielectric
US20030102569A1 (en) * 2001-08-17 2003-06-05 Edward Reyes Method and apparatus for die stacking
US20030202376A1 (en) * 2002-04-26 2003-10-30 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor
US6641049B2 (en) * 2000-08-31 2003-11-04 Pacusma Company, Ltd. Integrated circuit card with multiple integral electronic modules
US20040000725A1 (en) * 2002-06-19 2004-01-01 Inpaq Technology Co., Ltd. IC substrate with over voltage protection function and method for manufacturing the same
US20040008538A1 (en) * 2001-09-18 2004-01-15 Peng Jack Zezhong Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US20040047218A1 (en) * 2001-09-18 2004-03-11 Kilopass Technologies, Inc. Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US20040084538A1 (en) * 2000-01-25 2004-05-06 Hitachi, Ltd. IC card
US20040125671A1 (en) * 2002-04-26 2004-07-01 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection
US20040135241A1 (en) * 2002-11-18 2004-07-15 Storcard, Inc. Secure transaction card with a large storage volume
US20040156234A1 (en) * 2002-04-26 2004-08-12 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown
US6791891B1 (en) 2003-04-02 2004-09-14 Kilopass Technologies, Inc. Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage
US20040208055A1 (en) * 2002-09-26 2004-10-21 Jianguo Wang Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US20040223370A1 (en) * 2002-09-26 2004-11-11 Jianguo Wang Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US20040223363A1 (en) * 2002-04-26 2004-11-11 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
US20050035783A1 (en) * 2003-08-15 2005-02-17 Man Wang Field programmable gate array
US6903935B1 (en) * 2004-07-16 2005-06-07 Tien-Tzu Chen Memory card with a static electricity conducting board
US20050145690A1 (en) * 2002-08-16 2005-07-07 Fujitsu Limited Transaction terminal device and transaction terminal control method
US20050169040A1 (en) * 2004-02-03 2005-08-04 Peng Jack Z. Combination field programmable gate array allowing dynamic reprogrammability
US20050169039A1 (en) * 2004-02-03 2005-08-04 Peng Jack Z. Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown
US20050218929A1 (en) * 2004-04-02 2005-10-06 Man Wang Field programmable gate array logic cell and its derivatives
US20050259408A1 (en) * 2004-05-21 2005-11-24 Sergio Ramos Self-shielding high voltage distribution box
US20050275428A1 (en) * 2004-06-10 2005-12-15 Guy Schlacter Field programmable gate array logic unit and its cluster
US20050275427A1 (en) * 2004-06-10 2005-12-15 Man Wang Field programmable gate array logic unit and its cluster
US20060062068A1 (en) * 2004-09-20 2006-03-23 Guy Schlacter Field programmable gate arrays using both volatile and nonvolatile memory cell properties and their control
US20060104041A1 (en) * 2002-09-17 2006-05-18 Axalto Sa Hybrid card
US20060233012A1 (en) * 2005-03-30 2006-10-19 Elpida Memory, Inc. Semiconductor storage device having a plurality of stacked memory chips
US20060232296A1 (en) * 2005-04-18 2006-10-19 Kilopass Technologies, Inc. Fast processing path using field programmable gate array logic unit
US20060261489A1 (en) * 2005-05-23 2006-11-23 Yasuo Takemoto Semiconductor memory card and method of fabricating the same
US20070158440A1 (en) * 2006-01-06 2007-07-12 Renesas Technology Corp. Semiconductor device
US20080023562A1 (en) * 1999-12-03 2008-01-31 Hirotaka Nishizawa Ic card
US20080169573A1 (en) * 2007-01-16 2008-07-17 Advanced Semiconductor Engineering, Inc. Circuit substrate and the semiconductor package having the same
US20090180225A1 (en) * 2008-01-10 2009-07-16 Industrial Technology Research Institute Esd protection structure
US20100084762A1 (en) * 2006-04-21 2010-04-08 Hidenobu Nishikawa Memory card
US7719845B1 (en) * 2005-04-26 2010-05-18 Amkor Technology, Inc. Chamfered memory card module and method of making same
US20110159641A1 (en) * 2006-09-21 2011-06-30 Renesas Electronics Corporation Method of manufacturing semiconductor device
US8026574B2 (en) 2004-05-06 2011-09-27 Sidense Corporation Anti-fuse memory cell
US8283751B2 (en) 2004-05-06 2012-10-09 Sidense Corp. Split-channel antifuse array architecture
US8735297B2 (en) 2004-05-06 2014-05-27 Sidense Corporation Reverse optical proximity correction method
US8987053B2 (en) * 2007-12-27 2015-03-24 Sandisk Technologies Inc. Semiconductor package including flip chip controller at bottom of die stack
US9123572B2 (en) 2004-05-06 2015-09-01 Sidense Corporation Anti-fuse memory cell
US11166363B2 (en) * 2019-01-11 2021-11-02 Tactotek Oy Electrical node, method for manufacturing electrical node and multilayer structure comprising electrical node

Families Citing this family (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001672A (en) * 1997-02-25 1999-12-14 Micron Technology, Inc. Method for transfer molding encapsulation of a semiconductor die with attached heat sink
US7872871B2 (en) * 2000-01-06 2011-01-18 Super Talent Electronics, Inc. Molding methods to manufacture single-chip chip-on-board USB device
US7830666B2 (en) * 2000-01-06 2010-11-09 Super Talent Electronics, Inc. Manufacturing process for single-chip MMC/SD flash memory device with molded asymmetric circuit board
US20080185694A1 (en) * 1999-08-04 2008-08-07 Super Talent Electronics, Inc. Processes of Manufacturing Portable Electronic Storage Devices Utilizing Lead Frame Connectors
JP2002124626A (en) * 2000-10-16 2002-04-26 Hitachi Ltd Semiconductor device
KR100348102B1 (en) * 2001-01-17 2002-08-09 삼성전자 주식회사 Method For Detecting Defective Marking On Semiconductor Products By Using Optical Character Recognition Technique
US7352199B2 (en) * 2001-02-20 2008-04-01 Sandisk Corporation Memory card with enhanced testability and methods of making and using the same
US7220615B2 (en) * 2001-06-11 2007-05-22 Micron Technology, Inc. Alternative method used to package multimedia card by transfer molding
JP2003060046A (en) * 2001-08-09 2003-02-28 Murata Mfg Co Ltd Semiconductor integrated circuit and electronic apparatus using the same
JP2003188262A (en) * 2001-12-14 2003-07-04 Mitsubishi Electric Corp Semiconductor element
KR20030083306A (en) * 2002-04-20 2003-10-30 삼성전자주식회사 A memory card
JP3866178B2 (en) * 2002-10-08 2007-01-10 株式会社ルネサステクノロジ IC card
US20040084766A1 (en) * 2002-10-30 2004-05-06 Pei-Ying Shieh System-in-a-package device
CN100442514C (en) * 2002-11-29 2008-12-10 株式会社东芝 Semiconductor integrated circuit device and electronic card using it
JP2004214258A (en) * 2002-12-27 2004-07-29 Renesas Technology Corp Semiconductor module
EP1447809A1 (en) * 2003-02-14 2004-08-18 SCHLUMBERGER Systèmes Card with multiple IC's
JP4128473B2 (en) * 2003-03-07 2008-07-30 松下電器産業株式会社 Semiconductor device
KR20100107057A (en) * 2003-07-03 2010-10-04 르네사스 일렉트로닉스 가부시키가이샤 Semiconductor card device
JP4330411B2 (en) * 2003-09-24 2009-09-16 三洋電機株式会社 Circuit equipment
US7126219B2 (en) * 2003-10-09 2006-10-24 Kingpak Technology Inc. Small memory card
JP4272968B2 (en) * 2003-10-16 2009-06-03 エルピーダメモリ株式会社 Semiconductor device and semiconductor chip control method
US7253517B2 (en) * 2003-10-28 2007-08-07 Raytheon Company Method and apparatus for combining multiple integrated circuits
JP2007041629A (en) * 2003-11-04 2007-02-15 Renesas Technology Corp Memory card and semiconductor device
JP2005150154A (en) * 2003-11-11 2005-06-09 Sharp Corp Semiconductor module and its mounting method
US7095104B2 (en) * 2003-11-21 2006-08-22 International Business Machines Corporation Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same
JP2007066922A (en) * 2003-11-28 2007-03-15 Renesas Technology Corp Semiconductor integrated circuit device
US8102657B2 (en) 2003-12-02 2012-01-24 Super Talent Electronics, Inc. Single shot molding method for COB USB/EUSB devices with contact pad ribs
US8998620B2 (en) * 2003-12-02 2015-04-07 Super Talent Technology, Corp. Molding method for COB-EUSB devices and metal housing package
JP4361380B2 (en) * 2004-01-23 2009-11-11 富士通株式会社 Optical module
KR101117957B1 (en) * 2004-09-24 2012-02-16 엘지이노텍 주식회사 Protection Circuit module of innerpack
US7348661B2 (en) * 2004-09-24 2008-03-25 Intel Corporation Array capacitor apparatuses to filter input/output signal
TW200612347A (en) * 2004-10-06 2006-04-16 Advanced Flash Memory Card Technology Co Ltd Structure of memory card and producing method thereof
JP4710496B2 (en) * 2004-10-26 2011-06-29 株式会社デンソー Circuit board and electronic circuit device
KR100585163B1 (en) * 2004-11-27 2006-06-01 삼성전자주식회사 Memory cards and method of fabricating thereof
EP1662610B1 (en) 2004-11-30 2014-03-26 TDK Corporation Surge absorption circuit
JP2006155521A (en) 2004-12-01 2006-06-15 Oki Electric Ind Co Ltd Ic card
JP2006172122A (en) 2004-12-15 2006-06-29 Toshiba Corp Card type storage device
CN100405880C (en) * 2004-12-24 2008-07-23 鸿富锦精密工业（深圳）有限公司 Pin connection structure, and method for modifying definition of pin position
KR100761755B1 (en) * 2005-02-28 2007-09-28 삼성전자주식회사 Semiconductor memory device capable of controlling an input/output bit organization
DE102005014176B4 (en) * 2005-03-29 2009-08-20 Infineon Technologies Ag Method for creating a protective arrangement for protecting an electronic module from electrostatic discharges and appropriately designed electronic module
JP2007026421A (en) * 2005-06-15 2007-02-01 Toshiba Corp Portable storage device
JP2007019415A (en) * 2005-07-11 2007-01-25 Renesas Technology Corp Semiconductor device and its manufacturing method
US7317630B2 (en) * 2005-07-15 2008-01-08 Atmel Corporation Nonvolatile semiconductor memory apparatus
JP4715371B2 (en) 2005-07-29 2011-07-06 Ｔｄｋ株式会社 Surge absorbing element and surge absorbing circuit
US7429785B2 (en) * 2005-10-19 2008-09-30 Littelfuse, Inc. Stacked integrated circuit chip assembly
US7515391B2 (en) * 2005-10-19 2009-04-07 Littlefuse, Inc. Linear low capacitance overvoltage protection circuit
US7489488B2 (en) * 2005-10-19 2009-02-10 Littelfuse, Inc. Integrated circuit providing overvoltage protection for low voltage lines
WO2007056503A2 (en) * 2005-11-08 2007-05-18 Macsema, Inc. Information devices
JP2007205908A (en) * 2006-02-02 2007-08-16 Matsushita Electric Ind Co Ltd Weight sensor
TW200743035A (en) * 2006-05-09 2007-11-16 Siliconware Precision Industries Co Ltd Circuit card module and method for fabricating the same
FR2902213B1 (en) * 2006-06-08 2008-10-17 Thomson Licensing Sas ELECTRONIC CARD WITH SECURITY FUNCTIONS
KR100828956B1 (en) * 2006-06-27 2008-05-13 하나 마이크론(주) Universal Serial Bus memory package and manufacturing method the same
TWI301984B (en) * 2006-07-04 2008-10-11 Orient Semiconductor Elect Ltd Memory card with electrostatic discharge protection
US7659608B2 (en) * 2006-09-15 2010-02-09 Stats Chippac Ltd. Stacked die semiconductor device having circuit tape
JP2008084263A (en) * 2006-09-29 2008-04-10 Renesas Technology Corp Memory card and its manufacturing method
US7859814B2 (en) * 2006-10-19 2010-12-28 Littelfuse, Inc. Linear low capacitance overvoltage protection circuit using a blocking diode
US20080106415A1 (en) * 2006-11-08 2008-05-08 Macsema, Inc. Information tag
US7691668B2 (en) * 2006-12-19 2010-04-06 Spansion Llc Method and apparatus for multi-chip packaging
KR101221807B1 (en) * 2006-12-29 2013-01-14 페어차일드코리아반도체 주식회사 Power device package
US8079528B2 (en) * 2007-01-10 2011-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Input/output pads placement for a smart card chip
KR100851549B1 (en) 2007-02-01 2008-08-11 삼성전자주식회사 Memory module
US8446750B2 (en) 2007-02-01 2013-05-21 Samsung Electronics Co., Ltd. Memory module using optical signal
US7709278B2 (en) * 2007-02-26 2010-05-04 Sandisk Corporation Method of making PCB circuit modification from multiple to individual chip enable signals
US7778057B2 (en) * 2007-02-26 2010-08-17 Sandisk Corporation PCB circuit modification from multiple to individual chip enable signals
JP4913640B2 (en) * 2007-03-19 2012-04-11 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5137179B2 (en) * 2007-03-30 2013-02-06 ルネサスエレクトロニクス株式会社 Semiconductor device
TW200846797A (en) * 2007-05-28 2008-12-01 Wen-Jyh Sah Circuit board and display apparatus
WO2008152774A1 (en) * 2007-06-15 2008-12-18 Panasonic Corporation Memory card and method for manufacturing the same
US8399973B2 (en) * 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
JP2009266258A (en) 2008-04-22 2009-11-12 Hitachi Ltd Semiconductor device
US8816486B2 (en) * 2008-05-12 2014-08-26 Taiwan Semiconductor Manufacturing Co., Ltd. Pad structure for 3D integrated circuit
DE102008024479A1 (en) * 2008-05-21 2009-12-03 Epcos Ag Electrical component arrangement
JP2010003290A (en) * 2008-05-22 2010-01-07 Panasonic Corp Removable memory card,
EP2133915A1 (en) * 2008-06-09 2009-12-16 Micronas GmbH Semiconductor assembly with specially formed bonds and method for manufacturing the same
JP5253901B2 (en) 2008-06-20 2013-07-31 株式会社東芝 Memory system
JP2010021449A (en) * 2008-07-11 2010-01-28 Toshiba Corp Semiconductor device
TW201007917A (en) * 2008-08-05 2010-02-16 Kun Yuan Technology Co Ltd Method for fabricating package structure of stacked chips
KR20100021856A (en) * 2008-08-18 2010-02-26 삼성전자주식회사 Method of forming semiconductor device having tsv and related device
USD794644S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD794034S1 (en) * 2009-01-07 2017-08-08 Samsung Electronics Co., Ltd. Memory device
USD794641S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD794643S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD794642S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD795262S1 (en) * 2009-01-07 2017-08-22 Samsung Electronics Co., Ltd. Memory device
USD795261S1 (en) * 2009-01-07 2017-08-22 Samsung Electronics Co., Ltd. Memory device
US20100182092A1 (en) * 2009-01-19 2010-07-22 Tremblay John C Power sensitive variable attenuator
KR101555637B1 (en) * 2009-03-27 2015-09-24 삼성전자주식회사 Smart card
KR20100109243A (en) 2009-03-31 2010-10-08 삼성전자주식회사 Semiconductor package
KR20100129600A (en) * 2009-06-01 2010-12-09 삼성전자주식회사 Semiconductor apparatus and data memory apparatus having the same
JP2010288233A (en) * 2009-06-15 2010-12-24 Toshiba Corp Encryption processing apparatus
US8476749B2 (en) * 2009-07-22 2013-07-02 Oracle America, Inc. High-bandwidth ramp-stack chip package
JP2011048756A (en) * 2009-08-28 2011-03-10 Toshiba Corp Memory module
US8690283B2 (en) 2009-10-20 2014-04-08 Sandisk Il Ltd. Method and system for printing graphical content onto a plurality of memory devices and for providing a visually distinguishable memory device
USD638431S1 (en) 2009-10-20 2011-05-24 Sandisk Corporation MicroSD memory card with a semi-transparent color surface
USD628202S1 (en) 2009-10-20 2010-11-30 Sandisk Corporation MicroSD memory card with different color surfaces
JP5297992B2 (en) * 2009-12-15 2013-09-25 ルネサスエレクトロニクス株式会社 External storage device
JP5413189B2 (en) * 2009-12-28 2014-02-12 ソニー株式会社 Card type device
JP2012043372A (en) * 2010-08-23 2012-03-01 Fujitsu Component Ltd Card module and card module manufacturing method
TWI452665B (en) * 2010-11-26 2014-09-11 矽品精密工業股份有限公司 Anti-static package structure and fabrication method thereof
US8681546B2 (en) 2011-02-22 2014-03-25 Apple Inc. Variable impedance control for memory devices
FR2975528B1 (en) * 2011-05-17 2014-02-28 Alstom Transport Sa DEVICE FOR ELECTRICALLY INSULATING A CONDUCTIVE PLAN HAVING A FIRST ELECTRICAL POTENTIAL IN RELATION TO A SECOND POTENTIAL, COMPRISING MEANS FOR REDUCING THE ELECTROSTATIC FIELD VALUE AT A POINT OF THE PERIPHERAL EDGE OF THE CONDUCTIVE PLANE
JP2013025691A (en) * 2011-07-25 2013-02-04 Japan Radio Co Ltd Card type electronic equipment
JP2013030712A (en) * 2011-07-29 2013-02-07 Toshiba Corp Semiconductor module and method of manufacturing semiconductor module
US8368192B1 (en) * 2011-09-16 2013-02-05 Powertech Technology, Inc. Multi-chip memory package with a small substrate
KR101900423B1 (en) * 2011-09-19 2018-09-21 삼성전자주식회사 Semiconductor memory device
US9082632B2 (en) 2012-05-10 2015-07-14 Oracle International Corporation Ramp-stack chip package with variable chip spacing
JP5740372B2 (en) * 2012-09-12 2015-06-24 株式会社東芝 Semiconductor memory card
KR101540147B1 (en) * 2012-10-31 2015-07-28 삼성전기주식회사 Power module having the preventing malfunction and method thereof
KR102084553B1 (en) 2013-01-03 2020-03-04 삼성전자주식회사 Memory system
TW201507076A (en) * 2013-08-02 2015-02-16 Toshiba Kk Semiconductor device
US20150049448A1 (en) * 2013-08-13 2015-02-19 Kabushiki Kaisha Toshiba Semiconductor device
JP6235423B2 (en) * 2014-06-30 2017-11-22 東芝メモリ株式会社 Semiconductor device
KR101608226B1 (en) 2014-11-20 2016-04-14 주식회사 아모텍 Circuit protection device and mobile electronic device with the same
KR20160068546A (en) * 2014-12-05 2016-06-15 에스케이하이닉스 주식회사 Input circuit of semiconductor apparatus and semiconductor system using the same
DE102016205966A1 (en) * 2016-04-11 2017-10-12 Zf Friedrichshafen Ag Electronic unit with ESD protection arrangement
JP6790705B2 (en) * 2016-10-13 2020-11-25 セイコーエプソン株式会社 Circuits, oscillators, electronics and mobiles
US9953930B1 (en) * 2016-10-20 2018-04-24 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
JP2018202026A (en) * 2017-06-08 2018-12-27 株式会社オリンピア Game machine
KR102440366B1 (en) * 2018-01-04 2022-09-05 삼성전자주식회사 Memory card and electronic apparatus including the same
JP2020053655A (en) * 2018-09-28 2020-04-02 キオクシア株式会社 Semiconductor device and method for manufacturing semiconductor device
TWI681695B (en) 2019-01-31 2020-01-01 瑞昱半導體股份有限公司 Signal processing circuit capable of avoiding cooperating memory chip from performance degradation
US10892236B2 (en) * 2019-04-30 2021-01-12 Qualcomm Incorporated Integrated circuit having a periphery of input/output cells
FR3102642B1 (en) * 2019-10-23 2022-07-15 Safran Electronics & Defense Electronic card comprising a first ground plane and a second ground plane
CN110867435A (en) * 2019-10-30 2020-03-06 北京新忆科技有限公司 Memory device
US11869823B2 (en) * 2019-11-08 2024-01-09 Octavo Systems Llc System in a package modifications
US11329035B2 (en) * 2020-04-16 2022-05-10 International Business Machines Corporation Tetherless chip module
JP2022147368A (en) * 2021-03-23 2022-10-06 キオクシア株式会社 memory device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4896028A (en) * 1986-06-11 1990-01-23 Kabushiki Kaisha Toshiba Surge absorption apparatus
JPH02240792A (en) * 1989-03-15 1990-09-25 Matsushita Electric Ind Co Ltd Terminal equipment for ic card
US5378944A (en) * 1992-05-20 1995-01-03 Mitsubishi Denki Kabushiki Kaisha IC card input/output control circuit
US5451763A (en) * 1994-07-05 1995-09-19 Alto Corporation Personal medical IC card and read/write unit
JPH07271937A (en) 1994-03-29 1995-10-20 Sony Corp Information card
US5550402A (en) * 1992-11-27 1996-08-27 Esec Sempac S.A. Electronic module of extra-thin construction
US5715431A (en) * 1993-04-13 1998-02-03 Mondex International Limited Tamper proof security measure in data writing to non-volatile memory
JPH10209379A (en) 1997-01-22 1998-08-07 Rohm Co Ltd Semiconductor device
US5988509A (en) * 1995-06-01 1999-11-23 American Express Trs Refundable prepaid telephone card
US6235553B1 (en) * 1997-01-15 2001-05-22 Transaction Technology, Inc. Method and system for creating and using an electrostatic discharge (ESD) protected logotype contact module with a smart card

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2567970B1 (en) 1984-07-23 1989-04-28 Normetex COMPLETELY DRY AND WATERPROOF VACUUM PUMP WITH RECTILINEAR MOTION OF COMPRESSION COMPRESSION
US4918631A (en) * 1984-09-07 1990-04-17 Casio Computer Co., Ltd. Compact type electronic information card
JPS61193283A (en) 1985-02-20 1986-08-27 Matsushita Electric Ind Co Ltd Ic card
JPH0755587B2 (en) 1985-10-21 1995-06-14 日立マクセル株式会社 IC card
JPH0682405B2 (en) 1986-01-14 1994-10-19 カシオ計算機株式会社 Test program start method
JPS63149191A (en) * 1986-12-15 1988-06-21 日立マクセル株式会社 Ic card
US4861656A (en) * 1986-12-24 1989-08-29 Tdk Corporation Optical recording medium
JPS63211049A (en) 1987-02-27 1988-09-01 Toshiba Corp Portable electronic equipment
JPS6444171A (en) 1987-08-12 1989-02-16 Ricoh Kk Picture signal processor
US4896058A (en) * 1988-04-26 1990-01-23 North American Philips Corp. TTL circuit having ramped current output
US5048510A (en) 1988-08-29 1991-09-17 American Medical Systems, Inc. Inflatable penile prosthesis with satellite reservoir
JPH02249088A (en) 1989-03-22 1990-10-04 Toshiba Corp Memory card system
JPH03144823A (en) 1989-10-31 1991-06-20 N T T Data Tsushin Kk Controller for communication between ic card and host device
SG52794A1 (en) 1990-04-26 1998-09-28 Hitachi Ltd Semiconductor device and method for manufacturing same
JP3104795B2 (en) 1990-04-26 2000-10-30 株式会社日立製作所 Semiconductor device and manufacturing method thereof
JPH04302164A (en) 1991-03-29 1992-10-26 Fujitsu Ltd Semiconductor device
JPH0521714A (en) 1991-07-10 1993-01-29 Fujitsu Ltd Overvoltage protection circuit
JP3006208B2 (en) 1991-08-23 2000-02-07 株式会社村田製作所 Manufacturing method of chip type varistor
FR2694840B1 (en) * 1992-08-13 1994-09-09 Commissariat Energie Atomique Three-dimensional multi-chip module.
JPH0830747A (en) * 1994-07-20 1996-02-02 Sony Corp Memory card
JPH08129627A (en) 1994-11-01 1996-05-21 Fujitsu Ltd Memory card and integrated circuit
JP3559322B2 (en) 1994-11-14 2004-09-02 株式会社東芝 Method of manufacturing thin composite IC card
JPH08167017A (en) * 1994-12-14 1996-06-25 Mitsubishi Electric Corp Ic card
JP3059349B2 (en) 1994-12-19 2000-07-04 シャープ株式会社 IC card and flash memory parallel processing method
JPH08190615A (en) 1995-01-09 1996-07-23 Seiko Epson Corp Memory card
US5506499A (en) * 1995-06-05 1996-04-09 Neomagic Corp. Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad
WO1997004376A1 (en) * 1995-07-20 1997-02-06 Dallas Semiconductor Corporation Secure module with microprocessor and co-processor
JP2734424B2 (en) 1995-08-16 1998-03-30 日本電気株式会社 Semiconductor device
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
JPH09282900A (en) * 1996-04-11 1997-10-31 Oki Electric Ind Co Ltd Memory module
US5815426A (en) * 1996-08-13 1998-09-29 Nexcom Technology, Inc. Adapter for interfacing an insertable/removable digital memory apparatus to a host data part
JPH10203066A (en) * 1997-01-28 1998-08-04 Hitachi Ltd Non-contact ic card
JPH10214232A (en) * 1997-01-30 1998-08-11 Rohm Co Ltd Ic card, and ic card operating method
JP4212068B2 (en) * 1997-05-19 2009-01-21 ローム株式会社 IC card and IC chip module
US5987357A (en) * 1997-07-30 1999-11-16 Intermedics Inc. Stackable microelectronic components with self-addressing scheme
GB9720148D0 (en) * 1997-09-22 1997-11-26 Innes John Centre Innov Ltd Gene silencing materials and methods
JP3901811B2 (en) * 1997-10-15 2007-04-04 カルソニックカンセイ株式会社 Integration device and integration method
JPH11168185A (en) * 1997-12-03 1999-06-22 Rohm Co Ltd Laminated substrate body and semiconductor device
JP3481444B2 (en) 1998-01-14 2003-12-22 シャープ株式会社 Semiconductor device and manufacturing method thereof
JP2865102B2 (en) 1998-01-19 1999-03-08 株式会社日立製作所 Multi-chip module
JPH11273400A (en) 1998-03-24 1999-10-08 Hitachi Ltd Storage
JPH11296430A (en) 1998-04-08 1999-10-29 Hitachi Ltd Storage device and flash memory
US6315195B1 (en) * 1998-04-17 2001-11-13 Diebold, Incorporated Transaction apparatus and method
US6040622A (en) 1998-06-11 2000-03-21 Sandisk Corporation Semiconductor package using terminals formed on a conductive layer of a circuit board
WO2000007143A1 (en) * 1998-07-31 2000-02-10 Matsushita Electronics Corporation Portable body used in two way, communication system, communication method, terminal, computer-readable recorded medium on which program is recorded
CN100370612C (en) 1998-12-02 2008-02-20 株式会社日立制作所 Semiconductor device
US7093991B2 (en) * 1999-05-25 2006-08-22 Silverbrook Research Pty Ltd Combined printer and binder
JP3822768B2 (en) 1999-12-03 2006-09-20 株式会社ルネサステクノロジ IC card manufacturing method
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
JP3768761B2 (en) * 2000-01-31 2006-04-19 株式会社日立製作所 Semiconductor device and manufacturing method thereof
EP1278154A4 (en) * 2000-04-28 2004-08-25 Hitachi Ltd Ic card
CN100435170C (en) * 2001-04-02 2008-11-19 株式会社日立制作所 Memory card
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6843421B2 (en) * 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
JP4564215B2 (en) * 2001-09-26 2010-10-20 株式会社東芝 Flash memory rewriting circuit, IC card LSI, IC card, and flash memory rewriting method
US6731011B2 (en) * 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
JP4497874B2 (en) * 2002-12-13 2010-07-07 株式会社ルネサステクノロジ Semiconductor integrated circuit and IC card
US20050067694A1 (en) * 2003-09-30 2005-03-31 Pon Florence R. Spacerless die stacking
US7064430B2 (en) * 2004-08-31 2006-06-20 Stats Chippac Ltd. Stacked die packaging and fabrication method
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
US20070287824A1 (en) * 2006-06-08 2007-12-13 Johnson Mitchell T Waterbased polyurethane floor coating composition
JP4302164B2 (en) 2006-12-15 2009-07-22 三洋電機株式会社 Illumination device and projection display device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4896028A (en) * 1986-06-11 1990-01-23 Kabushiki Kaisha Toshiba Surge absorption apparatus
JPH02240792A (en) * 1989-03-15 1990-09-25 Matsushita Electric Ind Co Ltd Terminal equipment for ic card
US5378944A (en) * 1992-05-20 1995-01-03 Mitsubishi Denki Kabushiki Kaisha IC card input/output control circuit
US5550402A (en) * 1992-11-27 1996-08-27 Esec Sempac S.A. Electronic module of extra-thin construction
US5715431A (en) * 1993-04-13 1998-02-03 Mondex International Limited Tamper proof security measure in data writing to non-volatile memory
JPH07271937A (en) 1994-03-29 1995-10-20 Sony Corp Information card
US5451763A (en) * 1994-07-05 1995-09-19 Alto Corporation Personal medical IC card and read/write unit
US5988509A (en) * 1995-06-01 1999-11-23 American Express Trs Refundable prepaid telephone card
US6235553B1 (en) * 1997-01-15 2001-05-22 Transaction Technology, Inc. Method and system for creating and using an electrostatic discharge (ESD) protected logotype contact module with a smart card
JPH10209379A (en) 1997-01-22 1998-08-07 Rohm Co Ltd Semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Protecting Chips Cards Against Electrostatic Discharge" IBM Technical Disclosure Bulletin, Mar. 1984, vol. 26, Issue 10A, pp. 5091-5093.* *
"Smart Cards: Seizing Strategic Business Oppurtunities", The Smart Card Forum, Edited by Catherine A. Allen and William J. Barr with Ron Schultz, McGraw-Hill publishers, 1997, pp. 33-34. *

Cited By (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018038B2 (en) 1999-12-03 2011-09-13 Renesas Electronics Corporation IC card with terminals for direct access to internal components
US20080023562A1 (en) * 1999-12-03 2008-01-31 Hirotaka Nishizawa Ic card
US7768110B2 (en) 1999-12-03 2010-08-03 Renesas Technology Corp. Nonvolatile memory apparatus
US20100277963A1 (en) * 1999-12-03 2010-11-04 Renesas Technology Corp. Ic card
US20050090129A1 (en) * 2000-01-25 2005-04-28 Hitachi, Ltd. IC card
US20080257968A1 (en) * 2000-01-25 2008-10-23 Hirotaka Nishizawa Ic card
US7048197B2 (en) 2000-01-25 2006-05-23 Renesas Technology Corp. IC card
US7055757B2 (en) 2000-01-25 2006-06-06 Renesas Technology Corp. IC card
US20060157573A1 (en) * 2000-01-25 2006-07-20 Renesas Technology Corp. IC card
US20060157572A1 (en) * 2000-01-25 2006-07-20 Renesas Technology Corp. IC card
US20050090128A1 (en) * 2000-01-25 2005-04-28 Hitachi, Ltd. IC card
US7234644B2 (en) 2000-01-25 2007-06-26 Renesas Technology Corp. IC card
US20040084538A1 (en) * 2000-01-25 2004-05-06 Hitachi, Ltd. IC card
US7303138B2 (en) 2000-01-25 2007-12-04 Renesas Technology Corp. Integrated circuit card having staggered sequences of connector terminals
US7552876B2 (en) 2000-01-25 2009-06-30 Renesas Technology Corp. IC card
US6641049B2 (en) * 2000-08-31 2003-11-04 Pacusma Company, Ltd. Integrated circuit card with multiple integral electronic modules
US20060033191A1 (en) * 2001-04-02 2006-02-16 Renesas Technology Corp. Memory card
US7239011B2 (en) 2001-04-02 2007-07-03 Renesas Technology Corp. Memory card with a cap having indented portions
US20030034552A1 (en) * 2001-04-02 2003-02-20 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US7271475B2 (en) 2001-04-02 2007-09-18 Renesas Technology Corp. Memory card with connecting portions for connection to an adapter
US20090283885A1 (en) * 2001-04-02 2009-11-19 Renesas Technology Corp. Semiconductor Device and a Method of Manufacturing the Same
US7053471B2 (en) * 2001-04-02 2006-05-30 Renesas Technologies Corp. Memory card
US20060220204A1 (en) * 2001-04-02 2006-10-05 Renesas Technology Corp. Memory card
US20030117785A1 (en) * 2001-04-02 2003-06-26 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6858925B2 (en) 2001-04-02 2005-02-22 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US20060220203A1 (en) * 2001-04-02 2006-10-05 Renesas Technology Corp. Memory card
US7233058B2 (en) 2001-04-02 2007-06-19 Renesas Technology Corp. Memory card with an adaptor
US20050280131A1 (en) * 2001-04-02 2005-12-22 Renesas Technology Corp. Memory card
US7294918B2 (en) 2001-04-02 2007-11-13 Renesas Technology Corp. Memory card with connecting portions for connection to an adapter
US20030029920A1 (en) * 2001-08-13 2003-02-13 Chhor Khushrav S. Molded memory module and method of making the module absent a substrate support
US6843421B2 (en) * 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
US20030102569A1 (en) * 2001-08-17 2003-06-05 Edward Reyes Method and apparatus for die stacking
US6680219B2 (en) * 2001-08-17 2004-01-20 Qualcomm Incorporated Method and apparatus for die stacking
US6787901B2 (en) * 2001-08-17 2004-09-07 Qualcomm Incorporated Stacked dies utilizing cross connection bonding wire
US20040008538A1 (en) * 2001-09-18 2004-01-15 Peng Jack Zezhong Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US6798693B2 (en) 2001-09-18 2004-09-28 Kilopass Technologies, Inc. Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US20040047218A1 (en) * 2001-09-18 2004-03-11 Kilopass Technologies, Inc. Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US6822888B2 (en) 2001-09-18 2004-11-23 Kilopass Technologies, Inc. Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US6766960B2 (en) 2001-10-17 2004-07-27 Kilopass Technologies, Inc. Smart card having memory using a breakdown phenomena in an ultra-thin dielectric
US20030071296A1 (en) * 2001-10-17 2003-04-17 Peng Jack Zezhong Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric
WO2003034331A1 (en) * 2001-10-17 2003-04-24 Kilopass Technologies, Inc. Smart card having a memory using a ultra-thin dielectric
US6956258B2 (en) 2001-10-17 2005-10-18 Kilopass Technologies, Inc. Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric
US6856540B2 (en) 2002-04-26 2005-02-15 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor
US6940751B2 (en) 2002-04-26 2005-09-06 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown
US20030202376A1 (en) * 2002-04-26 2003-10-30 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor
US20030206467A1 (en) * 2002-04-26 2003-11-06 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor
US20040223363A1 (en) * 2002-04-26 2004-11-11 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
US20040125671A1 (en) * 2002-04-26 2004-07-01 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection
US6992925B2 (en) 2002-04-26 2006-01-31 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
US6777757B2 (en) 2002-04-26 2004-08-17 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor
US6898116B2 (en) 2002-04-26 2005-05-24 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection
US20040156234A1 (en) * 2002-04-26 2004-08-12 Peng Jack Zezhong High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown
US7528467B2 (en) 2002-06-19 2009-05-05 Inpaq Technology Co., Ltd. IC substrate with over voltage protection function
US20060138610A1 (en) * 2002-06-19 2006-06-29 Inpaq Technology Co., Ltd. Ball grid array IC substrate with over voltage protection function
US20040000725A1 (en) * 2002-06-19 2004-01-01 Inpaq Technology Co., Ltd. IC substrate with over voltage protection function and method for manufacturing the same
US20060138611A1 (en) * 2002-06-19 2006-06-29 Inpaq Technology Co., Ltd. IC substrate with over voltage protection function
US7053468B2 (en) * 2002-06-19 2006-05-30 Inpaq Technology Co., Ltd. IC substrate having over voltage protection function
US20060138609A1 (en) * 2002-06-19 2006-06-29 Inpaq Technology Co., Ltd. IC substrate with over voltage protection function
US20060138608A1 (en) * 2002-06-19 2006-06-29 Inpaq Technology Co., Ltd. IC substrate with over voltage protection function
US7513421B2 (en) 2002-08-16 2009-04-07 Fujitsu Limited Transaction terminal device and transaction terminal control method
US20080041933A1 (en) * 2002-08-16 2008-02-21 Fujitsu Limited Transaction terminal device and transaction terminal control method
US7293700B2 (en) * 2002-08-16 2007-11-13 Fujitsu Limited Transaction terminal device and transaction terminal control method
US20050145690A1 (en) * 2002-08-16 2005-07-07 Fujitsu Limited Transaction terminal device and transaction terminal control method
US7387259B2 (en) 2002-09-17 2008-06-17 Axalto S.A. Hybrid card
US20060104041A1 (en) * 2002-09-17 2006-05-18 Axalto Sa Hybrid card
US7042772B2 (en) 2002-09-26 2006-05-09 Kilopass Technology, Inc. Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US7031209B2 (en) 2002-09-26 2006-04-18 Kilopass Technology, Inc. Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US20040208055A1 (en) * 2002-09-26 2004-10-21 Jianguo Wang Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US20040223370A1 (en) * 2002-09-26 2004-11-11 Jianguo Wang Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US20040135241A1 (en) * 2002-11-18 2004-07-15 Storcard, Inc. Secure transaction card with a large storage volume
US6791891B1 (en) 2003-04-02 2004-09-14 Kilopass Technologies, Inc. Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage
US20050035783A1 (en) * 2003-08-15 2005-02-17 Man Wang Field programmable gate array
US6924664B2 (en) 2003-08-15 2005-08-02 Kilopass Technologies, Inc. Field programmable gate array
US6977521B2 (en) 2003-08-15 2005-12-20 Klp International, Ltd. Field programmable gate array
US20060033528A1 (en) * 2003-08-15 2006-02-16 Klp International Ltd. Field programmable gate array
US20050184754A1 (en) * 2003-08-15 2005-08-25 Kilopass Technologies, Inc. Field programmable gate array
US7061275B2 (en) 2003-08-15 2006-06-13 Klp International, Ltd. Field programmable gate array
US6972986B2 (en) 2004-02-03 2005-12-06 Kilopass Technologies, Inc. Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown
US20050169039A1 (en) * 2004-02-03 2005-08-04 Peng Jack Z. Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown
US7064973B2 (en) 2004-02-03 2006-06-20 Klp International, Ltd. Combination field programmable gate array allowing dynamic reprogrammability
US20050169040A1 (en) * 2004-02-03 2005-08-04 Peng Jack Z. Combination field programmable gate array allowing dynamic reprogrammability
US20050218929A1 (en) * 2004-04-02 2005-10-06 Man Wang Field programmable gate array logic cell and its derivatives
US8026574B2 (en) 2004-05-06 2011-09-27 Sidense Corporation Anti-fuse memory cell
US9123572B2 (en) 2004-05-06 2015-09-01 Sidense Corporation Anti-fuse memory cell
US8735297B2 (en) 2004-05-06 2014-05-27 Sidense Corporation Reverse optical proximity correction method
US8313987B2 (en) 2004-05-06 2012-11-20 Sidense Corp. Anti-fuse memory cell
US8283751B2 (en) 2004-05-06 2012-10-09 Sidense Corp. Split-channel antifuse array architecture
US7310242B2 (en) * 2004-05-21 2007-12-18 General Motors Corporation Self-shielding high voltage distribution box
US20050259408A1 (en) * 2004-05-21 2005-11-24 Sergio Ramos Self-shielding high voltage distribution box
US7164290B2 (en) 2004-06-10 2007-01-16 Klp International, Ltd. Field programmable gate array logic unit and its cluster
US20050275428A1 (en) * 2004-06-10 2005-12-15 Guy Schlacter Field programmable gate array logic unit and its cluster
US20050275427A1 (en) * 2004-06-10 2005-12-15 Man Wang Field programmable gate array logic unit and its cluster
US6903935B1 (en) * 2004-07-16 2005-06-07 Tien-Tzu Chen Memory card with a static electricity conducting board
US7135886B2 (en) 2004-09-20 2006-11-14 Klp International, Ltd. Field programmable gate arrays using both volatile and nonvolatile memory cell properties and their control
US20060062068A1 (en) * 2004-09-20 2006-03-23 Guy Schlacter Field programmable gate arrays using both volatile and nonvolatile memory cell properties and their control
US7466577B2 (en) * 2005-03-30 2008-12-16 Hitachi, Ltd., Intellectual Property Group Semiconductor storage device having a plurality of stacked memory chips
US20060233012A1 (en) * 2005-03-30 2006-10-19 Elpida Memory, Inc. Semiconductor storage device having a plurality of stacked memory chips
US7193436B2 (en) 2005-04-18 2007-03-20 Klp International Ltd. Fast processing path using field programmable gate array logic units
US20060232296A1 (en) * 2005-04-18 2006-10-19 Kilopass Technologies, Inc. Fast processing path using field programmable gate array logic unit
US7719845B1 (en) * 2005-04-26 2010-05-18 Amkor Technology, Inc. Chamfered memory card module and method of making same
US20060261489A1 (en) * 2005-05-23 2006-11-23 Yasuo Takemoto Semiconductor memory card and method of fabricating the same
US20070158440A1 (en) * 2006-01-06 2007-07-12 Renesas Technology Corp. Semiconductor device
US20100084762A1 (en) * 2006-04-21 2010-04-08 Hidenobu Nishikawa Memory card
US8599571B2 (en) * 2006-04-21 2013-12-03 Panasonic Corporation Memory card
US8518744B2 (en) 2006-09-21 2013-08-27 Renesas Electronics Corporation Method of manufacturing semiconductor device
US20110159641A1 (en) * 2006-09-21 2011-06-30 Renesas Electronics Corporation Method of manufacturing semiconductor device
US20080169573A1 (en) * 2007-01-16 2008-07-17 Advanced Semiconductor Engineering, Inc. Circuit substrate and the semiconductor package having the same
US7893530B2 (en) * 2007-01-16 2011-02-22 Advanced Semiconductor Engineering, Inc. Circuit substrate and the semiconductor package having the same
US8987053B2 (en) * 2007-12-27 2015-03-24 Sandisk Technologies Inc. Semiconductor package including flip chip controller at bottom of die stack
US7894172B2 (en) 2008-01-10 2011-02-22 Industrial Technology Research Institute ESD protection structure
US20090180225A1 (en) * 2008-01-10 2009-07-16 Industrial Technology Research Institute Esd protection structure
US11166363B2 (en) * 2019-01-11 2021-11-02 Tactotek Oy Electrical node, method for manufacturing electrical node and multilayer structure comprising electrical node
US11166364B2 (en) 2019-01-11 2021-11-02 Tactotek Oy Electrical node, method for manufacturing electrical node and multilayer structure comprising electrical node

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