US6417050B1 - Semiconductor component and method of manufacture - Google Patents
Semiconductor component and method of manufacture Download PDFInfo
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- US6417050B1 US6417050B1 US09/636,646 US63664600A US6417050B1 US 6417050 B1 US6417050 B1 US 6417050B1 US 63664600 A US63664600 A US 63664600A US 6417050 B1 US6417050 B1 US 6417050B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000002019 doping agent Substances 0.000 claims description 23
- 239000007943 implant Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 7
- 230000001590 oxidative effect Effects 0.000 claims 4
- 238000000137 annealing Methods 0.000 claims 3
- 238000004140 cleaning Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- -1 for example Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002789 length control Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
Definitions
- This invention relates, in general, to electronics, and more particularly, to semiconductor components and methods of manufacture.
- Semiconductor components include integrated circuits, discrete power transistors, and combinations thereof.
- One type of discrete power transistor is known as a trench power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), which is a vertical transistor with a gate electrode located in a trench that is etched into a semiconductor substrate.
- MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
- trench power MOSFETs have a channel structure that poorly controls source-drain punch-through and cannot achieve high insulation voltage resistance. To reduce the magnitude of these deficiencies, the size of these trench power MOSFETs is increased, which produces a low cell density.
- V-MOSFET Another type of discrete power transistor is known as a V-MOSFET.
- a V-MOSFET is similar to a trench power MOSFET, except that the trench of the V-MOSFET has the shape of a “V”.
- V-MOSFETs also have low cell densities and can neither achieve high insulation voltage resistance nor adequately control source-drain punch-through.
- FIGS. 1 through 15 illustrate cross-sectional views of a portion of a semiconductor component after different steps of a manufacturing process in accordance with an embodiment of the invention.
- FIG. 16 outlines a method of manufacturing the semiconductor component of FIGS. 1 through 15 in accordance with an embodiment of the invention.
- top, bottom, over, under, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein can exist in other orientations than described or illustrated herein.
- FIGS. 1 through 15 illustrate cross-sectional views of a portion of a semiconductor component 100 after different steps of a manufacturing process.
- Component 100 can comprise a power MOSFET and can also comprise an integrated circuit.
- component 100 consists only of a discrete vertically insulated power MOSFET.
- component 100 is illustrated to include a semiconductor substrate 110 having a surface 113 .
- substrate 110 comprises a support layer 111 and an epitaxial layer 112 .
- Layer 111 has a first conductivity type and a first doping concentration.
- the first conductivity type can be an n-type conductivity.
- Layer 112 overlies layer 111 and also has the first conductivity type. However, layer 112 has a second doping concentration that is less than the first doping concentration of layer 111 .
- layer 112 can have an N ⁇ conductivity type, and layer 111 can have an N+ conductivity type. Both layers 111 and 112 can be comprised of silicon.
- Layer 112 forms surface 113 of substrate 110 , and layer 111 serves as a drain region for component 100 .
- a first layer 120 is disposed or formed over surface 113 of substrate 110 .
- layer 120 can be comprised of an electrically insulative material and can have a thickness of approximately 200 to 2,000 nanometers. The thickness of layer 120 defines the gate length of the MOSFET in component 100 . Gate length control is more precise and easier for the MOSFET in component 100 because of vertical structure of the MOSFET as compared to conventional planar MOSFETs.
- layer 120 is comprised of silicon dioxide that is thermally grown on surface 113 of substrate 110 .
- layer 112 can be oxidized to form layer 120 .
- layer 120 can be comprised of a different electrically insulative material such silicon nitride or a semiconductor material such as silicon.
- an etch mask 210 is formed over layer 120 .
- mask 210 can be comprised of photoresist.
- Mask 210 exposes a portion of layer 120 and defines a trench to be etched sequentially into layers 120 and 112 .
- a trench 310 has been etched into layers 120 and 112 .
- mask 210 (FIG. 1) defines trench 310 in layer 120 , and then mask 210 is removed.
- layer 120 is used as a self-aligned etch mask for etching trench 310 into layer 112 .
- the process of forming trench 310 into layer 112 damages the exposed surface of layer 112 that defines trench 310 .
- the exposed surface of layer 112 is used as a seed crystal over which an epitaxial or crystalline layer is subsequently formed. Therefore, this damaged surface of layer 112 is removed by using a down-flow plasma clean or a wet clean to expose an undamaged and crystalline portion of layer 112 .
- trench 310 is prevented from extending into layer 111 .
- the process for forming trench 310 does not begin until after layer 120 is formed.
- the portion of trench 310 located in layer 112 can be formed prior to the formation of layer 120 .
- a second layer 410 is disposed, formed, or deposited over substrate 110 .
- Layer 410 is comprised of a semiconductor material such as, for example, silicon.
- Layer 410 is located over layer 120 , over layer 112 , and in trench 310 .
- layer 410 is deposited on layers 120 and 112 .
- Layer 410 is an electrically conductive layer.
- layer 410 has a second conductivity type and has a third doping concentration that is less than the first doping concentration of layer 111 .
- layer 410 can have a thickness of approximately 20 to 250 nanometers.
- the second conductivity type can be a p-type conductivity.
- layer 410 is deposited as an epitaxial layer and is subsequently annealed to align the crystalline structure of layer 410 with the crystalline structure of layer 112 . Also in the preferred embodiment, this anneal step is performed before layer 410 is implanted with different dopants. In an alternative embodiment, layer 410 is deposited with a polycrystalline structure. In this alternative embodiment, layer 410 is annealed to change the atomic structure of layer 410 from polycrystalline to crystalline.
- an implant mask 510 is formed over layer 410 .
- mask 510 can be comprised of photoresist.
- Mask 510 exposes trench 310 and the portion of layer 410 located within trench 310 .
- Mask 510 is used to define a portion of layer 410 that is to be converted from the second conductivity type to the first conductivity type.
- layer 410 is illustrated to include a portion 416 that has been implanted with a dopant of the first conductivity type. Accordingly, portion 416 has the first conductivity type while other portions of layer 410 still have the second conductivity type.
- a first implant concentration of a first dopant can be implanted into portion 416 to convert portion 416 from the second conductivity type to the first conductivity type.
- the doping concentration of portion 416 is preferably substantially similar to the doping concentration of layer 112 .
- Portion 416 of layer 410 is located at the bottom of trench 310 . Portion 416 of layer 410 can be annealed to activate the implanted dopant in portion 416 .
- portions 417 of layer 410 located along the side walls of trench 310 are preferably prevented from being substantially implanted with the first dopant. Accordingly, the side walls of trench 310 are preferably substantially vertical with respect to surface 113 of substrate 110 . Furthermore, the implantation angle of the first dopant is preferably substantially perpendicular to surface 113 of substrate 110 . Portions 417 serve as the channel region for component 100 .
- an implant mask 710 is formed over layer 410 .
- mask 710 can be comprised of photoresist.
- Mask 710 exposes portions of layer 410 and defines source regions within layer 410 .
- layer 410 is illustrated to include portions 418 that have been implanted with a dopant of the first conductivity type. Portions 418 serve as source regions for component 100 .
- a second implant concentration of the first dopant can be implanted into layer 410 to form portions 418 .
- the second implant concentration is greater than the first implant concentration used to form portion 416 in layer 410 .
- the dopant species implanted into portions 418 is preferably the same as the dopant species implanted into portion 416 and the dopant species located in layers 112 and 111 . Accordingly, portions 418 can have an N+ conductivity type, and portion 416 can have an N ⁇ conductivity type. Portions 418 of layer 410 can be annealed to activate the implant dopant in portions 418 .
- portions 417 are preferably prevented from being substantially implanted during the implantation of portions 418 . Accordingly, portions 417 continue to have the second conductivity type while portions 418 is converted from the second conductivity type to the first conductivity type.
- an implantation mask 910 is formed over layer 410 .
- mask 910 can be comprised of photoresist.
- Mask 910 exposes portions of layer 410 and defines isolation regions to be formed in layer 410 .
- layer 410 is illustrated to include portions 411 that have been implanted with a third implant concentration of a second dopant.
- the third implant concentration is greater than the first implant concentration used to form portions 416 of layer 410 .
- the second dopant used to form portions 411 of layer 410 increases the doping concentration of the second conductivity type in portions 411 . Accordingly, portions 411 have a P+ conductivity type.
- Portions 411 are located outside of trench 310 , adjacent to the rim of trench 310 , and also adjacent to portions 418 .
- Portions 411 of layer 410 can be annealed to activate the implanted dopant in portions 411 . In a different embodiment, a single anneal can be used to simultaneously activate the dopants implanted into portions 416 , 418 , and 411 of layer 410 .
- layer 410 is oxidized, and the oxidation layer is removed. This sacrificial oxidation process cleans the surface of layer 410 to ensure a high-quality gate oxide that is subsequently formed over layer 410 .
- a third layer 1210 is disposed or formed over layer 410 .
- layer 1210 is formed on layer 410 .
- layer 1210 can have a thickness of approximately 3.5 to 25 nanometers.
- Layer 1210 serves as a gate oxide for component 100 .
- layer 1210 is comprised of an electrically insulative material such as, for example, silicon dioxide, silicon nitride, or both.
- layer 1210 is thermally grown over layer 410 using an oxidation process. This oxidation process is preferably performed after the implantation steps used to form portions 416 , 418 , and 411 in layer 410 .
- Layer 1210 does not need to be formed over the entire surface of layer 410 , but can be formed only in and around trench 310 .
- a fourth layer 1310 is disposed or deposited over layer 1210 and in trench 310 .
- layer 1310 is formed on layer 1210 , is comprised of a semiconductor material such as silicon, has a polycrystalline structure, and has a thickness of approximately 17.5 to 175 nanometers.
- layers 1310 and 1210 are etched.
- layer 1310 is etched to form or define a gate contact 1410 in layer 1310 .
- Contact 1410 is located in trench 310 .
- layer 1210 is etched to expose a portion of the surface of layer 410 .
- source contacts 1520 and a drain contact 1530 are formed.
- an electrically insulative layer 1510 is deposited and patterned over layer 410 . The remaining portion of layer 1510 covers gate contact 1410 and exposes portions of portions 418 of layer 410 .
- source contacts 1520 are formed over layer 1510 and 410 . Source contacts 1520 are coupled to portions 418 of layer 410 .
- support layer 111 is thinned to a thickness of approximately 50 to 350 micrometers.
- a drain contact 1530 is formed adjacent to layer 111 . Drain contact 1530 is coupled to layer 111 .
- component 100 has higher cell density than conventional planar power MOSFETs, trench power MOSFETs, and power V-MOSFETs. Component 100 can also have a low on resistance because of the high cell density of component 100 . Furthermore, component 100 can have a submicron gate length with a large channel width. Component 100 can conduct high drain currents because of the large channel width and the short channel length of component 100 .
- component 100 prevents the generation of an unnecessary depletion layer around the drain region. Therefore, component 100 can control the punch-through phenomenon between the source and drain regions of component 100 .
- the source-drain punch-through can be controlled even at high drain voltage conditions.
- the shallow or thin channel region surrounded by a thick silicon dioxide layer minimizes the parasitic capacitance beneath the gate contact.
- the minimization of the parasitic gate capacitance eliminates the need to charge and discharge the parasitic capacitance. Accordingly, component 100 can operate at high frequencies.
- component 100 can have high insulation voltage resistance.
- FIG. 16 outlines a method of manufacturing semiconductor component 100 that was previously described in detail with reference to FIGS. 1 through 15.
- a semiconductor substrate is provided.
- a first electrically insulative layer is thermally grown on the semiconductor substrate.
- a trench is etched into the first electrically insulative layer and the semiconductor substrate, and at a step 1620 , the etched portion of the semiconductor substrate is cleaned.
- a semiconductor layer is deposited in the trench.
- the semiconductor layer is annealed, and then at a step 1635 , the semiconductor layer is implanted.
- a step 1640 of method 1600 the semiconductor layer is annealed again, and at a step 1645 , a second electrically insulative layer is thermally grown on the semiconductor layer. Then, at a step 1650 , a gate contact is formed in the trench, and at a step 1655 , a source contact is formed. Next, at a step 1660 of method 1600 , a drain contact is formed.
- the semiconductor component described herein has high cell density, can control the punch-through phenomenon, has low on resistance, can operate at high frequencies, and can have a high insulation voltage resistance.
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
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Priority Applications (1)
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US09/636,646 US6417050B1 (en) | 2000-08-07 | 2000-08-07 | Semiconductor component and method of manufacture |
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US09/636,646 US6417050B1 (en) | 2000-08-07 | 2000-08-07 | Semiconductor component and method of manufacture |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050233541A1 (en) * | 2002-03-05 | 2005-10-20 | Samsung Electronics, Co., Ltd. | Semiconductor device having dual isolation structure and method of fabricating the same |
US20090061584A1 (en) * | 2007-08-27 | 2009-03-05 | Wei-Chieh Lin | Semiconductor Process for Trench Power MOSFET |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5293053A (en) * | 1986-10-08 | 1994-03-08 | Texas Instruments Incorporated | Elevated CMOS |
US5923980A (en) * | 1996-10-30 | 1999-07-13 | Advanced Micro Devices, Inc. | Trench transistor with localized source/drain regions implanted through voids in trench |
US5998267A (en) * | 1998-09-18 | 1999-12-07 | National Semiconductor Corporation | Process to manufacture high density ULSI ROM array |
US6010930A (en) * | 1996-01-22 | 2000-01-04 | Micron Technology Inc. | Vertically oriented structure with sloped opening and method for etching |
US6077744A (en) * | 1999-02-22 | 2000-06-20 | Intersil Corporation | Semiconductor trench MOS devices |
US6100146A (en) * | 1996-10-30 | 2000-08-08 | Advanced Micro Devices, Inc. | Method of forming trench transistor with insulative spacers |
US6191446B1 (en) * | 1998-03-04 | 2001-02-20 | Advanced Micro Devices, Inc. | Formation and control of a vertically oriented transistor channel length |
US6225161B1 (en) * | 1998-03-30 | 2001-05-01 | Advanced Micro Devices, Inc. | Fully recessed semiconductor method for low power applications with single wrap around buried drain region |
-
2000
- 2000-08-07 US US09/636,646 patent/US6417050B1/en not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5293053A (en) * | 1986-10-08 | 1994-03-08 | Texas Instruments Incorporated | Elevated CMOS |
US6010930A (en) * | 1996-01-22 | 2000-01-04 | Micron Technology Inc. | Vertically oriented structure with sloped opening and method for etching |
US5923980A (en) * | 1996-10-30 | 1999-07-13 | Advanced Micro Devices, Inc. | Trench transistor with localized source/drain regions implanted through voids in trench |
US6100146A (en) * | 1996-10-30 | 2000-08-08 | Advanced Micro Devices, Inc. | Method of forming trench transistor with insulative spacers |
US6191446B1 (en) * | 1998-03-04 | 2001-02-20 | Advanced Micro Devices, Inc. | Formation and control of a vertically oriented transistor channel length |
US6225161B1 (en) * | 1998-03-30 | 2001-05-01 | Advanced Micro Devices, Inc. | Fully recessed semiconductor method for low power applications with single wrap around buried drain region |
US5998267A (en) * | 1998-09-18 | 1999-12-07 | National Semiconductor Corporation | Process to manufacture high density ULSI ROM array |
US6077744A (en) * | 1999-02-22 | 2000-06-20 | Intersil Corporation | Semiconductor trench MOS devices |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050233541A1 (en) * | 2002-03-05 | 2005-10-20 | Samsung Electronics, Co., Ltd. | Semiconductor device having dual isolation structure and method of fabricating the same |
US7297604B2 (en) * | 2002-03-05 | 2007-11-20 | Samsung Electronics Co., Ltd. | Semiconductor device having dual isolation structure and method of fabricating the same |
US20090061584A1 (en) * | 2007-08-27 | 2009-03-05 | Wei-Chieh Lin | Semiconductor Process for Trench Power MOSFET |
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