US6366176B1 - Method and arrangement for generating a control signal - Google Patents
Method and arrangement for generating a control signal Download PDFInfo
- Publication number
- US6366176B1 US6366176B1 US09/939,637 US93963701A US6366176B1 US 6366176 B1 US6366176 B1 US 6366176B1 US 93963701 A US93963701 A US 93963701A US 6366176 B1 US6366176 B1 US 6366176B1
- Authority
- US
- United States
- Prior art keywords
- signal
- operating voltage
- converter
- control signal
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000005259 measurement Methods 0.000 claims abstract description 15
- 230000007423 decrease Effects 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000005070 sampling Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Definitions
- the invention relates to a method of generating a control signal, in which method the control signal is generated from a digital signal which is converted into an analog control signal in a D/A converter.
- control signal of a means controlled by an analog control signal is typically generated by converting the digital signal into an analog control signal.
- the means be for example a voltage-controlled oscillator
- the oscillator is controlled by an analog signal generated in a commercially available D/A converter.
- the D/A converter is coupled to a specific voltage reference, whereby the control voltage of the voltage-controlled means is rendered independent of variations in the operating voltage of the arrangement.
- the prior art arrangement cannot be integrated as such into a digital ASIC circuit, for example. If the above arrangement is integrated into an ASIC circuit, the operating voltage of the D/A converter could change under the influence of e.g. the load on the arrangement and the temperature. If the operating voltage of a D/A converter changes, the change may also cause a change in the magnitude of the control signal, and consequently the arrangement would not operate in the desired manner. In practice this means that the voltage-controlled oscillator does not provide the desired frequency, but the actual frequency differs from the desired frequency to some degree.
- the invention also relates to an arrangement comprising a D/A converter for receiving a digital signal and converting the received signal into an analog control signal.
- the arrangement of the invention is characterized by comprising a measuring means for measuring the operating voltage of the D/A converter, a means for generating a difference signal from the measurement result obtained from the measurement of the operating voltage, and the nominal value of the operating voltage, the difference signal being used to change the control signal when the operating voltage differs from a nominal value preset for the operating voltage of the D/A converter.
- the invention is based on taking into account the operating voltage of the D/A converter in the generation of the control signal, whereby a deviation of the operating voltage from the nominal value does not affect the control signal to be generated.
- the method and arrangement of the invention provide a plurality of advantages.
- the arrangement takes into account variations in the operating voltage during generation of the control signal, whereby the control signal is always optimal in size.
- a control signal thus generated ensures that the means to be controlled operates in the desired manner.
- the method of the invention is particularly efficient in compensating for slow variations in the operating voltage.
- FIG. 1 shows the arrangement of the invention
- FIG. 2 is a more detailed view of the arrangement of the invention.
- the arrangement comprises a measuring means 10 , a D/A converter 20 , a filter 30 and a means 40 to be controlled by a control signal.
- the means 40 to be controlled by the control signal may be for example a voltage-controlled oscillator. In some cases the means 40 may be controlled by current control.
- the figure shows that the D/A converter is disposed inside an ASIC circuit 70 . However, as to the functionality of the invention, the D/A converter 20 does not have to be disposed in an ASIC circuit.
- the D/A converter 20 can be implemented by e.g. a pulse width modulator.
- FIG. 2 is a more detailed view of the arrangement of the invention.
- FIG. 2 shows that the input side of the measuring means 10 is coupled to the D/A converter 20 .
- the figure shows that the output side of the measuring means is also coupled to the D/A converter.
- the measuring means 10 is coupled to measure the operating voltage (Vcc) of the D/A converter, the nominal magnitude of which may be +5V, for example.
- Vcc operating voltage
- the operating voltage of the D/A converter the nominal magnitude of which may be +5V, for example.
- the operating voltage of the D/A converter is not regulated, the operating voltage changes more easily from its predetermined nominal value, owing to variations in the load, for example.
- the measuring means 10 may be implemented for example by an A/D converter which takes samples intermittently from the operating voltage of the D/A converter.
- the D/A converter and the ASIC circuit may be coupled to the same operating voltage.
- the output side of the D/A converter 20 is coupled via the filter 30 to the means 40 .
- the arrangement also comprises an adder means 50 and a means 60 which in practice may be a microprocessor, for example.
- the input side of the adder means 50 is coupled to the means 60 and its output side to the D/A converter 20 .
- the output side of the measuring means is coupled to the means 60 .
- the arrangement operates as follows.
- the measuring means 10 is arranged to measure the operating voltage of the D/A converter 20 .
- the measuring means 10 may measure, not only the operating voltage of the D/A converter, but also that of other units in the arrangement.
- the measuring means may take for example analog samples from the operating voltage, which are converted into a digital signal in the measuring means.
- the measuring means 10 transmits the digital sample signals further to the means 60 which generates the actual measurement result from the sample signals.
- the means 60 generates a difference signal 61 using the voltage value obtained from the measurement, and the nominal value of the operating voltage.
- the means 60 generates the difference signal 61 for example by subtracting the nominal value of the operating voltage from the measurement result it generated.
- the difference signal may also be generated for example by subtracting the obtained measurement result from the nominal value of the operating voltage. If the voltage value measured is for example 5.1 V and the nominal value of the operating voltage 5.0 V, the difference signal is generated from a word corresponding to the voltage 0.1 V. Accordingly, the difference signal is used to change the control signal 41 in a direction which maintains as accurately as possible the frequency of the means to be controlled, such as an oscillator, at the value set. In the arrangement, a change in the operating voltage is compensated for in such a manner that the output voltage of the converter 20 is restored to the level on which it was before the change.
- the adder means 50 receives a digital signal 51 , which is used to generate the analog signal required in controlling the means 40 .
- the signal 51 is a digital word whose length affects the accuracy of the control signal. A long word gives a more accurate control signal to the means 40 than a short word.
- the difference signal is also applied to the adder means which adds the difference signal 61 to the signal 51 , generating a sum signal 52 .
- the sum signal generated by the adder means is converted into an analog signal which is applied to the filter 30 acting as a low-pass filter.
- FIG. 2 shows that at its simplest, the filter 30 is composed of a capacitor 31 and a resistor 32 . After the filtering, the sum signal serves as a control signal for the means 40 . If the means 40 is for example a voltage-controlled oscillator, the frequency of the oscillator will change as the magnitude of the control signal changes. The frequency of the oscillator will change for example when the voltage level of the control signal 41 changes.
- Adding the difference signal 61 generated by the means 60 to the digital signal 51 decreases or increases the signal 52 conveyed to the D/A converter.
- adding the difference signal 61 to the signal 51 increases the voltage of the control signal conveyed to the means 40 .
- the actual operating voltage of the D/A converter 20 exceeds the nominal value of the operating voltage of the D/A converter, then adding the difference signal 61 to the signal 51 decreases the voltage of the control signal conveyed to the means 40 .
- the difference signal can be negative when added to the signal 51 in the adder means.
- the adder means may also act as a subtractor, subtracting the difference signal from for example the signal 51 . The method disclosed may be used to prevent variations in the operating voltage from causing interference to the control signal.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI990571 | 1999-03-15 | ||
FI990571A FI106757B (en) | 1999-03-15 | 1999-03-15 | Method and apparatus for forming a control signal |
PCT/FI2000/000200 WO2000055972A1 (en) | 1999-03-15 | 2000-03-14 | Method and arrangement for generating a control signal |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FI2000/000200 Continuation WO2000055972A1 (en) | 1999-03-15 | 2000-03-14 | Method and arrangement for generating a control signal |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020030547A1 US20020030547A1 (en) | 2002-03-14 |
US6366176B1 true US6366176B1 (en) | 2002-04-02 |
Family
ID=8554196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/939,637 Expired - Lifetime US6366176B1 (en) | 1999-03-15 | 2001-08-28 | Method and arrangement for generating a control signal |
Country Status (4)
Country | Link |
---|---|
US (1) | US6366176B1 (en) |
AU (1) | AU3435000A (en) |
FI (1) | FI106757B (en) |
WO (1) | WO2000055972A1 (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0412491A2 (en) | 1989-08-10 | 1991-02-13 | Mitsubishi Denki Kabushiki Kaisha | Frequency Synthesizer |
US5072358A (en) | 1990-03-09 | 1991-12-10 | Daytronic Corporation | Process controller |
US5293166A (en) * | 1992-03-31 | 1994-03-08 | Vlsi Technology, Inc. | Digital-to-analog converter and bias compensator therefor |
US5477194A (en) | 1993-07-12 | 1995-12-19 | Nec Corporation | Temperature compensated PLL frequency synthesizer and high-speed frequency lock method using the same |
EP0735693A1 (en) | 1995-03-28 | 1996-10-02 | Nokia Mobile Phones Ltd. | A voltage controlled oscillator circuit |
EP0909036A1 (en) | 1997-10-07 | 1999-04-14 | Nec Corporation | Phase locked loop circuit |
US5977839A (en) | 1996-11-28 | 1999-11-02 | Nec Corporation | Compensated frequency source with latched temperature compensation, and method for it's control |
-
1999
- 1999-03-15 FI FI990571A patent/FI106757B/en active
-
2000
- 2000-03-14 WO PCT/FI2000/000200 patent/WO2000055972A1/en active Application Filing
- 2000-03-14 AU AU34350/00A patent/AU3435000A/en not_active Abandoned
-
2001
- 2001-08-28 US US09/939,637 patent/US6366176B1/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0412491A2 (en) | 1989-08-10 | 1991-02-13 | Mitsubishi Denki Kabushiki Kaisha | Frequency Synthesizer |
US5072358A (en) | 1990-03-09 | 1991-12-10 | Daytronic Corporation | Process controller |
US5293166A (en) * | 1992-03-31 | 1994-03-08 | Vlsi Technology, Inc. | Digital-to-analog converter and bias compensator therefor |
US5477194A (en) | 1993-07-12 | 1995-12-19 | Nec Corporation | Temperature compensated PLL frequency synthesizer and high-speed frequency lock method using the same |
EP0735693A1 (en) | 1995-03-28 | 1996-10-02 | Nokia Mobile Phones Ltd. | A voltage controlled oscillator circuit |
US5977839A (en) | 1996-11-28 | 1999-11-02 | Nec Corporation | Compensated frequency source with latched temperature compensation, and method for it's control |
EP0909036A1 (en) | 1997-10-07 | 1999-04-14 | Nec Corporation | Phase locked loop circuit |
Also Published As
Publication number | Publication date |
---|---|
FI106757B (en) | 2001-03-30 |
AU3435000A (en) | 2000-10-04 |
WO2000055972A1 (en) | 2000-09-21 |
US20020030547A1 (en) | 2002-03-14 |
FI990571A0 (en) | 1999-03-15 |
FI990571A (en) | 2000-09-16 |
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Owner name: NOKIA NETWORKS OY, FINLAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PELTOLA, SEPPO;REEL/FRAME:012126/0583 Effective date: 20010806 |
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FPAY | Fee payment |
Year of fee payment: 12 |
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AS | Assignment |
Owner name: NOKIA CORPORATION, FINLAND Free format text: MERGER;ASSIGNOR:NOKIA NETWORKS OY;REEL/FRAME:035789/0917 Effective date: 20070911 |
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AS | Assignment |
Owner name: NOKIA TECHNOLOGIES OY, FINLAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NOKIA CORPORATION;REEL/FRAME:035796/0819 Effective date: 20150116 Owner name: NOKIA CORPORATION, FINLAND Free format text: MERGER;ASSIGNOR:NOKIA NETWORKS OY;REEL/FRAME:035842/0359 Effective date: 20070911 |