US6284620B1 - Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components - Google Patents

Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components Download PDF

Info

Publication number
US6284620B1
US6284620B1 US09/688,466 US68846600A US6284620B1 US 6284620 B1 US6284620 B1 US 6284620B1 US 68846600 A US68846600 A US 68846600A US 6284620 B1 US6284620 B1 US 6284620B1
Authority
US
United States
Prior art keywords
trenches
epitaxial layer
layer
semiconductor
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US09/688,466
Inventor
Jenoe Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Siemens AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Assigned to SIEMENS AKTIENGESELLSCHAFT reassignment SIEMENS AKTIENGESELLSCHAFT ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TIHANYI, JENOE
Application granted granted Critical
Publication of US6284620B1 publication Critical patent/US6284620B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • First trenches are introduced into the at least one epitaxial layer and a marking groove is introduced through the at least one epitaxial layer.
  • the marking groove reaches the semiconductor substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components includes producing a semiconductor wafer from a semiconductor substrate, on one outer surface of which a plurality of epitaxial layers are provided. Trenches and a marking groove, which reaches the semiconductor substrate, are introduced into the epitaxial layers. A polycrystalline silicon layer, which is doped with a dopant of one conduction type, is deposited on the surface of the uppermost epitaxial layer, the trenches and the marking groove. The surface of the uppermost epitaxial layer, which is provided with the doped polycrystalline silicon layer, is direct-bonded with an outer surface of a further semiconductor wafer provided with an insulating layer. The semiconductor substrate is removed from its other outer surface. Further trenches are introduced into the lowermost epitaxial layer from the removed surface until the bottom of the trenches is reached. A further polycrystalline silicon layer, which is doped with a dopant of the first conduction type, is applied on the walls of the further trenches so as to produce continuous trenches. The continuous trenches are filled with insulating material.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of copending International Application No. PCT/DE99/00247, filed Jan. 29, 1999, which designated the United States.
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating an SOI (Silicon On Insulator) wafer for low-impedance high-voltage semiconductor components.
Dielectrically isolated (DI) epitaxial wafers are desirable for a variety of semiconductor components in order to ensure reliable insulation of adjacent components. Single-chip converters are one example thereof.
DI epitaxial wafers have been obtainable heretofore with a thickness of about 20 μm. However, epitaxial wafers which have a thickness exceeding 20 μm and, moreover, are dielectrically isolated would be advantageous for a wide variety of application purposes such as, by way of example, for obtaining a particularly high dielectric strength. Such DI epitaxial wafers are SOI wafers, for example, in which one or more epitaxial layers are applied on a substrate.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and in which the wafer has a layer thickness of more than 20 μm.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components, which is achieved through the use of the following steps:
(a) A first semiconductor wafer is produced from a semiconductor substrate, on one outer surface of which at least one epitaxial layer is provided.
(b) First trenches are introduced into the at least one epitaxial layer and a marking groove is introduced through the at least one epitaxial layer. The marking groove reaches the semiconductor substrate.
(c) A first layer, which is doped with a dopant of a first conduction type, is deposited on a surface of the at least one epitaxial layer, the first trenches and the marking groove.
(d) A first surface of the at least one epitaxial layer, which is provided with the doped first layer, is direct-bonded with an outer surface of a second semiconductor wafer. The outer surface of the second semiconductor wafer is provided with an insulating layer. The semiconductor substrate is removed from its other outer surface, which is opposite to the first surface, until the bottom of the marking groove is reached.
(e) Second trenches are introduced into the at least one epitaxial layer from the removed surface until the bottom of the first trenches is reached. A second layer, which is doped with a dopant of the first conduction type, is applied on walls of the second trenches so as to produce continuous trenches having walls that are provided with layers which are doped with dopant of the first conduction type.
(f) The continuous trenches are filled with insulating material.
In accordance with another mode of the invention, polycrystalline silicon which is heavily doped with dopant of the first conduction type is advantageously used for the first layer as well as for the second layer and thus for the layers which are doped with dopant of the first conduction type and are applied on the walls of the continuous trenches. However, instead of polycrystalline silicon, it is also possible to use monocrystalline silicon which is likewise heavily doped with dopant of the first conduction type.
In accordance with a further mode of the invention, the insulating material which fills the continuous trenches and, if appropriate, the marking groove as well, is preferably silicon dioxide. It goes without saying, however, that other insulating materials are also possible, such as, for example, silicon nitride or different layers made of silicon dioxide and/or silicon nitride.
In accordance with an added mode of the invention, it is particularly important that floating, island-like semiconductor regions of the second conduction type are introduced into the first semiconductor wafer made from the semiconductor substrate and the at least one epitaxial layer between the semiconductor substrate and the at least one epitaxial layer. If there is a plurality of epitaxial layers, such floating semiconductor regions of the other conduction type are also situated between the individual epitaxial layers. These floating regions may, if appropriate, also be connected in a grid-like manner.
The floating regions are preferably p-doped, so that the semiconductor substrate and the epitaxial layers are n-doped. The doping concentration of the floating regions is chosen to be high enough to ensure that the doping of the floating regions at least corresponds to the doping of the epitaxial layers or of the semiconductor substrate or else is higher than that doping.
In accordance with an additional mode of the invention, the doping per unit area in the floating regions is preferably above 1012 cm−2.
Due to the floating regions, the semiconductor substrate and the at least one epitaxial layer can be doped more heavily with dopant of the first conduction type, with the overall result that a low-impedance wafer is obtained. When a voltage is applied to the wafer, the space charge zone builds up firstly as far as the first plane of the floating regions, that is to say as far as the interface between the uppermost and second-uppermost epitaxial layer and then remains in this plane. This build up of space charge zones progresses from plane to plane, which means that overall, if there are three planes, for example, four times the dielectric strength of a semiconductor wafer without floating regions is achieved. A semiconductor wafer provided with such floating regions is thus particularly suitable for low-impedance high-voltage semiconductor components.
In accordance with yet another mode of the invention, instead of the floating regions, it is also possible, if appropriate, to use homogeneous epitaxial layers, if less value is placed on the dielectric strength given a low resistivity.
In accordance with a concomitant mode of the invention, if appropriate, in addition to the floating regions, trenches with a pn junction (“junction trench”) can also be introduced into the epitaxial layers, if the intention is to fabricate especially space-saving semiconductor components.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 to 3 are fragmentary, diagrammatic, sectional views of structures in which some hatching has been omitted for the sake of better clarity.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the figures of the drawings in detail and first, particularly, to FIG. 1 thereof, it is seen that the method according to the invention proceeds from a first silicon semiconductor wafer 1 having an n-conducting silicon substrate 2, onto which first, second and third n-conducting epitaxial layers 3, 4 and 5 are applied one after the other. Floating p-conducting regions 9 are situated between the epitaxial layers 3 and 4 as well as between the epitaxial layers 4 and 5. If appropriate, the regions 9 may also be connected in a grid-like manner. Such floating regions 9 may also be present between the substrate 2 and the epitaxial layer 3, although not shown in FIG. 1.
First trenches 6 as well as a marking groove 7 are introduced into the uppermost epitaxial layer 5. In this case, the bottom of the marking groove 7 reaches the silicon substrate 2.
The semiconductor regions 9 are preferably present. However, they need not be present, which means that overall there may be a homogeneous epitaxial structure present. If appropriate, even further trenches, into which pn junctions are introduced, may be present between the trenches 6, if the intention is to fabricate especially space-saving semiconductor components.
An n+-conducting polysilicon layer 8 is applied on the surface of the uppermost epitaxial layer 5, in the trenches 6 and in the marking groove 7. Instead of this polysilicon layer 8, an n+-doped silicon layer formed by diffusion may also be provided, if appropriate.
The structure shown in FIG. 1 is fabricated in a customary manner: initially the first epitaxial layer 3 is applied to the semiconductor substrate 2. The semiconductor regions 9 are then introduced into the surface of the epitaxial layer 3 by diffusion or ion implantation. The semiconductor regions 9 are doped oppositely to the epitaxial layer 3 or to the substrate 2. However, it should be expressly noted, that instead of the dopings specified, that is to say n conduction type for the semiconductor substrate 2 and the epitaxial layers 3, 4 and 5 and p conduction type for the semiconductor regions 9, the opposite conduction types can also be used in each case.
Afterwards, the second epitaxial layer 4 is then applied, which is followed by the introduction of the next plane of semiconductor regions 9. After the application of the uppermost or third epitaxial layer 5, the trenches 6 and the marking groove 7 are introduced by photoresist and etching technology. Finally, the polycrystalline silicon layer 8 is deposited.
Then, as is shown in FIG. 2, a second silicon wafer 10, which is furnished with a silicon dioxide layer 11, is applied by wafer bonding to the outer surface of the first semiconductor wafer 1. The outer surface of the first semiconductor wafer 1 is provided with the polysilicon layer 8. The semiconductor substrate 2 is then ground until the bottom 12 (indicated in FIG. 3) of the marking groove 7 has been reached. This produces the structure shown in FIG. 2.
As is shown in FIG. 3, second trenches 16 are then introduced from the side of the epitaxial layer 3. The trenches 16 reach the trenches 6. Walls of these trenches 16 are likewise provided with an n+-doped polycrystalline silicon layer 15. Instead of the polycrystalline silicon layer 15, n+-conducting layers may also be fabricated by diffusion, as was explained above for the layers 8.
Finally, the trenches 6, 16 as well as the marking groove 7 are filled with insulating material 14. This insulating material, preferably silicon dioxide and/or silicon nitride, is also applied to the surface of the epitaxial layer 3.
This produces the structure shown in FIG. 3, in which a “silicon island” including the epitaxial layers 5, 6 and 7 is completely embedded in insulating material including the insulator layer 11 and the insulating material 14 that fills the trenches 6, 16. By way of example, a field-effect transistor and/or an integrated circuit may then be introduced into this semiconductor island in a customary manner.
The layer thickness of the semiconductor wafer which is thus fabricated may be up to 40 μm, since the depth of the individual trenches 6, 16 may be about 20 μm in each case. It is thus possible, therefore, to fabricate DI epitaxial wafers, in a simple manner, which are distinguished by a relatively large layer thickness of up to 40 μm. These epitaxial wafers, if they are specifically furnished with the semiconductor regions 9, are particularly suitable for low-impedance high-voltage semiconductor components.
The method according to the invention therefore makes it possible to fabricate an SOI wafer which is excellently matched to the requirements of low-impedance high-voltage semiconductor components with regard to its doping and its layer thickness.

Claims (9)

I claim:
1. A method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components, which comprises the following steps:
(a) producing a first semiconductor wafer from a semiconductor substrate having an outer surface, providing at least one epitaxial layer having first and second mutually opposite outer surfaces, and placing the second outer surface of the at least one epitaxial layer on the outer surface of the semiconductor substrate;
(b) introducing first trenches into the at least one epitaxial layer and introducing a marking groove through the at least one epitaxial layer to reach the semiconductor substrate;
(c) depositing a first layer, doped with a dopant of a first conduction type, on the first outer surface of the at least one epitaxial layer, the first trenches and the marking groove;
(d) providing a second semiconductor wafer having an outer surface, and placing an insulating layer on the outer surface of the second semiconductor wafer;
(e) direct-bonding the first outer surface of the at least one epitaxial layer, provided with the first doped layer, to the outer surface of the second semiconductor wafer having the insulating layer;
(f) removing the semiconductor substrate from the second outer surface of the at least one epitaxial layer until reaching a bottom of the marking groove;
(g) introducing second trenches from the second outer surface of the at least one epitaxial layer until reaching a bottom of the first trenches, and applying a second layer, doped with the dopant of the first conduction type, on walls of the second trenches to produce continuous trenches having walls provided with layers doped with the dopant of the first conduction type; and
(h) filling the continuous trenches with insulating material.
2. The method according to claim 1, which further comprises using polycrystalline silicon heavily doped with the dopant of the first conduction type for at least one of the first and second layers.
3. The method according to claim 1, which further comprises using silicon doped with the dopant of the first conduction type for at least one of the first and second layers.
4. The method according to claim 1, which further comprises carrying out the step of introducing each of the first and second trenches to a depth of about 20 μm.
5. The method according to claim 1, which further comprises introducing floating semiconductor regions of a second conduction type between the semiconductor substrate and each of the at least one epitaxial layer.
6. The method according to claim 5, which further comprises providing the floating semiconductor regions with a doping per unit area of above 1012 cm−2.
7. The method according to claim 5, which further comprises carrying out the step of introducing the floating regions in a grid-like manner.
8. The method according to claim 5, which further comprises carrying out the step of introducing the floating semiconductor regions by diffusion.
9. The method according to claim 5, which further comprises carrying out the step of introducing the floating semiconductor regions by ion implantation.
US09/688,466 1998-04-14 2000-10-16 Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components Expired - Fee Related US6284620B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19816449 1998-04-14
DE19816449A DE19816449C2 (en) 1998-04-14 1998-04-14 Method for producing an SOI wafer for low-resistance high-voltage semiconductor components
PCT/DE1999/000247 WO1999053541A1 (en) 1998-04-14 1999-01-29 Method for producing an soi (silicon on insulator) wafer for low-impedance high-voltage semiconductor components

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/000247 Continuation WO1999053541A1 (en) 1998-04-14 1999-01-29 Method for producing an soi (silicon on insulator) wafer for low-impedance high-voltage semiconductor components

Publications (1)

Publication Number Publication Date
US6284620B1 true US6284620B1 (en) 2001-09-04

Family

ID=7864451

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/688,466 Expired - Fee Related US6284620B1 (en) 1998-04-14 2000-10-16 Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components

Country Status (5)

Country Link
US (1) US6284620B1 (en)
EP (1) EP1074044A1 (en)
JP (1) JP2002511653A (en)
DE (1) DE19816449C2 (en)
WO (1) WO1999053541A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19816449C2 (en) 1998-04-14 2000-10-26 Siemens Ag Method for producing an SOI wafer for low-resistance high-voltage semiconductor components

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61182242A (en) 1985-02-08 1986-08-14 Toshiba Corp Manufacturing method of semiconductor device
JPH04348544A (en) 1991-05-27 1992-12-03 Fujitsu Ltd Manufacture of semiconductor device
US5700712A (en) 1993-06-23 1997-12-23 Siemens Aktiengesellschaft Method for manufacturing an insulating trench in an SOI substrate for smartpower technologies
US5952694A (en) * 1991-11-20 1999-09-14 Canon Kabushiki Kaisha Semiconductor device made using processing from both sides of a workpiece
DE19816449A1 (en) 1998-04-14 1999-10-28 Siemens Ag Method for producing an SOI wafer for low-resistance high-voltage semiconductor components

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59711481D1 (en) * 1996-02-05 2004-05-06 Infineon Technologies Ag Semiconductor component controllable by field effect

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61182242A (en) 1985-02-08 1986-08-14 Toshiba Corp Manufacturing method of semiconductor device
JPH04348544A (en) 1991-05-27 1992-12-03 Fujitsu Ltd Manufacture of semiconductor device
US5952694A (en) * 1991-11-20 1999-09-14 Canon Kabushiki Kaisha Semiconductor device made using processing from both sides of a workpiece
US5700712A (en) 1993-06-23 1997-12-23 Siemens Aktiengesellschaft Method for manufacturing an insulating trench in an SOI substrate for smartpower technologies
DE19816449A1 (en) 1998-04-14 1999-10-28 Siemens Ag Method for producing an SOI wafer for low-resistance high-voltage semiconductor components

Also Published As

Publication number Publication date
DE19816449A1 (en) 1999-10-28
JP2002511653A (en) 2002-04-16
DE19816449C2 (en) 2000-10-26
WO1999053541A1 (en) 1999-10-21
EP1074044A1 (en) 2001-02-07

Similar Documents

Publication Publication Date Title
US6465869B2 (en) Compensation component and process for producing the compensation component
US9396997B2 (en) Method for producing a semiconductor component with insulated semiconductor mesas
US8022501B2 (en) Semiconductor device and method for isolating the same
US8237221B2 (en) Semiconductor device and method of manufacturing semiconductor device
KR900002885B1 (en) Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
US3931674A (en) Self aligned CCD element including two levels of electrodes and method of manufacture therefor
US7906388B2 (en) Semiconductor device and method for manufacture
JP5089163B2 (en) Area-efficient gated diode structure and method of forming the same
EP0615286B1 (en) Semiconductor device provided with isolation region
KR101915627B1 (en) Thyristor random access memory device and method
CN1783452A (en) Method for forming silicon lining bottom on pattern insulator
JPH05267439A (en) Manufacture of semiconductor device
CN114464675A (en) Composite gate IGBT device structure and preparation method thereof
US8110455B2 (en) Semiconductor device and a method of manufacturing the same
US6284620B1 (en) Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components
JPH02285642A (en) Dielectric isolation semiconductor device and its manufacture
JP2024527641A (en) Semiconductor structure and method of manufacture thereof
US5616512A (en) Power semiconductor devices
US20120161276A1 (en) Semiconductor device comprising an isolation trench including semiconductor islands
US6693019B2 (en) Method of manufacturing an electronic power device monolithically integrated on a semiconductor and comprising a first power region, a second region, and an isolation structure of limited planar dimension
JPH05144930A (en) Semiconductor device
US20250006744A1 (en) Semiconductor structure
JP2701881B2 (en) Semiconductor isolation region
JP2980332B2 (en) Dielectric separation substrate, semiconductor device using the same, and method of manufacturing dielectric separation substrate
JPS61225866A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SIEMENS AKTIENGESELLSCHAFT, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TIHANYI, JENOE;REEL/FRAME:011493/0049

Effective date: 20001025

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20050904