US6207559B1 - Method of making a semiconductor device for attachment to a semiconductor substrate - Google Patents
Method of making a semiconductor device for attachment to a semiconductor substrate Download PDFInfo
- Publication number
- US6207559B1 US6207559B1 US09/196,566 US19656698A US6207559B1 US 6207559 B1 US6207559 B1 US 6207559B1 US 19656698 A US19656698 A US 19656698A US 6207559 B1 US6207559 B1 US 6207559B1
- Authority
- US
- United States
- Prior art keywords
- layer
- metal
- forming
- diffusion barrier
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81026—Applying a precursor material to the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01011—Sodium [Na]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the present invention is directed to an electrical interconnection for attachment to a substrate. More specifically, the present invention is directed to an electrical interconnection between a contact area of a substrate and a contact area of a die and a method of forming the same.
- Integrated circuits have for years been universally used in computer applications, as well as other high-tech applications such as communications and military technologies.
- a primary concern with integrated circuits has long been the electrical interconnection between the bond pad of a die and the bond pad of a semiconductive substrate.
- semiconductive substrate is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials.
- substrate refers to any supporting structure including but not limited to the semiconductor substrates described above.
- the term “die” is defined as a chip or other electronic component part, either passive or active, discrete or integrated.
- Bond pads have typically been used to provide electrically conductive metal contact areas on semiconductor substrates in integrated circuits. Bond pads used in integrated circuits have historically been composed of an aluminum-copper alloy, wherein the copper typically comprises less than about 0.5% of the alloy. Aluminum is an excellent metal for bond pad formation due to its superior adhesion qualities, high thermal stability, and ease of workability (i.e., in etching processes). Although aluminum bond pads are the semiconductor industry standard, aluminum readily oxidizes, even at room temperature, to form aluminum oxide (Al 2 O 3 ). Oxides of conductive metals, whether it be aluminum, copper or other conductive metals, sharply increase the contact resistance of the metal and decrease the electrical connection and the efficiency of the bond pad. Hence, while aluminum bond pads exhibit excellent electrical conductivity, unprotected aluminum bond pads readily react to form aluminum oxide which exhibits very high contact resistance and results in a poor interconnection between the bond pad of a die and the bond pad of a substrate.
- the zincate process activates the aluminum bond pads using a “zincate solution” and then deposits a layer of nickel and a layer of gold on the bond pad to preserve the electrical connection.
- the zincate solution consisting of zinc oxide and sodium hydroxide, dissolves an aluminum oxide formed on the aluminum bond pad to clean the same, and also deposits a thin layer of zinc over the clean aluminum bond pad.
- a thin nickel phosphorous barrier layer is then deposited over the zinc.
- a layer of gold is added to the surface of the nickel phosphorous layer to provide an oxide free surface.
- an electrical interconnection for attachment to a substrate and a method for forming an electrical interconnection to a substrate.
- the electrical interconnection in the present invention comprises a first metal layer, a first diffusion barrier layer on the first metal layer, a second metal layer on the first diffusion barrier layer, an organometallic layer on the second metal layer, and an electrical interconnect layer on the organometallic layer.
- a first diffusion barrier layer is formed on the first metal layer.
- the first diffusion barrier layer prevents diffusion of the first metal layer and the second metal layer therethrough.
- the first metal layer is composed of aluminum and the second metal layer is composed of copper.
- the first diffusion barrier layer prevents the aluminum and the copper from diffusing and adversely effecting the electrical interconnection.
- the organometallic layer is preferably formed by contacting the second metal layer with an organic material to form an organometallic layer.
- the organometallic layer formed is preferably a copper azole such as Cu + (azole ⁇ ) and Cu ++ (azole ⁇ ) 2 ).
- the organometallic layer prevents oxidation of the second metal layer which is preferably copper.
- the electrical interconnection device of the present invention may be combined with an additional substrate to form an electrical interconnection between a first substrate and a second substrate, for example, as in an integrated circuit.
- the electrical interconnect of the present invention has a low contact resistance and creates a good electrical interconnect to bond a die to another substrate, such as a supporting substrate.
- FIG. 1A is cross sectional view of a supporting substrate having a circuit trace.
- FIG. 1B is cross sectional view of an electrical interconnect on a die substrate.
- FIG. 1C is cross sectional view of an electrical interconnect on a die substrate, wherein a first metal layer includes a second diffusion layer on a first substrate.
- FIG. 2 is cross sectional view of an electronic structure, such as an electronic memory structure including an electrical interconnect between an electric circuit and a supporting substrate.
- First and second substrates 12 , 26 are illustrated respectively in FIG. 2 and FIGS. 1A-1C.
- Second substrate 26 is also referred to herein as a supporting substrate.
- FIG. 1B illustrates first substrate 12 , which can include a chip or die, as having an electrical interconnection 36 affixed thereto.
- Second substrate 26 typically includes or has fabricated thereon electrical circuitry structures.
- Second substrate 26 is fabricated to have a circuit trace 30 .
- Circuit trace 30 may be fabricated using any circuit trace technology known in the art, including, but not limited to, copper, aluminum, and printed polymer thick film (copper, silver, or carbon) technologies.
- a portion of circuit trace 30 is an electrical contact area 34 , such as a bond pad.
- First substrate 12 has thereon a masking or passivation layer 38 to protect the same from the ambient.
- First metal layer 16 is on first substrate 12 and is composed of a first metal.
- a first diffusion barrier layer 32 is on first metal layer 16
- a second metal layer 18 composed of a second metal is on first diffusion barrier layer 32 .
- First diffusion barrier layer 32 prevents diffusion therethrough of either the first metal or the second metal.
- An organometallic layer 20 is on second metal layer 18
- an electrical interconnect layer 22 is on organometallic layer 20 .
- First substrate 12 may be any supporting structure, including but not limited to a semiconductor substrate. In one embodiment of the present invention, first substrate 12 is a die pad.
- First metal layer 16 on first substrate 12 is formed to have an electrical contact area comprising a conducting metal.
- the electrical contact area is also referred to herein as a bond pad.
- First metal layer 16 can be formed from any conductive metal, including but :to limited to aluminum, copper or an aluminum copper alloy.
- First metal layer 16 is preferably composed of aluminum.
- first metal layer 16 is upon and in contact with a second diffusion barrier layer 14 that is upon and in contact with first substrate 12 .
- Second diffusion barrier layer 14 is preferably composed of titanium but can be composed of any material that prevents diffusion therethrough from either first metal layer 16 or first substrate 12 .
- Second metal layer 18 on first diffusion barrier layer 32 is an electrical conductive metal layer that can be formed from any conductive metal, including but not limited to copper.
- Second metal layer 18 is formed using any method known in the art, including but not limited to, deposition and photoresistive masking, where the deposition is a method such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and molecular beam epitaxy.
- Second metal layer 18 is preferably deposited in a vacuum or an inert atmosphere, such as a nitrogen atmosphere, to prevent oxidation of the deposited metal.
- Second metal layer 18 can have any thickness suitable for use with an electrical interconnection and preferably has a thickness in a range from about 10 nm to about 10 microns.
- First diffusion barrier layer 32 situated on first metal layer 16 and below second metal layer 18 , is composed of any type of metal that prevents diffusion therethrough of the metal of either first metal layer 16 or second metal layer 18 .
- the composition of first diffusion barrier layer 32 depends on the compositions of first metal layer 16 and second metal layer 18 .
- first metal layer 16 is composed of aluminum
- second metal layer 18 is composed of copper
- first diffusion barrier layer 32 is a metal selected from the group consisting of nickel (Ni), a refractory metal nitride and a refractory metal such as tungsten. More preferably, first diffusion barrier layer 32 is selectd from the group consisting of titanium tungsten (TiW), titanium nitride (TiN), and nickel (Ni).
- Organometallic layer 20 provides mechanical and chemical protection for second metal layer 18 . More particularly, a function of organometallic layer 20 is to prevent contamination of second metal layer 18 . An additional related function of organometallic layer 20 is to function as a hydrophobic passivation layer preventing corrosion and oxidation of second metal layer 18 .
- Organometallic layer 20 is composed of a metal azole complex, preferably comprising the metal of second metal layer 18 and an azole selected from the group consisting of benzimidazole, 2-methylbenzimidazole, benzotriazole (BTA) and benzotriazole derivatives, such as 5-methylbenzotriazole and 1-methylbenzotriazole, to form organometallic complexes having the general formula M + (azole ⁇ ) and M ++ (azole ⁇ ) 2 , depending on the valence of the metal, wherein M represents the metal and the azole is an organic ligand.
- a metal azole complex preferably comprising the metal of second metal layer 18 and an azole selected from the group consisting of benzimidazole, 2-methylbenzimidazole, benzotriazole (BTA) and benzotriazole derivatives, such as 5-methylbenzotriazole and 1-methylbenzotriazole, to form organometallic complexes having the general formula M + (
- the metal in organometallic layer 20 is formed from second metal layer 18 , which is preferably copper, and an organic material, preferably benzotriazole (BTA) or a benzotriazole derivative.
- BTA benzotriazole
- organometallic layer 20 is composed of Cu + (BTA ⁇ ) and Cu ++ (BTA ⁇ ) 2 , depending on the valence of the copper.
- organometallic layer 20 has a thickness of below about 30 Angstroms yet thick enough to effectively protect, both physically and chemically, second metal layer 18 .
- Electrical interconnect layer 22 is on organometallic layer 20 and provides electrical contact therewith. When combined with second substrate 26 seen in FIG. 1A, electrical interconnect layer 22 provides an electrical interconnection between an intended electrical contact area of first substrate 12 and an intended electrical contact area of second substrate 26 .
- electrical interconnect layer 22 provides an electrical interconnection between contact area 34 of first substrate 12 and a contact area on first metal layer 16 of second substrate 26 .
- Electrical interconnect layer 22 can be any electrical conducting material, including but not limited to electrically conductive material that is formed into epoxy bumps or solder connects as is known in the semiconductor chip packaging arts. Epoxy bumps can be formed by any known process commonly used in the art and can be made from any type of base resin material that is compatible with the electrical interconnect.
- the base resin material in electrical interconnect layer 22 farther comprises electrical conducting particles, including but not limited to silver particles and preferably nickel particles. Solder interconnects are well-known in the art and any compatible solder can be used to form electrical interconnect layer 22 .
- Electrical interconnect layer 22 can be combined with the second substrate 26 , also referred to herein as supporting substrate 26 , having circuit trace 30 to form a memory module 50 as illustrated in FIG. 2 .
- Contact area 34 also referred to as a third metal layer 34 , on supporting substrate 26 is aligned with first metal layer 16 .
- first substrate 12 represent a structure including a memory device, such as a ROM, RAM, DRAM, and other such memory devices, as are embodied in a chip or die.
- FIG. 2 be representative of the combined structures illustrate in FIG. 1A with either FIG. 1B or FIG. 1 C.
- As such structure 19 in FIG. 2 is intended to be a layered structure combining combination of first metal layer 16 upon second diffusion barrier layer 14 which is upon first substrate 12 .
- Electrical interconnect layer 22 is interposed between first and second substrates 12 , 26 .
- a small amount of a wet epoxy such as conductive epoxy, is added to contact area 34 to combine supporting substrate 26 with the multiple layers upon first substrate 12 .
- the conductive adhesive is cured so as to affix together first and second substrates 12 , 26 .
- a thermoplastic or epoxy is applied to third metal layer 34 or contact area 34 .
- Second substrate 26 is then attached to first substrate 12 by application of pressure and heat. A wire bond may then be used to electrically connect second substrate 26 to an external electrical connection.
- Third metal layer 34 or contact area 34 on second substrate 26 can be a die pond pad, and is preferably composed of any conducting metal, including but not limited to aluminum, copper, and aluminum copper alloys. As shown, electrical interconnect layer 22 is in contact with third metal layer 34 or contact area 34 .
- a method of forming an electrical interconnection to first substrate 12 comprises providing first metal layer 16 on first substrate 12 .
- First metal layer 16 is composed of a first metal, which is preferably electrically conductive, such as aluminum, copper, or an aluminum copper alloy.
- First metal layer 16 is an electrical contact area, also referred to as a bond pad.
- first metal layer 16 is composed of aluminum.
- Conductive metals used to form first metal layer 16 typically oxidize in ambient conditions. As mentioned above, oxidized metal, such as aluminum oxide, increases contact resistance and adversely effects the electrical connection of associated electrical contact areas.
- the method may also include forming second diffusion barrier layer 14 upon and in contact with first substrate 12 , and then forming first metal layer 16 upon and in contact with second barrier layer 14 .
- the present method includes removing the metal oxide from first metal layer 16 .
- the method comprises removing the aluminum oxide formed on first metal layer 16 .
- the metal oxide can be removed by any standard method known in the art, including but not limited to a wet etch method, reactive ion etching (including plasma enhanced reactive ion etching) and mechanical abrasion. Oxide removal is preferably performed in an inert atmosphere to avoid further oxidation.
- first diffusion barrier layer 32 is formed on a cleaned surface of first metal layer 16 .
- first diffusion barrier layer 32 After forming first diffusion barrier layer 32 on first metal layer 16 , a second metal layer 18 is formed on first diffusion barrier layer 32 using any known method, including but not limited to photoresistive masking and deposition processes such as physical vapor deposition, chemical vapor deposition, and molecular beam epitaxy. Diffusion barrier layer 32 prevents diffusion therethrough of either the first metal of first metal layer 16 or the second metal of second metal layer 18 . Second metal layer 18 is preferably deposited in a vacuum or an inert atmosphere, such as a nitrogen environment, to prevent oxidation of second metal layer 18 .
- organometallic layer 20 is formed on second metal layer 18 by contacting a metal with an azole that readily reacts with second metal layer 18 .
- Organometallic layer 20 typically has the formula M + (azole ⁇ ), M ++ (azole ⁇ ) 2 .
- organometallic layer 20 is formed on second metal layer 18 by immersing second metal layer 18 in a solution comprising an azole in a non-corrosive solution to form organometallic layer 20 .
- a copper second metal layer 18 can be immersed in a 2% benzotriazole (BTA) ethanol solution at 50 ° C. for about five minutes in an inert environment to form a thin layer of the organometallic material, Cu + (BTA ⁇ ) and Cu ++ (BTA ⁇ ) 2 .
- BTA benzotriazole
- organometallic layers formed from copper and azoles examples of processes for forming organometallic can be found in The Interaction of Imidazole Benzimidazole and Related Azoles with a Copper Surface, H. G. Tompkins et al., Surface and Interface Analysis, Vol. 4, No. 6, 1982; Coordination Polymerization of Benzotriazcle on the Surface of Metallic Copper, Gi Xue et al., Chinese Journal of Polymer Science, Vol. 7, No. 3, 1989; and Correlation of Surface Wettability and Corrosion Rate for Benzotriazole-Treated Copper, Richard R. Thomas et al., The Electrochemical Society, Inc., Vol. 139, No. 3,March 1992, which are herein incorporated by reference.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (46)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/196,566 US6207559B1 (en) | 1997-12-16 | 1998-11-20 | Method of making a semiconductor device for attachment to a semiconductor substrate |
US09/817,877 US6566253B2 (en) | 1997-12-16 | 2001-03-26 | Method of making electrical interconnection for attachment to a substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/991,891 US6051879A (en) | 1997-12-16 | 1997-12-16 | Electrical interconnection for attachment to a substrate |
US09/196,566 US6207559B1 (en) | 1997-12-16 | 1998-11-20 | Method of making a semiconductor device for attachment to a semiconductor substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/991,891 Division US6051879A (en) | 1997-12-16 | 1997-12-16 | Electrical interconnection for attachment to a substrate |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/817,877 Continuation US6566253B2 (en) | 1997-12-16 | 2001-03-26 | Method of making electrical interconnection for attachment to a substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
US6207559B1 true US6207559B1 (en) | 2001-03-27 |
Family
ID=25537690
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/991,891 Expired - Lifetime US6051879A (en) | 1997-12-16 | 1997-12-16 | Electrical interconnection for attachment to a substrate |
US09/196,566 Expired - Lifetime US6207559B1 (en) | 1997-12-16 | 1998-11-20 | Method of making a semiconductor device for attachment to a semiconductor substrate |
US09/516,047 Expired - Lifetime US6380626B1 (en) | 1997-12-16 | 2000-03-01 | Semiconductor device for attachment to a semiconductor substrate |
US09/817,877 Expired - Lifetime US6566253B2 (en) | 1997-12-16 | 2001-03-26 | Method of making electrical interconnection for attachment to a substrate |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/991,891 Expired - Lifetime US6051879A (en) | 1997-12-16 | 1997-12-16 | Electrical interconnection for attachment to a substrate |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/516,047 Expired - Lifetime US6380626B1 (en) | 1997-12-16 | 2000-03-01 | Semiconductor device for attachment to a semiconductor substrate |
US09/817,877 Expired - Lifetime US6566253B2 (en) | 1997-12-16 | 2001-03-26 | Method of making electrical interconnection for attachment to a substrate |
Country Status (1)
Country | Link |
---|---|
US (4) | US6051879A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6595404B2 (en) * | 2000-01-13 | 2003-07-22 | Hitachi, Ltd. | Method of producing electronic part with bumps and method of producing electronic part |
US6610601B2 (en) * | 1999-03-31 | 2003-08-26 | Lam Research Corporation | Bond pad and wire bond |
US6825120B1 (en) | 2002-06-21 | 2004-11-30 | Taiwan Semiconductor Manufacturing Company | Metal surface and film protection method to prolong Q-time after metal deposition |
US20040242116A1 (en) * | 2001-12-20 | 2004-12-02 | Stephen Forrest | Organic optoelectronic device structures |
US20050205522A1 (en) * | 2000-03-03 | 2005-09-22 | Chartered Semiconductor Manufacturing Ltd. | Chemical agent additives in copper CMP slurry |
US20160043034A1 (en) * | 2014-08-07 | 2016-02-11 | Infineon Technologies Ag | Device and method for manufacturing a device |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6082610A (en) * | 1997-06-23 | 2000-07-04 | Ford Motor Company | Method of forming interconnections on electronic modules |
US6051879A (en) * | 1997-12-16 | 2000-04-18 | Micron Technology, Inc. | Electrical interconnection for attachment to a substrate |
EP1154471B1 (en) * | 1998-09-30 | 2008-07-16 | Ibiden Co., Ltd. | Semiconductor chip with bump contacts |
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US6230400B1 (en) * | 1999-09-17 | 2001-05-15 | George Tzanavaras | Method for forming interconnects |
JP2001118927A (en) * | 1999-10-22 | 2001-04-27 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method therefor |
JP2003037133A (en) * | 2001-07-25 | 2003-02-07 | Hitachi Ltd | Semiconductor device, method of manufacturing the same, and electronic device |
US20040069651A1 (en) * | 2002-10-15 | 2004-04-15 | Applied Materials, Inc. | Oxide treatment and pressure control for electrodeposition |
MY134318A (en) * | 2003-04-02 | 2007-12-31 | Freescale Semiconductor Inc | Integrated circuit die having a copper contact and method therefor |
US7459790B2 (en) * | 2003-10-15 | 2008-12-02 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
DE10357673A1 (en) * | 2003-12-09 | 2005-07-28 | Infineon Technologies Ag | Mounting and adhesive layer for semiconductor device |
US7279407B2 (en) | 2004-09-02 | 2007-10-09 | Micron Technology, Inc. | Selective nickel plating of aluminum, copper, and tungsten structures |
JP4882229B2 (en) * | 2004-09-08 | 2012-02-22 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
US7307321B1 (en) * | 2005-03-25 | 2007-12-11 | Spansion Llc | Memory device with improved data retention |
US20100101840A1 (en) * | 2008-10-29 | 2010-04-29 | Raytheon Company | Application of a self-assembled monolayer as an oxide inhibitor |
US20100120242A1 (en) * | 2008-11-07 | 2010-05-13 | Texas Instruments Incorporated | Method to prevent localized electrical open cu leads in vlsi cu interconnects |
US8535999B2 (en) | 2010-10-12 | 2013-09-17 | International Business Machines Corporation | Stress memorization process improvement for improved technology performance |
JP5812090B2 (en) * | 2011-03-10 | 2015-11-11 | 富士電機株式会社 | Electronic component and method for manufacturing electronic component |
KR20130007124A (en) * | 2011-06-29 | 2013-01-18 | 삼성전자주식회사 | Joint structure having an organic preservative film |
KR102036942B1 (en) | 2012-02-24 | 2019-10-25 | 스카이워크스 솔루션즈, 인코포레이티드 | Improved structures, devices and methods related to copper interconnects for compound semiconductors |
US9558859B2 (en) * | 2014-02-18 | 2017-01-31 | Rsm Electron Power, Inc. | Multilayer substrate and method for manufacturing the same |
WO2016137452A1 (en) * | 2015-02-25 | 2016-09-01 | Intel Corporation | Surface finishes for interconnection pads in microelectronic structures |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3106489A (en) | 1960-12-09 | 1963-10-08 | Bell Telephone Labor Inc | Semiconductor device fabrication |
WO1986001640A1 (en) | 1984-08-27 | 1986-03-13 | American Telephone & Telegraph Company | Diffusion barrier layer for integrated-circuit devices |
US4598022A (en) * | 1983-11-22 | 1986-07-01 | Olin Corporation | One-step plasma treatment of copper foils to increase their laminate adhesion |
JPH01145856A (en) | 1987-12-02 | 1989-06-07 | Hitachi Ltd | Electrode for compound semiconductor |
JPH02235372A (en) | 1989-03-08 | 1990-09-18 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
JPH0427163A (en) | 1990-05-23 | 1992-01-30 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPH0574959A (en) | 1991-09-18 | 1993-03-26 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPH065599A (en) | 1992-06-22 | 1994-01-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US5583073A (en) * | 1995-01-05 | 1996-12-10 | National Science Council | Method for producing electroless barrier layer and solder bump on chip |
US5629564A (en) | 1994-06-28 | 1997-05-13 | International Business Machines Corporation | Electroplated solder terminal |
US5656858A (en) | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
US5708302A (en) | 1995-04-26 | 1998-01-13 | Symetrix Corporation | Bottom electrode structure for dielectric capacitors |
US5844318A (en) * | 1997-02-18 | 1998-12-01 | Micron Technology, Inc. | Aluminum film for semiconductive devices |
US5960251A (en) * | 1996-04-18 | 1999-09-28 | International Business Machines Corporation | Organic-metallic composite coating for copper surface protection |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5074947A (en) * | 1989-12-18 | 1991-12-24 | Epoxy Technology, Inc. | Flip chip technology using electrically conductive polymers and dielectrics |
TW347149U (en) * | 1993-02-26 | 1998-12-01 | Dow Corning | Integrated circuits protected from the environment by ceramic and barrier metal layers |
US5480834A (en) * | 1993-12-13 | 1996-01-02 | Micron Communications, Inc. | Process of manufacturing an electrical bonding interconnect having a metal bond pad portion and having a conductive epoxy portion comprising an oxide reducing agent |
US6051879A (en) * | 1997-12-16 | 2000-04-18 | Micron Technology, Inc. | Electrical interconnection for attachment to a substrate |
-
1997
- 1997-12-16 US US08/991,891 patent/US6051879A/en not_active Expired - Lifetime
-
1998
- 1998-11-20 US US09/196,566 patent/US6207559B1/en not_active Expired - Lifetime
-
2000
- 2000-03-01 US US09/516,047 patent/US6380626B1/en not_active Expired - Lifetime
-
2001
- 2001-03-26 US US09/817,877 patent/US6566253B2/en not_active Expired - Lifetime
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3106489A (en) | 1960-12-09 | 1963-10-08 | Bell Telephone Labor Inc | Semiconductor device fabrication |
US4598022A (en) * | 1983-11-22 | 1986-07-01 | Olin Corporation | One-step plasma treatment of copper foils to increase their laminate adhesion |
WO1986001640A1 (en) | 1984-08-27 | 1986-03-13 | American Telephone & Telegraph Company | Diffusion barrier layer for integrated-circuit devices |
JPH01145856A (en) | 1987-12-02 | 1989-06-07 | Hitachi Ltd | Electrode for compound semiconductor |
JPH02235372A (en) | 1989-03-08 | 1990-09-18 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
JPH0427163A (en) | 1990-05-23 | 1992-01-30 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPH0574959A (en) | 1991-09-18 | 1993-03-26 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPH065599A (en) | 1992-06-22 | 1994-01-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US5629564A (en) | 1994-06-28 | 1997-05-13 | International Business Machines Corporation | Electroplated solder terminal |
US5656858A (en) | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
US5583073A (en) * | 1995-01-05 | 1996-12-10 | National Science Council | Method for producing electroless barrier layer and solder bump on chip |
US5708302A (en) | 1995-04-26 | 1998-01-13 | Symetrix Corporation | Bottom electrode structure for dielectric capacitors |
US5960251A (en) * | 1996-04-18 | 1999-09-28 | International Business Machines Corporation | Organic-metallic composite coating for copper surface protection |
US5844318A (en) * | 1997-02-18 | 1998-12-01 | Micron Technology, Inc. | Aluminum film for semiconductive devices |
US5963835A (en) * | 1997-02-18 | 1999-10-05 | Micron Technology Inc. | Method of forming aluminum film |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6610601B2 (en) * | 1999-03-31 | 2003-08-26 | Lam Research Corporation | Bond pad and wire bond |
US6595404B2 (en) * | 2000-01-13 | 2003-07-22 | Hitachi, Ltd. | Method of producing electronic part with bumps and method of producing electronic part |
US6695200B2 (en) | 2000-01-13 | 2004-02-24 | Hitachi, Ltd. | Method of producing electronic part with bumps and method of producing electronic part |
US20050205522A1 (en) * | 2000-03-03 | 2005-09-22 | Chartered Semiconductor Manufacturing Ltd. | Chemical agent additives in copper CMP slurry |
US20040242116A1 (en) * | 2001-12-20 | 2004-12-02 | Stephen Forrest | Organic optoelectronic device structures |
US7002294B2 (en) * | 2001-12-20 | 2006-02-21 | Universal Display Corporation | Method of protecting organic optoelectronic devices |
US6825120B1 (en) | 2002-06-21 | 2004-11-30 | Taiwan Semiconductor Manufacturing Company | Metal surface and film protection method to prolong Q-time after metal deposition |
US20160043034A1 (en) * | 2014-08-07 | 2016-02-11 | Infineon Technologies Ag | Device and method for manufacturing a device |
CN105374855A (en) * | 2014-08-07 | 2016-03-02 | 英飞凌科技股份有限公司 | Device and method for manufacturing a device |
US9899325B2 (en) * | 2014-08-07 | 2018-02-20 | Infineon Technologies Ag | Device and method for manufacturing a device with a barrier layer |
CN105374855B (en) * | 2014-08-07 | 2018-07-17 | 英飞凌科技股份有限公司 | Device and method for manufacturing device |
Also Published As
Publication number | Publication date |
---|---|
US6566253B2 (en) | 2003-05-20 |
US20010019882A1 (en) | 2001-09-06 |
US6051879A (en) | 2000-04-18 |
US6380626B1 (en) | 2002-04-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6207559B1 (en) | Method of making a semiconductor device for attachment to a semiconductor substrate | |
US6779711B2 (en) | Self-aligned corrosion stop for copper C4 and wirebond | |
US7262126B2 (en) | Sealing and protecting integrated circuit bonding pads | |
JP3172501B2 (en) | Titanium-tungsten alloy etching method and etchant solution | |
JP2528617B2 (en) | Multilayer interconnect metal structure and method of forming same | |
US4840302A (en) | Chromium-titanium alloy | |
US6979647B2 (en) | Method for chemical etch control of noble metals in the presence of less noble metals | |
US3881884A (en) | Method for the formation of corrosion resistant electronic interconnections | |
JP2526007B2 (en) | Structures and methods for forming electrical interconnections to semiconductor chips | |
EP0690504A1 (en) | Solder terminal and method of fabricating it | |
US6933614B2 (en) | Integrated circuit die having a copper contact and method therefor | |
US5446625A (en) | Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface | |
CN1311526A (en) | Method for mfg. conductive seat used for electric connection and formed conductive seat therefor | |
US6784088B2 (en) | Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped | |
JPS62145758A (en) | Method for protecting copper bonding pad from oxidation using palladium | |
US6297160B1 (en) | Application of pure aluminum to prevent pad corrosion | |
US20080274294A1 (en) | Copper-metallized integrated circuits having electroless thick copper bond pads | |
US7560369B2 (en) | Method of forming metal line in semiconductor device | |
EP0256357B1 (en) | Semiconductor chip including a bump structure for tape automated bonding | |
US6555912B1 (en) | Corrosion-resistant electrode structure for integrated circuit decoupling capacitors | |
CN1879208A (en) | I/O sites for probe test and wire bond | |
CN101088152A (en) | Semiconductor chip and method for manufacturing same, electrode structure of semiconductor chip and method for forming same, and semiconductor device | |
JP3242827B2 (en) | Method for manufacturing semiconductor device | |
CN1205114A (en) | Process for single mask C4 solder bump fabrication | |
JP3498094B2 (en) | Method of forming circuit wiring or electrode in semiconductor chip |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JIANG, TONGBI;REEL/FRAME:009609/0269 Effective date: 19971211 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001 Effective date: 20180629 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001 Effective date: 20190731 |