US6125467A - Method and apparatus for partial word read through ECC block - Google Patents
Method and apparatus for partial word read through ECC block Download PDFInfo
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- US6125467A US6125467A US09/063,962 US6396298A US6125467A US 6125467 A US6125467 A US 6125467A US 6396298 A US6396298 A US 6396298A US 6125467 A US6125467 A US 6125467A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/1052—Bypassing or disabling error detection or correction
Definitions
- the present invention generally relates to computer systems, particularly to a method of transmitting information between different components in a computer system, such as between a system memory device and a central processing unit, and more specifically to a method and apparatus for reading a partial word through an error-correcting code (ECC) circuit.
- ECC error-correcting code
- a typical structure for a conventional computer system includes one or more processing units connected to a system memory device (random access memory or RAM) and to various peripheral, or input/output (I/O), devices such as a display monitor, a keyboard, a graphical pointer (mouse), and a permanent storage device (hard disk).
- the system memory device is used by a processing unit in carrying out program instructions, and stores those instructions as well as data values that are used or generated by the programs.
- a read-only memory device ROM is used to provide firmware whose primary purpose is to seek out and load an operating system from one of the peripherals (usually the permanent storage device) whenever the computer is first turned on.
- a processing unit communicates with the other components by various means, including one or more interconnects (buses), or direct memory-access channels.
- a computer system may have many additional components, such as serial and parallel ports for connection to, e.g., printers, and network adapters.
- Other components might further be used in conjunction with the foregoing; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access the system memory, etc.
- System 10 includes a central processing unit (CPU) 12, firmware or read-only memory (ROM) 14, and a dynamic random access memory (DRAM) 16 which are all connected to a system bus 18.
- CPU 12, ROM 14 and DRAM 16 are also coupled to a peripheral component interconnect (PCI) local bus 20 using a PCI host bridge 22.
- PCI host bridge 22 provides a low latency path through which processor 12 may access PCI devices mapped anywhere within bus memory or I/O address spaces.
- PCI host bridge 22 also provides a high bandwidth path to allow the PCI devices to access DRAM 16.
- Attached to PCI local bus 20 are a local area network (LAN) adapter 24, a small computer system interface (SCSI) adapter 26, an expansion bus bridge 28, an audio adapter 30, and a graphics adapter 32.
- Lan adapter 24 is used to connected computer system 10 to an external computer network 34.
- SCSI adapter 26 is used to control high-speed SCSI disk drive 36.
- Expansion bus bridge 28 is used to couple an ISA (Industry Standard Architecture) expansion bus 38 to PCI local bus 20.
- ISA bus 38 As shown, several user input devices are connected to ISA bus 38, including a keyboard 40, a microphone 42, and a graphical pointing device (mouse) 44. Other devices may also be attached to ISA bus 38, such as a CD-ROM drive 46.
- Audio adapter 30 controls audio output to a speaker 48
- graphics adapter 32 controls visual output to a display monitor 50.
- Parity checks and error-correction codes are commonly used to ensure that data is properly transferred between system components.
- a magnetic disk permanent memory device
- ECC's are also used with temporary memory devices, e.g., DRAM or cache memory devices, and the ECC for files stored in DRAM can be analyzed by a memory controller which provides an interface between the processor and the DRAM array.
- a memory cell fails during reading of a particular memory word (due to, e.g., stray radiation, electrostatic discharge, or a defective cell), then the failure can at least be detected so that further action can be taken. ECC's can further be used to reconstruct the proper data stream.
- Some error correction codes can only be used to detect single-bit errors; if two or more bits in a particular memory word are invalid, then the ECC might not be able to determine what the proper data stream should actually be.
- Other ECC's are more sophisticated and allow detection or correction of double errors, and some ECC's further allow the memory word to be broken up into clusters of bits, or "symbols," which can then be analyzed for errors in even more detail.
- ECC circuits One limitation of ECC circuits relates to the fact that they are always designed to receive and analyze a memory word of a fixed width.
- DRAM 16 might provide a 64-bit data word (eight 8-bit bytes), with an additional 8-bit check word used for error correction (i.e., a total of 72 bits). Therefore, if an ECC circuit were implemented in an interconnection between the DRAM and some other component (such as CPU 12), then the ECC circuit would necessarily be constructed to specifically conform to the 72-bit format.
- the presence of an ECC circuit in this communications path prevents other devices from using the path if they do not utilize the same word format. In other words, a problem exists where a memory word having a width less than the fixed width is to be read through the ECC block.
- ROM 14 transmits single-byte data (8 bits). If ROM data were to pass through an ECC block adapted for DRAM 16, then the check word and the remaining data bits expected by the ECC block would be undefined. In this situation, one of three results can occur within the ECC block (depending upon the ROM value): no error is detected; a single-bit error is detected; or a multiple-bit error is detected. The case of "no error detected” is possible where the undefined signals input into the ECC block, along with the ROM byte, exactly match a "no error" pattern. This result will leave the ROM data bits unaffected, and therefore does not present a problem.
- the undefined signals do not match the "no error” pattern, but the data is passed through unmodified anyway (including the ROM data), since the ECC block cannot determine which bits require correction, so this case also does not present a problem.
- the error-correction code presumes that the memory word has a single-bit error which can be corrected and, as a consequence, the ECC circuitry will modify the imagined 64-bit memory word, by complementing one of these 64 bits. If the modified bit is within the ROM data bits, a ROM corruption will appear to the reading device (e.g., CPU 12), which could lead to catastrophic failure of the system.
- ECC error-correction code
- a method of communicating between components in a computer system generally comprising the steps of providing a communications path between a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)), wherein the first component transmits data to the second component using a first granularity, and wherein the communications path includes an error-correction code (ECC) circuit adapted to detect and correct parity errors transmitted from the first component to the second component, interconnecting a third component to the communications path (such as a read-only memory (ROM) device) such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity, and merging data from the third component with predefined data to present a merged data word to the ECC circuit, the merged data word having the first granularity.
- ECC error-correction code
- the first granularity may be, e.g., 72 bits, while the second granularity is 8 bits.
- the data is merged by forcing undriven check bits and undriven data bits in the ECC block to a predefined state such that error correction of the merged data word by the ECC circuit results in modification of the predefined data and not in modification of the data from the third component.
- the undriven check bits and undriven data bits are preferably forced to the predefined state using a plurality of respective pull-up resistors.
- FIG. 1 is block diagram of a conventional computer system
- FIG. 2 is a block diagram of one embodiment of a communications path within a computer system, constructed in accordance with the present invention, which provides an error-correction code block usable by one device having a first granularity (a ROM device), and another device having a second granularity (a RAM device).
- a ROM device a device having a first granularity
- a RAM device a device having a second granularity
- Communications path 100 comprises a system or CPU bus 104, an ECC block 106, and a memory bus which in the depicted embodiment includes a data bus 108 and a check word bus 110.
- Check word bus 110 is connected to a memory device 112 having a large word size (granularity), such as a 72-bit DRAM device wherein 64 bits comprise the data word and eight bits comprise the check word.
- Data bus 108 is also connected to DRAM 112, and is further connected to an 8-bit ROM device 114 (containing the firmware used to start up system 102).
- CPU bus 104 is connected to a CPU 116, a memory controller 118, and one or more other devices such as those shown in FIG. 1. While the various devices shown in FIG. 1 can be utilized in conjunction with a computer system constructed in accordance with the present invention, those skilled in the art will appreciate that the present invention may be applied to computer systems having novel components, or having novel arrangements of conventional components. Therefore, the reference to FIG. 1 should not be construed in a limiting sense.
- ECC block 106 is designed to provide single-bit error correction and multi-bit error detection for the 72-bit memory words transmitted from DRAM 112. It is convenient, however, to allow ROM 114 to additionally use memory data bus 108 to provide an interconnection with CPU 116.
- the present invention overcomes the problem in prior art systems, of using a single ECC block with devices of differing granularities, by forcing the undriven check word and the undriven data bits (when ROM 114 owns the memory bus) to a predefined state wherein any single-bit errors based on the ECC block's "no error" pattern will result only in modifications to the imagined 64-bit data word that do not complement any of the eight bits in the ROM byte.
- the undriven check word and the undriven data bits are forced to the predefined state using bias (pull-up) resistors 120 and 122.
- the ROM bits 0 . . . 7 supply data to the inputs Data00 . . . Data07.
- the data bits Data08 . . . Data63 are set to 1 for all ROM reads by resistors 120.
- the check bits Check0 . . . Check7 are similarly set to 1 for all ROM reads by resistors 122.
- the table included in the Appendix indicates the results for all 256 possible ROM data patterns.
- All 256 of these patterns pass the ROM data through the ECC block without modification, although some do result in modification of other data that is of no concern, since memory controller 118 examines only the first eight bits when constructing a 64-bit ROM word for CPU 116. In other words, memory controller 118 collects these first eight bits from a series of eight ROM reads, and then passes those 64 bits as a single ROM word to CPU 116.
- ROM 114 drives bus 108 for the ROM access time, but the data is only sampled after the access time. Therefore, pull-up resistors that result in an RC time constant less that the ROM access time ( ⁇ 150 ns) may be used.
- This approach is relatively low cost, particularly when compared to the alternatives of special bypass circuitry around the ECC block, or the expense of a 72-bit wide ROM.
- An alternative approach contemplated by the present invention is to use a bank of 1's provided by a buffer which is turned on when ROM 114 is selected, but that embodiment is more expensive. Either approach places significantly less load on the CPU bus as compared to the alternatives.
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Abstract
A method of passing transmissions through an error-correction code (ECC) block in a communications path of a computer system. The communications path interconnects a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)) using a first granularity, and a third component (such as a read-only memory (ROM) device) is further connected to the communications path such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity. The data from the third component passes through the ECC block by merging data from the third component with predefined data to present a merged data word to the ECC circuit, wherein the merged data word has the first granularity. The first granularity may be, e.g., 72 bits, while the second granularity is 8 bits. The undriven check bits and undriven data bits are preferably forced to the predefined state using a plurality of respective pull-up resistors.
Description
1. Field of the Invention
The present invention generally relates to computer systems, particularly to a method of transmitting information between different components in a computer system, such as between a system memory device and a central processing unit, and more specifically to a method and apparatus for reading a partial word through an error-correcting code (ECC) circuit.
2. Description of Related Art
A typical structure for a conventional computer system includes one or more processing units connected to a system memory device (random access memory or RAM) and to various peripheral, or input/output (I/O), devices such as a display monitor, a keyboard, a graphical pointer (mouse), and a permanent storage device (hard disk). The system memory device is used by a processing unit in carrying out program instructions, and stores those instructions as well as data values that are used or generated by the programs. A read-only memory device (ROM) is used to provide firmware whose primary purpose is to seek out and load an operating system from one of the peripherals (usually the permanent storage device) whenever the computer is first turned on. A processing unit communicates with the other components by various means, including one or more interconnects (buses), or direct memory-access channels. A computer system may have many additional components, such as serial and parallel ports for connection to, e.g., printers, and network adapters. Other components might further be used in conjunction with the foregoing; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access the system memory, etc.
An exemplary computer system 10 is illustrated in FIG. 1. System 10 includes a central processing unit (CPU) 12, firmware or read-only memory (ROM) 14, and a dynamic random access memory (DRAM) 16 which are all connected to a system bus 18. CPU 12, ROM 14 and DRAM 16 are also coupled to a peripheral component interconnect (PCI) local bus 20 using a PCI host bridge 22. PCI host bridge 22 provides a low latency path through which processor 12 may access PCI devices mapped anywhere within bus memory or I/O address spaces. PCI host bridge 22 also provides a high bandwidth path to allow the PCI devices to access DRAM 16.
Attached to PCI local bus 20 are a local area network (LAN) adapter 24, a small computer system interface (SCSI) adapter 26, an expansion bus bridge 28, an audio adapter 30, and a graphics adapter 32. Lan adapter 24 is used to connected computer system 10 to an external computer network 34. SCSI adapter 26 is used to control high-speed SCSI disk drive 36. Expansion bus bridge 28 is used to couple an ISA (Industry Standard Architecture) expansion bus 38 to PCI local bus 20. As shown, several user input devices are connected to ISA bus 38, including a keyboard 40, a microphone 42, and a graphical pointing device (mouse) 44. Other devices may also be attached to ISA bus 38, such as a CD-ROM drive 46. Audio adapter 30 controls audio output to a speaker 48, and graphics adapter 32 controls visual output to a display monitor 50.
Parity checks and error-correction codes (ECC's) are commonly used to ensure that data is properly transferred between system components. For example, a magnetic disk (permanent memory device) typically records not only information that comprises data to be retrieved for processing (the memory word), but also records an error-correction code for each file, which allows the processor, or a controller, to determine whether the data retrieved is valid. ECC's are also used with temporary memory devices, e.g., DRAM or cache memory devices, and the ECC for files stored in DRAM can be analyzed by a memory controller which provides an interface between the processor and the DRAM array. If a memory cell fails during reading of a particular memory word (due to, e.g., stray radiation, electrostatic discharge, or a defective cell), then the failure can at least be detected so that further action can be taken. ECC's can further be used to reconstruct the proper data stream.
Some error correction codes can only be used to detect single-bit errors; if two or more bits in a particular memory word are invalid, then the ECC might not be able to determine what the proper data stream should actually be. Other ECC's are more sophisticated and allow detection or correction of double errors, and some ECC's further allow the memory word to be broken up into clusters of bits, or "symbols," which can then be analyzed for errors in even more detail.
One limitation of ECC circuits relates to the fact that they are always designed to receive and analyze a memory word of a fixed width. In a computer system such as that shown in FIG. 1, DRAM 16 might provide a 64-bit data word (eight 8-bit bytes), with an additional 8-bit check word used for error correction (i.e., a total of 72 bits). Therefore, if an ECC circuit were implemented in an interconnection between the DRAM and some other component (such as CPU 12), then the ECC circuit would necessarily be constructed to specifically conform to the 72-bit format. The presence of an ECC circuit in this communications path, however, prevents other devices from using the path if they do not utilize the same word format. In other words, a problem exists where a memory word having a width less than the fixed width is to be read through the ECC block.
For example, in the system of FIG. 1, ROM 14 transmits single-byte data (8 bits). If ROM data were to pass through an ECC block adapted for DRAM 16, then the check word and the remaining data bits expected by the ECC block would be undefined. In this situation, one of three results can occur within the ECC block (depending upon the ROM value): no error is detected; a single-bit error is detected; or a multiple-bit error is detected. The case of "no error detected" is possible where the undefined signals input into the ECC block, along with the ROM byte, exactly match a "no error" pattern. This result will leave the ROM data bits unaffected, and therefore does not present a problem. In the case of "multiple-bit error detected," the undefined signals do not match the "no error" pattern, but the data is passed through unmodified anyway (including the ROM data), since the ECC block cannot determine which bits require correction, so this case also does not present a problem. However, in the case of "single-bit error detected," while the undefined signals do not match the "no error" pattern, the error-correction code presumes that the memory word has a single-bit error which can be corrected and, as a consequence, the ECC circuitry will modify the imagined 64-bit memory word, by complementing one of these 64 bits. If the modified bit is within the ROM data bits, a ROM corruption will appear to the reading device (e.g., CPU 12), which could lead to catastrophic failure of the system.
One solution to the foregoing problem is to simply make all devices which use a common ECC block operate at the same granularity, that is, with the same memory word size. This solution is not, however, always feasible. For example, considering again the use of an ECC block which passes data from both a DRAM device and a ROM device, this approach would require the use of a 72-bit ROM, which is quite expensive compared to 8-bit ROMs. In light of the foregoing, it would be desirable to devise a method of passing different sizes of memory words through a common ECC block. It would be further advantageous if the method could be implemented at a relatively low cost and with less load on the CPU bus.
It is therefore one object of the present invention to provide an improved computer system having error-correction and detection in transmission of data between system components.
It is another object of the present invention to provide such a computer system wherein error-correction code (ECC) circuitry can be established in a single communications path used by devices having different memory word sizes, such as an 8-bit ROM and a 72-bit RAM.
It is yet another object of the present invention to provide a simple and inexpensive method of constructing such a compliant ECC block.
The foregoing objects are achieved in a method of communicating between components in a computer system, generally comprising the steps of providing a communications path between a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)), wherein the first component transmits data to the second component using a first granularity, and wherein the communications path includes an error-correction code (ECC) circuit adapted to detect and correct parity errors transmitted from the first component to the second component, interconnecting a third component to the communications path (such as a read-only memory (ROM) device) such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity, and merging data from the third component with predefined data to present a merged data word to the ECC circuit, the merged data word having the first granularity. The first granularity may be, e.g., 72 bits, while the second granularity is 8 bits. The data is merged by forcing undriven check bits and undriven data bits in the ECC block to a predefined state such that error correction of the merged data word by the ECC circuit results in modification of the predefined data and not in modification of the data from the third component. The undriven check bits and undriven data bits are preferably forced to the predefined state using a plurality of respective pull-up resistors.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is block diagram of a conventional computer system; and
FIG. 2 is a block diagram of one embodiment of a communications path within a computer system, constructed in accordance with the present invention, which provides an error-correction code block usable by one device having a first granularity (a ROM device), and another device having a second granularity (a RAM device).
With reference now to the figures, and in particular with reference to FIG. 2, there is depicted one embodiment of a communications path 100 within a computer system 102, constructed in accordance with the present invention. Communications path 100 comprises a system or CPU bus 104, an ECC block 106, and a memory bus which in the depicted embodiment includes a data bus 108 and a check word bus 110. Check word bus 110 is connected to a memory device 112 having a large word size (granularity), such as a 72-bit DRAM device wherein 64 bits comprise the data word and eight bits comprise the check word. Data bus 108 is also connected to DRAM 112, and is further connected to an 8-bit ROM device 114 (containing the firmware used to start up system 102).
In a preferred embodiment, the undriven check word and the undriven data bits are forced to the predefined state using bias (pull-up) resistors 120 and 122. The ROM bits 0 . . . 7 supply data to the inputs Data00 . . . Data07. The data bits Data08 . . . Data63 are set to 1 for all ROM reads by resistors 120. The check bits Check0 . . . Check7 are similarly set to 1 for all ROM reads by resistors 122. The table included in the Appendix indicates the results for all 256 possible ROM data patterns. All 256 of these patterns pass the ROM data through the ECC block without modification, although some do result in modification of other data that is of no concern, since memory controller 118 examines only the first eight bits when constructing a 64-bit ROM word for CPU 116. In other words, memory controller 118 collects these first eight bits from a series of eight ROM reads, and then passes those 64 bits as a single ROM word to CPU 116.
It is preferable to select 1's in the static bits using pull-up resistors, since they can supply the necessary high logic level for the relatively long duration of the ROM cycle. ROM 114 drives bus 108 for the ROM access time, but the data is only sampled after the access time. Therefore, pull-up resistors that result in an RC time constant less that the ROM access time (˜150 ns) may be used. This approach is relatively low cost, particularly when compared to the alternatives of special bypass circuitry around the ECC block, or the expense of a 72-bit wide ROM. An alternative approach contemplated by the present invention is to use a bank of 1's provided by a buffer which is turned on when ROM 114 is selected, but that embodiment is more expensive. Either approach places significantly less load on the CPU bus as compared to the alternatives.
Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. For example, the foregoing embodiment illustrates the application of the invention to an 8-bit ROM and a 64-bit RAM, but the invention can further be adapted to interconnect devices having other granularities. The nature of the ECC block could be more complicated than described, and the communications path might interconnect devices other than memory and the CPU. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the present invention as defined in the appended claims.
APPENDIX ______________________________________ In each of the following cases, the term "trick" refers to the forced data (D.sub.8 . . . D.sub.63 and C.sub.0 . . . C.sub.7) merged with the ROM data. The term "in" is the output ofECC block 106. When "sbe.sub.-- " is low (zero), this indicates single-bit error status. When "mbe.sub.-- " is low (zero), this indicates multi-bit error status. In each case where sbe.sub.-- = 0, one bit is complemented but that bit is not in the ROM data (the rightmost two hexadecimal characters). ______________________________________ trick =ffffffffffffff00 in =ffffffffffffff00 rom = 00 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff01 in =ffffffffffffff01 rom = 01 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff02 in =ffffffffffffff02 rom = 02 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff03 in =ffffffffffffff03 rom = 03 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff04 in =ffffffffffffff04 rom = 04 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff05 in =ffffffffffffff05 rom = 05 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff06 in =ffffffffffffff06 rom = 06 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff07 in =ffffffffff7fff07 rom = 07 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff08 in =ffffffffffffff08 rom = 08 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff09 in =ffffffffffffff09 rom = 09 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff0a in =ffffffffffffff0a rom = 0a sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff0b in =ffffffffffbfff0b rom = 0b sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff0c in =ffffffffffffff0c rom = 0c sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff0d in =ffffffffffdfff0d rom = 0d sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff0e in =ffffffffffefff0e rom = 0e sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff0f in =ffffffffffffff0f rom = 0f sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff10 in =ffffffffffffff10 rom = 10 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff11 in =ffffffffffffff11 rom = 11 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff12 in =ffffffffffffff12 rom = 12 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff13 in =ffffffffffffff13 rom = 13 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff14 in =ffffffffffffff14 rom = 14 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff15 in =ffffffffffffff15 rom = 15 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff16 in =fffffffffff7ff16 rom = 16 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff17 in =ffffffffffffff17 rom = 17 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff18 in =ffffffffffffff18 rom = 18 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff19 in =ffffffffffffff19 rom = 19 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff1a in =fffffffffffbff1a rom = 1a sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff1b in =ffffffffffffff1b rom = 1b sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff1c in =fffffffffffdff1c rom = 1c sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff1d in =ffffffffffffff1d rom = 1d sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff1e in =ffffffffffffff1e rom = 1e sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff1f in =fffffffffffeff1f rom = 1f sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff20 in =ffffffffffffff20 rom = 20 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff21 in =ffffffffffffff21 rom = 21 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff22 in =ffffffffffffff22 rom = 22 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff23 in =ffffffffffffff23 rom = 23 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff24 in =ffffffffffffff24 rom = 24 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff25 in =fffffffffff7ff25 rom = 25 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff26 in =ffffffffffffff26 rom = 26 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff27 in =ffffffffffffff27 rom = 27 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff28 in =ffffffffffffff28 rom = 28 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff29 in =fffffffffffbff29 rom = 29 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff2a in =ffffffffffffff2a rom = 2a sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff2b in =ffffffffffffff2b rom = 2b sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff2c in =fffffffffffeff2c rom = 2c sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff2d in =ffffffffffffff2d rom = 2d sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff2e in =ffffffffffffff2e rom = 2e sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff2f in =fffffffffffdff2f rom = 2f sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff30 in =ffffffffffffff30 rom = 30 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff31 in =ffffffffffffff31 rom = 31 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff32 in =ffffffffffffff32 rom = 32 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff33 in =ffffffffffffff33 rom = 33 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff34 in =ffffffffff7fff34 rom = 34 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff35 in =ffffffffffffff35 rom = 35 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff36 in =ffffffffffffff36 rom = 36 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff37 in =ffffffffffffff37 rom = 37 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff38 in =ffffffffffbfff38 rom = 38 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff39 in =ffffffffffffff39 rom = 39 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff3a in =ffffffffffffff3a rom = 3a sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff3b in =ffffffffffffff3b rom = 3b sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff3c in =ffffffffffffff3c rom = 3c sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff3d in =ffffffffffefff3d rom = 3d sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff3e in =ffffffffffdfff3e rom = 3e sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff3f in =ffffffffffffff3f rom = 3f sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff40 in =ffffffffffffff40 rom = 40 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff41 in =ffffffffffffff41 rom = 41 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff42 in =ffffffffffffff42 rom = 42 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff43 in =fffffffffff7ff43 rom = 43 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff44 in =ffffffffffffff44 rom = 44 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff45 in =ffffffffffffff45 rom = 45 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff46 in =ffffffffffffff46 rom = 46 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff47 in =ffffffffffffff47 rom = 47 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff48 in =ffffffffffffff48 rom = 48 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff49 in =fffffffffffdff49 rom = 49 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff4a in =fffffffffffeff4a rom = 4a sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff4b in =ffffffffffffff4b rom = 4b sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff4c in =ffffffffffffff4c rom = 4c sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff4d in =ffffffffffffff4d rom = 4d sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff4e in =ffffffffffffff4e rom = 4e sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff4f in =fffffffffffbff4f rom = 4f sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff50 in =ffffffffffffff50 rom = 50 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff51 in =ffffffffffffff51 rom = 51 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff52 in =ffffffffff7fff52 rom = 52 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff53 in =ffffffffffffff53 rom = 53 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff54 in =ffffffffffffff54 rom = 54 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff55 in =ffffffffffffff55 rom = 55 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff56 in =ffffffffffffff56 rom = 56 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff57 in =ffffffffffffff57 rom = 57 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff58 in =ffffffffffdfff58 rom = 58 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff59 in =ffffffffffffff59 rom = 59 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff5a in =ffffffffffffff5a rom = 5a sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff5b in =ffffffffffefff5b rom = 5b sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff5c in =ffffffffffffff5c rom = 5c sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff5d in =ffffffffffffff5d rom = 5d sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff5e in =ffffffffffbfff5e rom = 5e sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff5f in =ffffffffffffff5f rom = 5f sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff60 in =ffffffffffffff60 rom = 60 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff61 in =ffffffffff7fff61 rom = 61 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff62 in =ffffffffffffff62 rom = 62 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff63 in =ffffffffffffff63 rom = 63 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff64 in =ffffffffffffff64 rom = 64 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff65 in =ffffffffffffff65 rom = 65 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff66 in =ffffffffffffff66 rom = 66 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff67 in =ffffffffffffff67 rom = 67 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff68 in =ffffffffffefff68 rom = 68 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff69 in =ffffffffffffff69 rom = 69 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff6a in =ffffffffffffff6a rom = 6a sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff6b in =ffffffffffdfff6b rom = 6b sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff6c in =ffffffffffffff6c rom = 6c sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff6d in =ffffffffffbfff6d rom = 6d sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff6e in =ffffffffffffff6e rom = 6e sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff6f in =ffffffffffffff6f rom = 6f sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff70 in =fffffffffff7ff70 rom = 70 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff71 in =ffffffffffffff71 rom = 71 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff72 in =ffffffffffffff72 rom = 72 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff73 in =ffffffffffffff73 rom = 73 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff74 in =ffffffffffffff74 rom = 74 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff75 in =ffffffffffffff75 rom = 75 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff76 in =ffffffffffffff76 rom = 76 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff77 in =ffffffffffffff77 rom = 77 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff78 in =ffffffffffffff7e rom = 78 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff79 in =fffffffffffeff79 rom = 79 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff7a in =fffffffffffdff7a rom = 7a sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff7b in =ffffffffffffff7b rom = 7b sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff7c in =fffffffffffbff7c rom = 7c sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff7d in =ffffffffffffff7d rom = 7d sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff7e in =ffffffffffffff7e rom = 7e sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff7f in =ffffffffffffff7f rom = 7f sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff80 in =ffffffffffffff80 rom = 80 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff81 in =ffffffffffffff81 rom = 81 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff82 in =ffffffffffffff82 rom = 82 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff83 in =fffffffffffbff83 rom = 83 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff84 in =ffffffffffffff84 rom = 84 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff85 in =fffffffffffdff85 rom = 85 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff86 in =fffffffffffeff86 rom = 86 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff87 in =ffffffffffffff87 rom = 87 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff88 in =ffffffffffffff88 rom = 88 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff89 in =ffffffffffffff89 rom = 89 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff8a in =ffffffffffffff8a rom = 8a sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff8b in =ffffffffffffff8b rom = 8b sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff8c in =ffffffffffffff8c rom = 8c sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff8d in =ffffffffffffff8d rom = 8d sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff8e in =ffffffffffffff8e rom = 8e sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff8f in =fffffffffff7ff8f rom = 8f sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff90 in =ffffffffffffff90 rom = 90 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff91 in =ffffffffffffff91 rom = 91 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff92 in =ffffffffffbfff92 rom = 92 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff93 in =ffffffffffffff93 rom = 93 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff94 in =ffffffffffdfff94 rom = 94 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff95 in =ffffffffffffff95 rom = 95 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff96 in =ffffffffffffff96 rom = 96 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff97 in =ffffffffffefff97 rom = 97 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff98 in =ffffffffffffff98 rom = 98 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff99 in =ffffffffffffff99 rom = 99 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff9a in =ffffffffffffff9a rom = 9a sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff9b in =ffffffffffffff9b rom = 9b sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff9c in =ffffffffffffff9c rom = 9c sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff9d in =ffffffffffffff9d rom = 9d sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffff9e in =ffffffffff7fff9e rom = 9e sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffff9f in =ffffffffffffff9f rom = 9f sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffa0 in =ffffffffffffffa0 rom = 00 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffa1 in =ffffffffffbfffa1 rom = a1 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffa2 in =ffffffffffffffa2 rom = a2 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffa3 in =ffffffffffffffa3 rom = a3 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffa4 in =ffffffffffefffa4 rom = a4 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffa5 in =ffffffffffffffa5 rom = a5 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffa6 in =ffffffffffffffa6 rom = a6 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffa7 in =ffffffffffdfffa7 rom = a7 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffa8 in =ffffffffffffffa8 rom = a8 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffa9 in =ffffffffffffffa9 rom = a9 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffaa in =ffffffffffffffaa rom = aa sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffab in =ffffffffffffffab rom = ab sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffac in =ffffffffffffffac rom = ac sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffad in =ffffffffff7fffad rom = ad sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffae in =ffffffffffffffae rom = ae sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffaf in =ffffffffffffffaf rom = af sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffb1 in =ffffffffffffffb1 rom = b1 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffb2 in =ffffffffffffffb2 rom = b2 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffb3 in =ffffffffffffffb3 rom = b3 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffb4 in =ffffffffffffffb4 rom = b4 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffb5 in =fffffffffffeffb5 rom = b5 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffb6 in =fffffffffffdffb6 rom = b6 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffb7 in =ffffffffffffffb7 rom = b7 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffb8 in =ffffffffffffffb8 rom = b8 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffb9 in =ffffffffffffffb9 rom = b9 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffba in =ffffffffffffffba rom = ba sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffbb in =ffffffffffffffbb rom = bb sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffbc in =fffffffffff7ffbc rom = bc sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffbd in =ffffffffffffffbd rom = bd sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffbe in =ffffffffffffffbe rom = be sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffbf in =ffffffffffffffbf rom = bf sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffc0 in =ffffffffffffffc0 rom = c0 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffc1 in =ffffffffffdfffc1 rom = c1 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffc2 in =ffffffffffefffc2 rom = c2 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffc3 in =ffffffffffffffc3 rom = c3 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffc4 in =ffffffffffffffc4 rom = c4 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffc5 in =ffffffffffffffc5 rom = c5 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffc6 in =ffffffffffffffc6 rom = c6 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffc7 in =ffffffffffbfffc7 rom = c7 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffc8 in =ffffffffffffffc8 rom = c8 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffc9 in =ffffffffffffffc9 rom = c9 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffca in =ffffffffffffffca rom = ca sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffcb in =ffffffffff7fffcb rom = cb sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffcc in =ffffffffffffffcc rom = cc sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffcd in =ffffffffffffffcd rom = cd sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffce in =ffffffffffffffce rom = ce sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffcf in =ffffffffffffffcf rom = cf sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffd0 in =fffffffffffdffd0 rom = d0 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffd1 in =ffffffffffffffd1 rom = d1 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffd2 in =ffffffffffffffd2 rom = d2 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffd3 in =fffffffffffeffd3 rom = d3 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffd4 in =ffffffffffffffd4 rom = d4 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffd5 in =ffffffffffffffd5 rom = d5 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffd6 in =fffffffffffbffd6 rom = d6 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffd7 in =ffffffffffffffd7 rom = d7 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffd8 in =ffffffffffffffd8 rom = d8 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffd9 in =ffffffffffffffd9 rom = d9 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffda in =fffffffffff7ffda rom = da sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffdb in =ffffffffffffffdb rom = db sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffdc in =ffffffffffffffdc rom = dc sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffdd in =ffffffffffffffdd rom = dd sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffde in =ffffffffffffffde rom = de sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffdf in =ffffffffffffffdf rom = df sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffe0 in =fffffffffffeffe0 rom = e0 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffe1 in =ffffffffffffffe1 rom = e1 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffe2 in =ffffffffffffffe2 rom = e2 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffe3 in =fffffffffffdffe3 rom = e3 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffe4 in =ffffffffffffffe4 rom = e4 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffe5 in =fffffffffffbffe5 rom = e5 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffe6 in =ffffffffffffffe6 rom = e6 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffe7 in =ffffffffffffffe7 rom = e7 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffe8 in =ffffffffffffffe8 rom = e8 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffe9 in =fffffffffff7ffe9 rom = e9 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =ffffffffffffffea in =ffffffffffffffea rom = ea sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffeb in =ffffffffffffffeb rom = eb sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffec in =ffffffffffffffec rom = ec sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffed in =ffffffffffffffed rom = ed sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffee in =ffffffffffffffee rom = ee sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffef in =ffffffffffffffef rom = ef sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffff0 in =fffffffffffffff0 rom = f0 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffff1 in =ffffffffffeffff1 rom = f1 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =fffffffffffffff2 in =ffffffffffdffff2 rom = f2 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =fffffffffffffff3 in =fffffffffffffff3 rom = f3 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffff4 in =ffffffffffbffff4 rom = f4 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =fffffffffffffff5 in =fffffffffffffff5 rom = f5 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffff6 in =fffffffffffffff6 rom = f6 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffff7 in =fffffffffffffff7 rom = f7 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffff8 in =ffffffffff7ffff8 rom = f8 sbe.sub.-- = 0 mbe.sub.-- = 1 trick =fffffffffffffff9 in =fffffffffffffff9 rom = f9 sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffffa in =fffffffffffffffa rom = fa sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffffb in =fffffffffffffffb rom = fb sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffffc in =fffffffffffffffc rom = fc sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffffd in =fffffffffffffffd rom = fd sbe.sub.-- = 1 mbe.sub.-- = 0 trick =fffffffffffffffe in =fffffffffffffffe rom = fe sbe.sub.-- = 1 mbe.sub.-- = 0 trick =ffffffffffffffff in =ffffffffffffffff rom = ff sbe.sub.-- = 1 mbe.sub.-- = 0 ______________________________________
Claims (15)
1. A method of communicating between components in a computer system, comprising the step of:
providing a communications path between a first component of the computer system and a second component of the computer system, wherein the first component transmits data to the second component using a first granularity, and wherein the communications path includes an error-correction code (ECC) circuit adapted to detect and correct memory errors transmitted from the first component to the second component;
interconnecting a third component to the communications path such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity; and
merging data from the third component with predefined data to present a merged data word to the ECC circuit, the merged data word having the first granularity.
2. The method of claim 1 further comprising the step of correcting a single-bit error in the merged data word using the ECC circuit.
3. The method of claim 1 wherein the first granularity is 72 bits, the second granularity is 8 bits, and further comprising the step of creating the predefined data with 64 bits.
4. The method of claim 1 wherein said merging step includes the step of forcing undriven check bits and undriven data bits to a predefined state such that error correction of the merged data word by the ECC circuit results in modification of the predefined data and not in modification of the data from the third component.
5. The method of claim 4 wherein the undriven check bits and undriven data bits are forced to the predefined state using a plurality of respective pull-up resistors.
6. The method of claim 1 wherein:
the first component is a random-access memory (RAM) device;
the second component is a central processing unit (CPU);
the third component is a read-only memory (ROM) device; and
said interconnecting step includes the steps of connecting the ECC circuit and the CPU to a system bus, and connecting the RAM device, the ROM device and the ECC circuit to a memory bus.
7. The method of claim 6 further comprising the steps of:
forwarding a plurality of such merged data words to a memory controller;
constructing a ROM word having the first granularity using the memory controller; and
transmitting the ROM word from the memory controller to the CPU.
8. The method of claim 6 wherein said merging step includes the step of forcing undriven check bits and undriven data bits to a predefined state such that error correction of the merged data word by the ECC circuit results in of modification the predefined data and not in modification of the data from the ROM device.
9. The method of claim 8 wherein the undriven check bits and undriven data bits are forced to the predefined state using a plurality of respective pull-up resistors.
10. A computer system comprising:
a random-access memory (RAM) device having a first data width;
a read-only memory (ROM) device having a second data width which is smaller than said first data width;
means for processing program instructions;
means interconnecting said processing means with said RAM and ROM devices, said interconnecting means including error-correction code (ECC) means for correcting an error in a memory word transmitted by said RAM device; and
means for merging a memory word from said ROM device with predefined data to present a merged data word to said ECC means, wherein said merged data word has a width equal to said first data width.
11. The computer system of claim 10 wherein said ECC means corrects a single-bit error in said merged data word.
12. The computer system of claim 10 wherein:
said first data width is 72 bits; and
said second data width is 8 bits.
13. The computer system of claim 10 wherein said merging means forces undriven check bits and undriven data bits in said ECC means to a predefined state such that error correction of said merged data word by said ECC means results in modification of said predefined data and not in modification of said memory word from said ROM device.
14. The computer system of claim 10 wherein said merging means includes a plurality of respective pull-up resistors adapted to bias said undriven check bits and said undriven data bits to the predefined state.
15. The computer system of claim 10 wherein said interconnecting means includes a memory controller having means for constructing a ROM word having the first data width from a plurality of said merged data words.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/063,962 US6125467A (en) | 1998-04-21 | 1998-04-21 | Method and apparatus for partial word read through ECC block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/063,962 US6125467A (en) | 1998-04-21 | 1998-04-21 | Method and apparatus for partial word read through ECC block |
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| Publication Number | Publication Date |
|---|---|
| US6125467A true US6125467A (en) | 2000-09-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/063,962 Expired - Fee Related US6125467A (en) | 1998-04-21 | 1998-04-21 | Method and apparatus for partial word read through ECC block |
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| US (1) | US6125467A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050249010A1 (en) * | 2004-05-06 | 2005-11-10 | Klein Dean A | Memory controller method and system compensating for memory cell data losses |
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| CN100399287C (en) * | 2004-10-27 | 2008-07-02 | 威盛电子股份有限公司 | Data error check method and relative device |
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| US9098428B2 (en) * | 2012-12-11 | 2015-08-04 | Sandisk Technologies Inc. | Data recovery on cluster failures and ECC enhancements with code word interleaving |
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