US6110796A - Method of improving junction leakage problem of shallow trench isolation by covering said STI with an insulating layer during salicide process - Google Patents
Method of improving junction leakage problem of shallow trench isolation by covering said STI with an insulating layer during salicide process Download PDFInfo
- Publication number
- US6110796A US6110796A US09/268,883 US26888399A US6110796A US 6110796 A US6110796 A US 6110796A US 26888399 A US26888399 A US 26888399A US 6110796 A US6110796 A US 6110796A
- Authority
- US
- United States
- Prior art keywords
- insulating layer
- sti structure
- sti
- conductive region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
Definitions
- the invention relates in general to a method of improving junction leakage problem of shallow trench isolation (STI) structure, and more particularly to a method of improving junction leakage problem as STI and self-aligned silicide (Salicide) processes are performed.
- STI shallow trench isolation
- Integrated circuits are composed of many devices and isolation structures formed between the devices.
- the isolation structures such as STI structure or field oxide isolation structure, are used for preventing carriers moving between devices and reducing charge leakage problem.
- STI is currently employed in manufacturing IC devices, particularly in sub-half micron semiconductor process, to avoid the topographical uncertanties caused in using the more conventional thick field oxide isolation.
- the conventional growth of thermal field oxide using a mask such as nitride creates an encroachment of the oxide into the active areas, this encroachment being referred to as the bird's beak effect.
- STI When STI is used, it is common to use wet dip (or wet etching) for removing oxide. Trench sidewall of STI structure may accordingly exposed after wet oxide dip (or wet oxide etching) to result in recess effect on the upper surface of the trench sidewall, such as sidewall recess 16 as shown in FIG. 1. It is more serious for non-volatile products, such as flash memories, since the non-volatile products include many oxide layers. For example, there are at least tunnel oxide layer, silicon oxide/silicon nitride/silicon oxide (ONO) layer or several different gate oxide layers with different thickness formed in flash memories. Therefore, the wet oxide dip process will perform much more times during fabricating non-volatile products.
- wet oxide dip or wet etching
- Salicide process is used for reducing the resistance of conductive poly-silicon layer and wiring lines.
- the Salicide process comprises the steps of forming refractory metal layer on poly-silicon layer or silicon substrate, and performing thermal process to make the metal layer reacting with silicon to form metal silicide (salicide) on the poly-silicon layer or silicon substrate.
- metal silicide metal silicide
- a method of improving junction leakage problem as STI and self-aligned silicide (Salicide) processes comprises the following steps. First a silicon substrate is provided. A conductive region (such as a source/drain region) and a STI structure are formed in the substrate, wherein the conductive region connects to STI structure, and a sidewall recess is formed between the conductive region and STI structure to expose the substrate. An insulating layer is formed on STI structure, the sidewall recess and the conductive region. The preferred insulating layer is silicon oxide. The preferred thickness of the insulating layer is about 400 angstroms, which is thick enough to prevent penetration of metal ions formed during the Salicide process.
- a photoresist layer is formed and patterned on the insulating layer to cover STI structure and the periphery of STI structure.
- An etching process is performed on the insulating layer using the photoresist layer as a mask.
- the photoresist layer is removed.
- a Salicide process is performed on the insulating layer and the conductive region.
- FIGS. 1 to 4 are cross-sectional views showing a process flow of performing STI and Salicide processes of the invention.
- FIGS. 1 to 4 are cross-sectional views showing a process flow of performing STI and Salicide processes of the invention.
- a semiconductor substrate 10 is provided, such as silicon substrate.
- a MOS transister (not shown) and STI structure 14 are formed on the substrate 10.
- the MOS transister includes a gate (not shown) and a conductive region 12, such as a source/drain region formed in the substrate 10.
- the conductive region 12 connects to STI structure 14, and a sidewall recess 16 formed on the upper surface of the trench sidewall between the conductive region 12 and STI structure 14 to expose the substrate 10.
- the sidewall recess 16 is formed during forming STI structure 14 and the MOS transister.
- wet oxide dip or wet oxide etching
- Trench sidewall of STI structure 14 may accordingly exposed after wet oxide dip (or wet oxide etching) to result in recess effect on the upper surface of the trench sidewall to form such as sidewall recess 16 as shown in FIG. 1.
- a thin insulating layer 18 is formed on STI structure 14, the sidewall recess 16 and the conductive region 12.
- the method of forming the insulating layer 18 is preferably low pressure chemical vapor deposition (LPCVD) or sub-atmosphere pressure chemical vapor deposition (SACVD) using tetra-ethyl-ortho-siloxane (TEOS) as a source gas.
- LPCVD low pressure chemical vapor deposition
- SACVD sub-atmosphere pressure chemical vapor deposition
- TEOS tetra-ethyl-ortho-siloxane
- the preferred material of the insulating layer 18 is silicon oxide, and the preferred thickness of the insulating layer 18 is about 400 angstroms.
- the thickness of the insulating layer is preferably thick enough to prevent penetration of metal ions formed during the following Salicide process or metalization process.
- a photolithography process is performed on the insulating layer 18.
- a photoresist layer 20 is formed and patterned on the insulating layer 18 to cover STI structure 14 and the periphery of STI structure 14. That is, the photoresist layer 20 is patterned by exposing, developing and etching to cover STI structure 14 and part of the conductive region 12 which is located on the periphery of STI structure, as shown in FIG. 2.
- an anisotropic etching process is performed on the insulating layer 18 using the photoresist layer 20 as a mask, until the surface of the conductive region 12 is exposed. Then the photoresist layer 20 is removed.
- a Salicide process is performed on the insulating layer 18 and the conductive region 12 to form a metal silicide (salicide) layer 22 is on the conductive region 12 and the gate of the MOS transister (not shown).
- the method of forming the metal silicide (salicide) layer 22 includes the steps of forming a refractory metal layer, performing thermal process to make the metal layer reacting with silicon which is located below the metal layer, and removing the remained metal layer not reacting with silicon.
- the preferred metal layer is titanium (Ti).
- the salicide layer 22 is accordingly formed on the conductive region 12 and the gate of the MOS transister (not shown) but not formed on the insulating layer 18. Therefore, the salicide layer 22 is not formed on the sidewall recess 16, and the sidewall recess 16 is protected to eliminate junction leakage problem.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW88101193 | 1999-01-27 | ||
TW88101193 | 1999-01-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
US6110796A true US6110796A (en) | 2000-08-29 |
Family
ID=21639523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/268,883 Expired - Lifetime US6110796A (en) | 1999-01-27 | 1999-03-16 | Method of improving junction leakage problem of shallow trench isolation by covering said STI with an insulating layer during salicide process |
Country Status (1)
Country | Link |
---|---|
US (1) | US6110796A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6352897B1 (en) * | 1999-06-09 | 2002-03-05 | United Microelectronics Corp. | Method of improving edge recess problem of shallow trench isolation |
US20080274606A1 (en) * | 2005-03-29 | 2008-11-06 | Fujitsu Limited | Method of manufacturing semiconductor device |
US20090294809A1 (en) * | 2008-05-30 | 2009-12-03 | Kai Frohberg | Reduction of metal silicide diffusion in a semiconductor device by protecting sidewalls of an active region |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5405806A (en) * | 1994-03-29 | 1995-04-11 | Motorola Inc. | Method for forming a metal silicide interconnect in an integrated circuit |
US5434093A (en) * | 1994-08-10 | 1995-07-18 | Intel Corporation | Inverted spacer transistor |
US5561078A (en) * | 1992-03-09 | 1996-10-01 | Nec Corporation | Method of fabrication of semiconductor device |
US5780348A (en) * | 1997-07-14 | 1998-07-14 | United Microelectronics Corporation | Method of making a self-aligned silicide component |
US5989965A (en) * | 1998-02-13 | 1999-11-23 | Sharp Laboratories Of America, Inc. | Nitride overhang structures for the silicidation of transistor electrodes with shallow junction |
-
1999
- 1999-03-16 US US09/268,883 patent/US6110796A/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5561078A (en) * | 1992-03-09 | 1996-10-01 | Nec Corporation | Method of fabrication of semiconductor device |
US5405806A (en) * | 1994-03-29 | 1995-04-11 | Motorola Inc. | Method for forming a metal silicide interconnect in an integrated circuit |
US5434093A (en) * | 1994-08-10 | 1995-07-18 | Intel Corporation | Inverted spacer transistor |
US5780348A (en) * | 1997-07-14 | 1998-07-14 | United Microelectronics Corporation | Method of making a self-aligned silicide component |
US5989965A (en) * | 1998-02-13 | 1999-11-23 | Sharp Laboratories Of America, Inc. | Nitride overhang structures for the silicidation of transistor electrodes with shallow junction |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6352897B1 (en) * | 1999-06-09 | 2002-03-05 | United Microelectronics Corp. | Method of improving edge recess problem of shallow trench isolation |
US20080274606A1 (en) * | 2005-03-29 | 2008-11-06 | Fujitsu Limited | Method of manufacturing semiconductor device |
US7741185B2 (en) * | 2005-03-29 | 2010-06-22 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
US20090294809A1 (en) * | 2008-05-30 | 2009-12-03 | Kai Frohberg | Reduction of metal silicide diffusion in a semiconductor device by protecting sidewalls of an active region |
DE102008026214B3 (en) * | 2008-05-30 | 2010-01-28 | Advanced Micro Devices, Inc., Sunnyvale | Reduction of metal silicide diffusion in a semiconductor device by protecting sidewalls of an active area |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6274444B1 (en) | Method for forming mosfet | |
US5635746A (en) | Semiconductor device comprising a salicide structure | |
US6589842B2 (en) | Manufacturing method of a gate-split flash memory | |
US6060357A (en) | Method of manufacturing flash memory | |
JP3442596B2 (en) | Method for manufacturing semiconductor device | |
US6534405B1 (en) | Method of forming a MOSFET device featuring a dual salicide process | |
US6339001B1 (en) | Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist | |
US6740592B1 (en) | Shallow trench isolation scheme for border-less contact process | |
US20070155079A1 (en) | Gate structure of semiconductor device and method of manufacturing the same | |
US6624039B1 (en) | Alignment mark having a protective oxide layer for use with shallow trench isolation | |
US7084022B2 (en) | Method of manufacturing a semiconductor device including forming a pattern, an interlayer insulation film, exposing the patterning and flattening | |
US6110796A (en) | Method of improving junction leakage problem of shallow trench isolation by covering said STI with an insulating layer during salicide process | |
US6800525B2 (en) | Method of manufacturing split gate flash memory device | |
US7316970B2 (en) | Method for forming high selectivity protection layer on semiconductor device | |
US5923988A (en) | Two step thermal treatment procedure applied to polycide structures deposited using dichlorosilane as a reactant | |
US6635537B2 (en) | Method of fabricating gate oxide | |
JPH06151783A (en) | Method for manufacturing semiconductor device | |
KR100327428B1 (en) | Method for forming a semiconductor device | |
US6110801A (en) | Method of fabricating trench isolation for IC manufacture | |
US6150072A (en) | Method of manufacturing a shallow trench isolation structure for a semiconductor device | |
US20090098735A1 (en) | Method of forming isolation layer in semicondcutor device | |
US6372615B2 (en) | MOSFET and fabrication method thereof | |
US6281143B1 (en) | Method of forming borderless contact | |
TWI877861B (en) | Memory device and method for forming the same | |
US6403428B1 (en) | Method of forming shallow trench isolation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNITED INTEGRATED CIRCUITS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SUNG, KUO-TUNG;REEL/FRAME:009831/0655 Effective date: 19990224 |
|
AS | Assignment |
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNITED INTEGRATED CIRCUITS CORP.;REEL/FRAME:010579/0500 Effective date: 19991230 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |