US5892961A - Field programmable gate array having programming instructions in the configuration bitstream - Google Patents

Field programmable gate array having programming instructions in the configuration bitstream Download PDF

Info

Publication number
US5892961A
US5892961A US08920738 US92073897A US5892961A US 5892961 A US5892961 A US 5892961A US 08920738 US08920738 US 08920738 US 92073897 A US92073897 A US 92073897A US 5892961 A US5892961 A US 5892961A
Authority
US
Grant status
Grant
Patent type
Prior art keywords
data
register
configuration
array
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08920738
Inventor
Stephen M. Trimberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17776Structural details of configuration resources for speeding up configuration or reconfiguration
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources

Abstract

A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes the programming instructions to efficiently load configuration data into the configuration memory array. For instance, configuration data can be temporarily stored in the CPU and reused where data patterns in the configuration memory array repeat. Use of the programmable CPU for loading the configuration memory array reduces the amount of data transmitted to the FPGA during array configuration.

Description

This application is a continuation of application Ser. No. 08/389,846, filed Feb. 17, 1995 , now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to gate arrays, and more particularly to a field programmable gate array in which programming instructions are carried by the configuration bitstream and executed by a CPU in the logic cell array.

2. Description of the Background Art

Digital logic can be implemented using several options: discrete logic devices, often called small-scale integrated circuits or SSI, programmable devices such as programmable logic arrays (PLAs) or programmable logic devices (PLDs), masked-programmed gate arrays or cell-based application specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs).

FPGAs are general purpose programmable devices that are customized by the end users. FPGAs are composed of an array of configurable logic blocks that are programmably interconnected. The basic device architecture of an FPGA consists of an array of configurable logic blocks (CLBs) embedded in a configurable interconnect structure and surrounded by configurable I/O blocks (IOBs). An IOB allows signals to be driven off-chip or optionally brought into the FPGA. The IOB can typically perform other functions, such as tri-stating outputs and registering incoming or out-going signals. The configurable interconnect structure allows users to implement multi-level logic designs (multi-level refers to logic in which the output signal of one logic unit provides input to another logic unit and the output of that provides input to another, etc.). An FPGA can support tens of thousands of gates of logic operating at system speeds of tens of megahertz. The FPGA is programmed by loading programming data into the memory cells controlling the configurable logic blocks, I/O blocks, and interconnect structure. Further information about FPGAs appears in "The Programmable Logic Data Book", copyright 1994 by Xilinx, Inc. and available from Xilinx, Inc. at 2100 Logic Drive, San Jose, Calif. 95124, which is incorporated herein by reference.

Each configurable logic block in the FPGA can include configuration memory cells for controlling the function performed by that logic block. These configuration memory cells can implement a lookup table, control multiplexers, and control other logic elements such as XOR gates and AND gates. A lookup table stores a truth table which implements that combinational logic function corresponding to the truth table. Each configurable logic block may also be defined to include an adjacent portion of the interconnect structure. The interconnect structure includes programmable interconnect points which control the connection of wiring segments in the programmable interconnect network of the FPGA. Each programmable interconnect point may be a pass transistor controlled by a configuration memory cell. Wire segments on each side of the pass transistor are either connected or not connected depending on whether the transistor is turned on by the corresponding configuration memory cell. The multiplexer is a special-case one-directional routing structure that is controlled by a configuration memory cell. Although the multiplexer can be any width, controlling multiplexers with many inputs will require additional configuration memory cells. Switches that are built using multiplexers require fewer configuration memory cells than the number of multiplexer inputs.

Configuration is the process of loading a bitstream containing the program data into the configuration memory cells which control the configurable logic blocks and I/O blocks of the FPGA. The bitstream is loaded into the FPGA serially to minimize the number of pins required for configuration and to reduce the complexity of the interface to external memory. The bitstream is broken into packets of data called frames. As each frame is received, it is shifted through a frame register until the frame register is filled. The data in the frame register of the FPGA are then loaded in parallel into one row of configuration memory cells forming the memory array. (The configuration memory cells which control a configurable logic block typically occupy a two dimensional section of the array.) The configuration memory cells make up the lookup tables and control the programmable interconnect points, multiplexers, and other programmable elements of a configurable logic block or I/O block. Following the loading of the first frame, subsequent frames of bitstream data are shifted into the FPGA, and another row of configuration memory cells in the array of CLBs is designated to be loaded with a frame of bitstream data.

A limitation on the speed at which configuration of the FPGA occurs is the serial loading of the bitstream into the FPGA. This configuration bitstream bottleneck has become increasingly apparent as the number of configuration bits has increased from thousands to tens and hundreds of thousands of bits over the past several years. This dramatic increase in FPGA size has resulted in a corresponding increase in the time required for configuration and reconfiguration. As the bitstream length increases in the future to millions of bits and beyond, an alternative method of loading bitstream data must be developed. What is needed is a method and system for efficiently loading bitstream data into an FPGA for rapid configuration and reconfiguration of the memory cell array.

SUMMARY OF THE INVENTION

In accordance with the present invention, the bitstream includes programming instructions in order to reduce the number of data bits which must be transferred into the FPGA. An encoded bitstream is intercepted by a central processing unit (CPU), prior to the bitstream data being loaded into the frame register. These instructions encoded in the bitstream cause the CPU to perform data operations on a frame before the frame data is loaded into the configuration memory, and thereby enable efficient loading of the configuration memory array. For example, data from the encoded bitstream may be loaded into several locations in the configuration memory without having to be repeated in the encoded bitstream, or data may be moved from one location in the configuration memory to another without having to be present in the bitstream.

The processor contains a configurable logic block (CLB) register, for use by the processor as a temporary storage area. This CLB register enables local storage of repetitively used bitstream segments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a simplified section of a field programmable gate array architecture of the prior art, outlining the layout of programming registers that are used for programming the field programmable gate array;

FIG. 2 depicts the field programmable gate array architecture of the present invention, outlining the layout of configuration registers and the CPU;

FIG. 3 depicts a table containing exemplary instructions used in programming the CPU of the present invention;

FIG. 4 depicts a schematic representation of the CPU architecture of the present invention;

FIG. 5 depicts a detailed circuit block diagram illustrating the architectural components of the length data path logic of FIG. 4;

FIG. 6 depicts a circuit block diagram detailing the architectural configuration of the bits data path logic of FIG. 4; and

FIG. 7 depicts a circuit block diagram illustrating architectural details of the control state machine of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, an overview diagram is shown depicting the architecture of a conventional Logic Cell Array (LCA) 10 field programmable gate array (FPGA). Configuration memory array 12 consists of a matrix of memory cells 25 which function, among other things, as look-up table memory and routing selectors in the implementation of FPGA logic. A detailed description of the organization of the configuration memory array 12 can be found in the Programmable Logic Data Book, pages 2-105 to 2-132, published by Xilinx, Inc., 1994. The matrix of memory cells 25 is organized in regular discrete arrays of discrete Configurable Logic Blocks 18 (CLBs). The CLB's 18 of configuration memory array 12 are shown as 3×5 arrays of memory cells 25. In an actual FPGA the CLB is generally much larger than 3×5 memory cells 25. The CLBs 18 are bounded on all four sides by input/output blocks (IOBs) 22. The IOBs 22 communicate data between external pins (not shown) of the FPGA and the CLBs 18. Corner logic blocks 24 are located in each of the four corners of the configuration memory array 12. The corner logic blocks 24 perform special functions and will be discussed further with reference to FIG. 4 below. Loading of data into configuration memory array 12 is performed from a frame register 14, shown in FIG. 1 above the configuration memory array 12, and connected to the configuration memory array 12 by connect lines 13. Frame register 14 is a conventional serial shift register which receives and sequentially clocks bitstream 17 into the frame register 14 from left to right.

The CLBs 18 and IOBs 22 are configured by shifting bitstream 17 into frame register 14 and then loading the contents of frame register 14 in parallel into rows of the memory array 12. In order to facilitate the parallel loading of bitstream 17 from frame register 14 into a row of the memory array 12, a row pointer 19 in shift register 16 points sequentially to each row such as rows 21, 23. Shift register 16 consists of a sequential series of pointer cells 20, each storing a logic "0", with the exception of one bit storing a logic "1" which is referred to as the row pointer 19. The row pointer 19 shifts sequentially through the shift register 16 starting from the bottom cell 26 to sequentially load the contents of the configuration memory array 12 on a row-by-row basis. For example, during loading of the configuration memory array 12, row pointer 19 will at some point be addressing row 21. Pointer 19 causes the data in frame register 14 to be loaded into row 21. Following the loading of the contents of frame register 14 into row 21, the row pointer 19 shifts up one pointer cell 20 and points to row 23 of the configuration memory array 12. With row pointer 19 addressing row 23, frame register 14 sequentially shifts in a new frame of bitstream 17, and once the frame register 14 is completely loaded, the contents of frame register 14 is loaded in parallel to row 23 of the memory array 12. In this manner, each of the rows of configuration memory array 12 is sequentially loaded with a frame of bitstream 17.

FPGA Architecture

Referring now to FIG. 2, one embodiment of the present invention is shown, in which encoded bitstream 27 is received by a Central Processing Unit (CPU) 40 for decoding. In contrast to the conventional bitstream 17 (FIG. 1), which is comprised of a series of data bits for direct loading into frame register 14, the encoded bitstream 27 of the present invention consists of a sequence of programming instructions combined with configuration data. These instructions comprising the encoded bitstream 27 enable the CPU 40 to load the frame register 14 via frame data path 41. Frame data path 41 is a data path connecting CPU 40 to the frame register 14. Frame data path 41 carries frames of bitstream data used in configuring the CLB's 18. Use of the CPU 40 enables a single instruction carried in the encoded bitstream 27 to perform multiple repetitive or common data-loading tasks with respect to configuration memory array 12. For instance, an instruction which might be executed on the configuration memory array 12 would be to load the entire configuration memory array with logic "1's." To perform this task using conventional techniques, a bit containing a logic "1" would need to be transmitted to the FPGA for each memory cell 25 contained in the configuration memory array 12. Depending on the size of the FPGA, this might require the transfer of tens or hundreds of thousands of bits. Using the CPU 40 of the present invention, a single instruction such as CLR, containing only a few bits, can notify CPU 40 to clear the entire configuration memory array by loading logic "1's" into each of the memory cells 25. The CPU 40 then generates a sequence of "1's" equal to the length of the frame register 14 and transmits the sequence along frame data path 41 to the frame register 14. The contents of the frame register 14 is then transmitted into the configuration memory array 12, as discussed with respect to FIG. 1 above. For each row that is loaded by the frame register 14, the CPU 40 sends a signal along control bus 115 to the shift register 16 to sequentially increment the frame pointer 19 after each row 21 is loaded into the configuration memory array 12. Alternatively, if CPU 40 loads 1's into all rows of shift register 16, all rows of configuration memory 12 are cleared simultaneously. From this simple example, it can be seen that through the use of programming instructions transmitted in the encoded bitstream 2, CPU 40 can greatly improve the transfer efficiency of data to the FPGA and into the configuration memory array 12.

As an alternative example, the requirement of the FPGA may be to load each CLB 18 of the configuration memory array 12 with the same data set. In this case, an instruction and the CLB data are transmitted via encoded bitstream 27 instructing CPU 40 to load all CLBs 18 with a single set of CLB data. Using this instruction, CPU 40 generates appropriate data for each row of each of the CLBs 18 and loads this data into the configuration memory array 12. Using conventional bitstream formats, the loading of all the CLBs in the configuration memory array would have required transmission to the FPGA of a data stream equal to the size of the configuration memory array 12. Using the present invention, only a single instruction, along with the data required to load a single CLB 18, need be transmitted. The CPU 40 can then generate data for frame register 14 for loading into the CLBs 18.

Referring now to FIG. 3, a table 29 is shown identifying a list of example operation codes (OPCODE) 31 (CPU instructions) and their respective instruction definitions (INSTRUCTION 33), which may be used with the CPU 40 of the present invention. The first opcode 31 listed in FIG. 3 is LF, which represents the instruction Load Frame Immediate. The function of the LF instruction is to load the configuration data contained in the encoded bitstream 27 immediately following the instruction into the frame register 14. In decoding this instruction, the CPU 40 reads a data word immediately following the instruction from the encoded bitstream 27, and loads the data word onto the frame data path 41 for transfer into the frame register 14. The contents of the frame register 14 may then be loaded into the row of configuration memory array 12 pointed to by frame pointer 19, using the WR X instruction.

The second example opcode 31 listed in FIG. 3 is LFN N, which is shorthand notation for Load N bits into the frame register 14. The preferred implementation of this instruction results in CPU 40 reading some number (N) of bits from the encoded bitstream 27, and loading these N bits onto the frame data path 41. These N bits are then transferred into the frame register 14, as determined by CPU 40.

The third example instruction in the table 29 of FIG. 3 is the opcode 31 instruction WR X, which stands for Program Row X. The function of WR X is to load the contents of frame register 14 into a specific row 21, designated by address X. Using this instruction, the row pointer 19 can be set as discussed below with reference to FIG. 7, and the CPU 40 can then load a specific row 21. By sending multiple repetitive WR X commands, a single frame register can efficiently load multiple rows, as identified by the various addresses defined by the X attribute.

The fourth example command, RD X, instructs the CPU 40 to read a specific row X into frame register 14. This command is useful in combination with WR X, in that a single row X can be read into frame register 14 and then subsequently written into a different row.

The next example instruction shown in FIG. 3 is RB, which stands for Read Back the frame register 14. The RB command instructs CPU 40 to shift the contents of the frame register 14 outward to the right to a designated output pin (not shown) on the FPGA. This may be used to check the contents of the data stored in the configuration memory array 12.

The last example instruction shown in FIG. 3 is Jump XX. The Jump XX instruction enables the CPU 40 to control the addressing of memory external (not shown) to the FPGA. The CPU sends a signal to the external memory to instruct the memory to begin sending encoded bitstream 27 data beginning at memory location XX in external memory. In an alternative embodiment, the Jump XX instruction may be executed conditionally, based on the contents of an internal register. This Jump XX instruction is discussed in more detail with reference to FIG. 7 below.

These exemplary instructions of FIG. 3 are listed only to illustrate the functional capability of CPU 40, and are in no way intended to define the limits or represent the totality of possible instructions which the CPU 40 can implement. It will be obvious to those skilled in the art that a wide range of possible instructions could be equivalently used to manipulate data and control data flow into and out of configuration memory array 12.

CPU Description

Referring now to FIG. 4, a circuit block diagram is shown illustrating the architectural overview of the CPU 40. CPU 40 contains three major structures: length data path logic 101, bits data path logic 121, and control state machine 141. The function of each of the components (101, 121, and 141) of the CPU 40 will be discussed in detail with reference to the figures that follow. CPU 40 receives encoded bitstream 27 into length data path logic 101, the bits data path logic 121, or the control state machine 141, as determined by logic in the control state machine 141. The function of the length data path logic 101 is to store values, to count numbers of bits, to read data bits serially into internal registers and to count various other events in the execution of CPU 40 instructions. Bits data path logic 121 receives the encoded bitstream 27 and sequentially shifts the encoded bitstream 27 to the frame register 14 along frame data path 41. Control state machine 141 also receives encoded bitstream 27; decodes the opcode commands from the encoded bitstream 27; and provides control signals to the various components of the CPU 40, into the frame register 14, and configuration memory array 12. Control state machine 141 also provides a next instruction address 152 which is routed off-chip of the FPGA and used to control memory logic, as in the Jump XX command discussed above. Control state machine 141 communicates with the length data path logic 101 through the frame data bus 109 and a control bus 110. Communication between the control state machine 141 and the bits data path logic 121 is performed through control bus 130. Communication between the control state machine 141 and the frame register 14 occurs through control bus 113, and communication between the control state machine 141 and the configuration memory array 12 is through control bus 115.

Referring now to FIG. 5, a detailed circuit block diagram is shown illustrating the architectural components of length data path logic 101. Encoded bitstream 27 is received by a user count register 102 in a bit-serial fashion. The user count register 102 stores the bits, and in response to signals from control bus 110, can transfer the data in parallel to temporary register 107 or to accumulator 104 via data bus 109. The transfer of data from the encoded bitstream 27 into the user count register 102 is enabled by control state machine 141 via user count enable line 144. User count enable line 144 carries one of several control signals originating from the control state machine 141 and transmitted to the length data path logic 101 via control bus 110.

Length data path logic 101 contains an array of memory locations identified as constant registers 103. These constant registers 103 contain a plurality of stored constants which are used by control state machine 141 in counting constant data and field lengths. Examples of data which may be contained in constant registers 103 include the constants "0" and "1" as well as the length of a prescribed data field, the length in bits of the frame register 14, and the size of a standard CLB 18 (FIG. 1). In the preferred embodiment, the content of the constant register 103 is programmed as fixed memory; however, one skilled in the art would recognize that this constant register 103 can be constructed using dynamic read/write memory, thus enabling the register to be programmed and dynamically updated with a variety of constant values.

The length data path logic 101 also contains a register called the accumulator 104 which is connected to the frame data bus 109. One or more temporary registers 107 may optionally be used with the length data path logic 101 to serve as temporary storage locations for specific instruction commands. A conventional Arithmetic Logic Unit (ALU) 105, also connected to the frame data bus 109, receives input from the accumulator 104 to provide arithmetic logic results to frame data bus 109. Results may be stored back in accumulator 104 or in the temporary register 107. Constant register 103, accumulator 104 and temporary register 107 are all enabled by control bus 110. The ALU 105 receives a length data path operation signal 140 from the control state machine 141. The length data path operation signal 140 controls the arithmetic function to be performed by the ALU 105. A length data path source signal 143 controls and selects which of the signals of the length data path logic 101 has access to the frame data bus 109. A length data path destination signal 145 controls which of the elements of the length data path logic 101 is addressed by the frame data path 109. For example, the length data path destination signal might control the frame data path 109 to write data to the ALU 105, but not the accumulator 104 or the temporary register 107. The ALU 105 further generates an A=0 signal 165 when the value of the accumulator is equal to zero. This A=0 signal 165 is useful, for instance, for detecting when a decrement operation being performed by the ALU 105 is completed.

Referring now to FIG. 6, a circuit block diagram is shown detailing the architectural configuration of the bits data path logic 121. As stated above, the function of the bits data path logic 121, is to transfer data from the encoded bitstream 27 to frame register 14. Bits data path logic 121 principally comprises a multiplexer 114 which selects from among several data sources in response to a multiplexer control signal 148 from control bus 130. Control bus 130 originates from the control state machine 141. A first register 122 and second register 123 are two of the data sources received by the multiplexer 114. The first register 122 and the second register 123 enable the CPU 40 to generate a stream of values to be loaded into the frame register 14 by selectively reading from each of the registers 122, 123 in response to multiplexer control signal 148 sent via control bus 130. Encoded bitstream 27 also has a direct path through multiplexer 114 to frame data path 41. Alternatively, frame data path 41 can connect through the multiplexer 114 to a CLB data register 117 or an optional register A 119. CLB data register 117 and register A 119 are identical in structure and operation. CLB data register 117 is a sequential shift register into which data is loaded from encoded bitstream 27.

To load all CLB's 18 (FIG.2) in a row 21 identically from the encoded bitstream 27, the control state machine 141 sends a CLB data select signal 161 via the control bus 130 to the CLB data register 117. A block of data is then loaded into the CLB data register 117 from the encoded bitstream 27. Once the CLB data is loaded into the CLB data register 117, the entire block of CLB data contained in CLB register 117 can be repetitively shifted through multiplexer 114 along frame data path 41. Cycling (also known in the art as data recirculation) of the CLB data into the CLB data register 117 is achieved by controlling multiplexer 116 to select the feedback signal which comes from output line 124 of CLB data register 117. As data shifts out of CLB data register 117 to frame data path 41, the same CLB data register output 124 cycles back to the input 120 of the CLB data register 117 to create a data loop. Once the entire contents of the sequential CLB data register 117 has been shifted out, the contents of the CLB data register has again been loaded into the CLB data register 117 and is ready for re-use. In the same way register A 119 has a multiplexer 118 controlled by a register A data enable 148 signal, originating from the control bus 130, and can also be used to recycle data. The register A is enabled from the control state machine 141 by register A data select 162.

Referring now to FIG. 7, a circuit block diagram is shown illustrating architectural details of the control state machine 141. The control state machine receives encoded bitstream 27 into an opcode register 142. An opcode is stripped from the encoded bitstream 27 and transferred to decoder logic 138 along opcode data path 139. The structure of decoder logic 138 is conventional, and may be implemented as combinational or sequential digital logic or in software. The decoding of the opcode in decoder logic 138 results in the production of a variety of control signals (140, 143-156, 161, 162). Among the control signals produced in decoder logic 138, is an opcode enable signal 151 which is used to enable the loading of an opcode from the opcode register 142 to the opcode decoder logic 138. The length data path operation 140, length data path source 143, user count enable 144, and length data path destination 145 signals are all carried on the control bus 110, which is transmitted to the length data path logic 101 (FIG. 5). The CLB data enable 146, register A data enable 147, frame data select 148, CLB data select 161, and register A data select 162 signals are carried on the control bus 130, which is used in the operation of the bits data path logic 121 (FIG. 6).

Frame readback enable 150, readback enable 149, and frame shift signal 153 are combined to produce control bus 113 which connects the control state machine 141 to the frame register 14 as shown in FIG. 4. Frame parallel load 154, configuration data read 155, and configuration data write 156, combine to produce control bus 115 which connects control state machine 141 to the configuration memory array 12 as also shown in FIG. 4. The frame parallel load 154 signal directs the shift register 16 to load a new value from the configuration memory array 12. The configuration data read signal 155 controls the writing of configuration data from the configuration memory array 12 to the frame register 14. The configuration data write signal 156 controls the writing of configuration data from the frame register 14 to the configuration memory array 12. A next instruction address 152 signal is produced and transmitted off the chip to control memory logic (not shown) in support of the FPGA. The next instruction address 152 signal is used in the Jump XX instruction, as discussed above with reference to FIG. 3.

Instruction Processing

The CPU has two data paths (the length data path 101 and the bits data path 121) and a control state machine 141. Encoded bitstream 27 is initially shifted serially into the opcode register 142 of the control state machine 141. The contents of the opcode register 142 are then decoded to control the direction of subsequent bits in the encoded bitstream 27.

When the LF instruction (FIG. 3) is decoded in the opcode register 142, the control state machine 141 performs the following functions:

i) The length data path destination 145 signal is set to load the accumulator 104 with a value from the frame size constant register 103 representing the number of bits in a bitstream frame.

ii) The frame data select 148 signal is set to control the multiplexer 114 to select the encoded bitstream 27 as an input, and to pass the encoded bitstream 27 along the frame data path 41 to the frame register 14.

iii) The frame shift 153 signal is set to enable the frame register 14 to accept data from the frame data path 41.

iv) The length data path logic 101 ALU 105 is set to decrement the input value received from the accumulator 104. The instruction for the ALU 105 to decrement is provided by the length data path operation signal 140 from the control state machine 141. The length data path source 143 selects the ALU 105, and the length data path destination 145 puts the result back into the accumulator 104. The frame register 14 passes data until an A=0 signal 165 is received from the length data path logic 101 ALU 105.

v) When the A=0 signal 165 is received by the control state machine 141, the control state machine 141 stops passing data into the frame register 14 and sets the opcode enable 151 signal to begin loading another opcode into the opcode register 142.

When the LFN instruction (FIG. 3) is decoded in the opcode register 142, the control state machine 141 performs the following functions:

i) The length field constant from the constant register 103 is loaded into the accumulator 104 of the length data path logic 101;

ii) The user count enable 144 signal is set to direct the encoded bitstream 27 into the user count register 102;

iii) The length data path logic 101 ALU 105 is set to decrement the input value received from the accumulator 104. The length data path source 143 signal selects the ALU 105, and the length data path destination 145 signal puts the result back into the accumulator 104. The frame register 14 passes data until an A=0 signal 165 is received from the length data path logic 101 ALU 105.

iv) The control state machine 141 waits for receipt of an A=0 signal 165 from the ALU 105, indicating that all bits have been loaded into the user count register 102.

v) The accumulator 104 is loaded with the contents of the user count register 102.

vi) The frame data select 148 signal is set so that multiplexer 114 selects the encoded bitstream 27 as an input, and passes the encoded bitstream 27 along frame data path 41 to the frame register 14.

vii) The frame shift signal 153 is set to allow the frame register 14 to accept the frame data 41.

viii) The length data path ALU 105 is set to decrement the input value received from the accumulator 104. The length data path source 143 selects the ALU, and the length data path destination 145 puts the result back into the accumulator 104. The frame register 14 passes data until an A=0 signal 165 is received from the length data path logic 101 ALU 105.

ix) Multiplexer 114 continues to pass data until an A=0 signal 165 is received from the length data path logic 101 ALU 105.

x) When the A=0 signal 165 is received, the control state machine 141 stops transferring data to the frame register 14 and sets the opcode enable 151 signal to begin loading another opcode into the opcode register 142.

When the WR instruction is decoded in the opcode register 142, the control state machine 141 performs the following functions:

i) The accumulator 104 is loaded with the length field constant from the constant register 103.

ii) The user count enable 144 signal is set to direct the encoded bitstream 27 into the user count register 102.

iii) The length data path logic 101 ALU 105 is set to decrement the input value received from the accumulator 104. The length data path source 143 selects the ALU 105 and the length data path destination 145 puts the result back into the accumulator 104. The frame register 14 passes data until an A=0 signal 165 is received from the length data path logic 101 ALU 105.

iv). The control state machine 141 waits for receipt of an A=0 signal 165 from the ALU 105 indicating that all bits from the encoded bitstream 27 have been loaded into the user count register 102.

v) The frame parallel load signal 154 is set which directs the shift register 16 to load a new value.

vi) When the shift register 16 has the new value, the control state machine 141 sets the configuration data write 156 signal to allow the data in the frame register 14 to be loaded into the configuration memory array 12.

vii) The opcode enable 151 signal is set to begin loading another opcode into the opcode register 142.

When the RD instruction is decoded in the opcode register 142, the control state machine 141 performs the following functions:

i) The frame parallel load 154 signal and the configuration data read signal 155 are set to allow one frame of configuration data to be loaded into the frame register 14 from the configuration memory array 12.

ii) When the frame register 14 contains the data from the configuration memory array 12, the control state machine 141 sets the readback enable signal 149 which directs the frame register 14 to shift its contents out of an off-chip readback pin (not shown).

iii) When the frame bits have been shifted out of the off-chip readback pin, the opcode enable 151 signal is set to begin loading another opcode into the opcode register 142.

When the JMP instruction is decoded in the opcode register 142, the control state machine 141 performs the following functions:

i) The accumulator 104 is set with the length field constant from the constant register 103.

ii) The user count enable signal 144 is set to direct the encoded bitstream 27 into the user count register 102.

iii) The length data path logic 101 ALU 105 is set to decrement the input value received from the accumulator 104. The length data path source 143 selects the ALU 105, and the length data path destination 145 puts the result back into the accumulator 104. The frame register 14 passes data until an A=0 signal 165 is received from the length data path logic 101 ALU 105.

iv) When the A=0 signal 165 is received by the control state machine 141, indicating that all bits have been loaded into the user count register 102, the next instruction address 152 signal is set which directs the contents of the user count register 102 to be transferred to the bitstream instruction address pin (not shown).

vi) The external memory (not shown) then begins sending data from the new address.

vii) The opcode enable 151 signal is set to begin loading another opcode into the opcode register 142.

Claims (30)

What is claimed is:
1. A programmable gate array comprising:
a bitstream comprising a combination of configuration data and programming instructions;
a processor coupled to the bitstream for separating the configuration data from the programming instructions and for executing the programming instructions and having
a control state machine coupled to receive the configuration bitstream for decoding programming instructions and providing control signals; and
an arithmetic logic unit coupled to receive a control signal from the control state machine and for performing arithmetic functions in response to programming instructions in the bitstream; and
a memory array having a plurality of memory cells for receiving and storing configuration data transmitted from the processor.
2. The programmable gate array according to claim 1 in which the processor generates a plurality of control signals in response to the programming instructions.
3. The programmable gate array according to claim 2 in which the memory stores configuration data responsive to at least one of the control signals generated by the processor.
4. The programmable gate array of claim 1, further comprising, an accumulator register coupled to receive data from the arithmetic logic unit and provide data to the arithmetic logic unit.
5. A programmable gate array that is programmable with a bitstream having a combination of configuration data and programming instructions, comprising:
a memory array having a plurality of memory cells for storing configuration data;
a frame register coupled to the memory array for receiving configuration data from the bitstream and transferring the configuration data to the memory array; and
a processor coupled to the frame register for controlling the transfer of configuration data to the memory array, the processor being responsive to programming instructions in the bitstream and having
a control state machine coupled to receive the bitstream for decoding the programming instructions in the bitstream and providing control signals; and
an arithmetic logic unit coupled to receive a control signal from the control state machine for performing arithmetic functions in response to the programming instructions in the bitstream.
6. The programmable array according to claim 5 further comprising a shift register coupled to the processor for addressing rows of the memory array in which each cell of the shift register stores a row pointer identifying a row to be addressed.
7. The programmable array according to claim 5 further comprising a data bus for coupling the processor to the frame register.
8. The programmable array according to claim 7, wherein the data bus carries addressing, configuration and control data.
9. The programmable array according to claim 5 wherein the memory array further comprises memory cells organized as a plurality of configurable logic blocks.
10. The programmable array according to claim 9 wherein the processor further comprises a memory for use in temporarily storing configurable logic block data during gate array logic configuration.
11. The programmable array according to claim 10 wherein the processor further comprises logic for identifying and decoding programming instructions.
12. The programmable array according to claim 5 wherein configuration data is loaded into the frame register under the control of the processor.
13. The system of claim 5, further comprising, an accumulator register coupled to receive data from the arithmetic logic unit and provide data to the arithmetic logic unit.
14. The programmable gate array of claim 5, wherein the processor has means for loading a variable number of bits into the frame register in response to one or more of the programming instructions.
15. The programmable gate array of claim 5, wherein the processor has means for reading an addressable row of data from the memory array into the frame register in response to one or more of the programming instructions.
16. The programmable gate array of claim 5, wherein the processor has means for transmitting data from the frame register to a data output terminal of the programmable gate array in response to an instruction.
17. The programmable gate array of claim 5, wherein the processor has means for transmitting an instruction address received from the bitstream to an instruction address output terminal of the programmable gate array in response to an instruction.
18. The system of claim 5, wherein the processor has
means for transmitting an instruction address received from the bitstream to an instruction address output terminal of the programmable gate array in response to an instruction;
means for reading an addressable row of data from the memory array into the frame register in response to an instruction
means for transmitting data from the frame register to a data output terminal of the programmable gate array in response to an instruction; and
means for loading a variable number of bits into the frame register in response to an instruction.
19. An apparatus for configuring the configuration memory array of a field programmable gate array (FPGA) comprising:
means for encoding gate array configuration data with programming instructions to produce encoded bitstream data;
means for transferring bitstream data to the FPGA;
means for receiving the bitstream data into a CPU on the FPGA; and
means for performing arithmetic functions to configure the FPGA in response to programming instructions in the bitstream.
20. The apparatus for configuring the configuration memory array of a field programmable gate array (FPGA) according to claim 19, the apparatus further comprising means for decoding the bitstream data to separate the programming instructions from the configuration data.
21. The apparatus for configuring the configuration memory array of a field programmable gate array (FPGA) according to claim 19, the apparatus further comprising means for selectively transferring configuration data from the CPU to the configuration memory array responsive to the programming instructions.
22. The apparatus for configuring the configuration memory array of a field programmable gate array (FPGA) according to claim 19 wherein the CPU comprises means for temporarily storing configuration data.
23. A method for configuring the configuration memory array of a field programmable gate array (FPGA), the method comprising the steps:
encoding gate array configuration data with programming instructions to produce encoded bitstream data;
transferring bitstream data to the FPGA;
receiving the bitstream data into a CPU on the FPGA;
decoding the bitstream data to a separate the programming instructions from the configuration data; and
performing arithmetic functions to configure the FPGA in response to programming instructions in the bitstream.
24. The method for configuring the configuration memory array of a field programmable gate array (FPGA) according to claim 23, the method further comprising the step of selectively transferring configuration data from the CPU to the configuration memory array responsive to the programming instructions.
25. The method for configuring the configuration memory array of a field programmable gate array (FPGA) according to claim 23, wherein the FPGA further comprises a frame register coupled between the CPU and the configuration memory for temporarily storing configuration data transferred from the CPU to the configuration memory array.
26. The method for configuring the configuration memory array of a field programmable gate array (FPGA) according to claim 23, wherein the frame register is controlled by the CPU.
27. The method for configuring the configuration memory array of a field programmable gate array (FPGA) according to claim 23, wherein the FPGA further comprises a shift register coupled between the CPU and the configuration memory for addressing specific rows of the configuration memory.
28. The method for configuring the configuration memory array of a field programmable gate array (FPGA) according to claim 23, wherein row addressing of the shift register is controlled by the CPU.
29. A programmable gate array, comprising:
a processor having an input port for receiving a bitstream, the bitstream having configuration data and programming instructions, the processor for separating the configuration data from the programming instructions and executing the programming instructions, and the processor having
a control state machine coupled to receive the configuration bitstream for decoding programming instructions and providing control signals; and
an arithmetic logic unit coupled to receive a control signal from the control state machine and for performing arithmetic functions in response to programming instructions in the bitstream; and
a memory array having a plurality of memory cells for receiving and storing configuration data transmitted from the processor.
30. The programmable array according to claim 6 further comprising a shift register coupled to the processor for addressing rows of the memory array.
US08920738 1995-02-17 1997-08-29 Field programmable gate array having programming instructions in the configuration bitstream Expired - Lifetime US5892961A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US38984695 true 1995-02-17 1995-02-17
US08920738 US5892961A (en) 1995-02-17 1997-08-29 Field programmable gate array having programming instructions in the configuration bitstream

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08920738 US5892961A (en) 1995-02-17 1997-08-29 Field programmable gate array having programming instructions in the configuration bitstream

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US38984695 Continuation 1995-02-17 1995-02-17

Publications (1)

Publication Number Publication Date
US5892961A true US5892961A (en) 1999-04-06

Family

ID=23539981

Family Applications (1)

Application Number Title Priority Date Filing Date
US08920738 Expired - Lifetime US5892961A (en) 1995-02-17 1997-08-29 Field programmable gate array having programming instructions in the configuration bitstream

Country Status (1)

Country Link
US (1) US5892961A (en)

Cited By (141)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026481A (en) * 1995-04-28 2000-02-15 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
US6097988A (en) * 1998-02-10 2000-08-01 Advanced Micro Devices, Inc. Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US6405299B1 (en) * 1997-02-11 2002-06-11 Pact Gmbh Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US6425068B1 (en) 1996-12-09 2002-07-23 Pact Gmbh Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)
US6445205B1 (en) * 1998-11-26 2002-09-03 Telefonaktiebolaget Lm Ericsson Method of testing integrated circuits
US20020138716A1 (en) * 2001-03-22 2002-09-26 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US6477643B1 (en) 1996-12-27 2002-11-05 Pact Gmbh Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US6480937B1 (en) 1998-02-25 2002-11-12 Pact Informationstechnologie Gmbh Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--
US20020184291A1 (en) * 2001-05-31 2002-12-05 Hogenauer Eugene B. Method and system for scheduling in an adaptable computing engine
US20020181559A1 (en) * 2001-05-31 2002-12-05 Quicksilver Technology, Inc. Adaptive, multimode rake receiver for dynamic search and multipath reception
US6496971B1 (en) 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6526520B1 (en) 1997-02-08 2003-02-25 Pact Gmbh Method of self-synchronization of configurable elements of a programmable unit
US20030046607A1 (en) * 2001-09-03 2003-03-06 Frank May Method for debugging reconfigurable architectures
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US20030062922A1 (en) * 2001-09-28 2003-04-03 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6553523B1 (en) * 1999-08-13 2003-04-22 Jeffrey V. Lindholm System and method for verifying configuration of a programmable logic device
US20030105949A1 (en) * 2001-11-30 2003-06-05 Quicksilver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US20030135743A1 (en) * 2001-03-22 2003-07-17 Quicksilver Technology Inc. Hardware implementation of the secure hash standard
US20030154357A1 (en) * 2001-03-22 2003-08-14 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US20030200538A1 (en) * 2002-04-23 2003-10-23 Quicksilver Technology, Inc. Method, system and language structure for programming reconfigurable hardware
US6665766B1 (en) * 2000-08-14 2003-12-16 Xilinx, Inc. Adaptable configuration interface for a programmable logic device
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US6697979B1 (en) 1997-12-22 2004-02-24 Pact Xpp Technologies Ag Method of repairing integrated circuits
US6721884B1 (en) * 1999-02-15 2004-04-13 Koninklijke Philips Electronics N.V. System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time
US6732263B1 (en) 2000-06-12 2004-05-04 Altera Corporation Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
US6745369B1 (en) 2000-06-12 2004-06-01 Altera Corporation Bus architecture for system on a chip
US6754882B1 (en) 2002-02-22 2004-06-22 Xilinx, Inc. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
US20040132479A1 (en) * 2001-12-05 2004-07-08 Rubin Owen Robert Consumer product distribution in the embedded system market
US20040143724A1 (en) * 2002-09-30 2004-07-22 Quicksilver Technology, Inc. System and method using embedded microprocessor as a node in an adaptable computing machine
US6772230B2 (en) * 2000-05-26 2004-08-03 Lattice Semiconductor Corp. Field programmable gate array (FPGA) bit stream format
US6772405B1 (en) 2002-06-13 2004-08-03 Xilinx, Inc. Insertable block tile for interconnecting to a device embedded in an integrated circuit
US20040153608A1 (en) * 2001-01-09 2004-08-05 Martin Vorbach Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US6781407B2 (en) 2002-01-09 2004-08-24 Xilinx, Inc. FPGA and embedded circuitry initialization and processing
US20040174187A1 (en) * 2003-03-03 2004-09-09 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
US20040181614A1 (en) * 2001-03-22 2004-09-16 Quicksilver Technology, Inc. Input/output controller node in an adaptable computing environment
US6820248B1 (en) 2002-02-14 2004-11-16 Xilinx, Inc. Method and apparatus for routing interconnects to devices with dissimilar pitches
US6839874B1 (en) 2002-02-28 2005-01-04 Xilinx, Inc. Method and apparatus for testing an embedded device
US6859869B1 (en) * 1995-11-17 2005-02-22 Pact Xpp Technologies Ag Data processing system
US20050040850A1 (en) * 2001-09-28 2005-02-24 Xilinx, Inc. Programmable gate array and embedded circuitry initialization and processing
US20050058186A1 (en) * 2003-09-11 2005-03-17 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
US20050066213A1 (en) * 2001-03-05 2005-03-24 Martin Vorbach Methods and devices for treating and processing data
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US20050125760A1 (en) * 2003-12-04 2005-06-09 International Business Machines Corporation Data processing in digital systems
US6931543B1 (en) 2000-11-28 2005-08-16 Xilinx, Inc. Programmable logic device with decryption algorithm and decryption key
US6934922B1 (en) 2002-02-27 2005-08-23 Xilinx, Inc. Timing performance analysis
US6957340B1 (en) 2000-11-28 2005-10-18 Xilinx, Inc. Encryption key for multi-key encryption in programmable logic device
US6961919B1 (en) 2002-03-04 2005-11-01 Xilinx, Inc. Method of designing integrated circuit having both configurable and fixed logic circuitry
US6965675B1 (en) 2000-11-28 2005-11-15 Xilinx, Inc. Structure and method for loading encryption keys through a test access port
US6973405B1 (en) 2002-05-22 2005-12-06 Xilinx, Inc. Programmable interactive verification agent
US6976160B1 (en) 2002-02-22 2005-12-13 Xilinx, Inc. Method and system for controlling default values of flip-flops in PGA/ASIC-based designs
US6981153B1 (en) 2000-11-28 2005-12-27 Xilinx, Inc. Programmable logic device with method of preventing readback
US6983405B1 (en) 2001-11-16 2006-01-03 Xilinx, Inc., Method and apparatus for testing circuitry embedded within a field programmable gate array
US20060015701A1 (en) * 2002-11-01 2006-01-19 Quicksilver Technology, Inc. Arithmetic node including general digital signal processing functions for an adaptive computing machine
US6996758B1 (en) 2001-11-16 2006-02-07 Xilinx, Inc. Apparatus for testing an interconnecting logic fabric
US7007121B1 (en) 2002-02-27 2006-02-28 Xilinx, Inc. Method and apparatus for synchronized buses
US7024653B1 (en) * 2000-10-30 2006-04-04 Cypress Semiconductor Corporation Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD)
US7058177B1 (en) 2000-11-28 2006-06-06 Xilinx, Inc. Partially encrypted bitstream method
US7058920B2 (en) 2001-05-06 2006-06-06 Altera Corporation Methods for designing PLD architectures for flexible placement of IP function blocks
US7076595B1 (en) 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US7085973B1 (en) 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
US7088767B1 (en) 2002-03-01 2006-08-08 Xilinx, Inc. Method and apparatus for operating a transceiver in different data rates
US7092865B1 (en) 2002-09-10 2006-08-15 Xilinx, Inc. Method and apparatus for timing modeling
US7099426B1 (en) 2002-09-03 2006-08-29 Xilinx, Inc. Flexible channel bonding and clock correction operations on a multi-block data path
US20060192586A1 (en) * 2002-09-06 2006-08-31 Martin Vorbach Reconfigurable sequencer structure
US7111220B1 (en) 2002-03-01 2006-09-19 Xilinx, Inc. Network physical layer with embedded multi-standard CRC generator
US7111217B1 (en) 2002-02-28 2006-09-19 Xilinx, Inc. Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC)
US7117373B1 (en) * 2000-11-28 2006-10-03 Xilinx, Inc. Bitstream for configuring a PLD with encrypted design data
US7117372B1 (en) 2000-11-28 2006-10-03 Xilinx, Inc. Programmable logic device with decryption and structure for preventing design relocation
US7187709B1 (en) 2002-03-01 2007-03-06 Xilinx, Inc. High speed configurable transceiver architecture
US20070123091A1 (en) * 2005-11-18 2007-05-31 Swedberg Benjamin D Releasable Wire Connector
US20070139074A1 (en) * 2005-12-19 2007-06-21 M2000 Configurable circuits with microcontrollers
US7243312B1 (en) 2003-10-24 2007-07-10 Xilinx, Inc. Method and apparatus for power optimization during an integrated circuit design process
US20070245049A1 (en) * 2006-04-12 2007-10-18 Dell Products L.P. System and method for transferring serial data
WO2007120439A2 (en) * 2006-04-14 2007-10-25 Raytheon Company Data storing
US7314174B1 (en) * 2004-10-22 2008-01-01 Xilinx, Inc. Method and system for configuring an integrated circuit
US7389485B1 (en) 2006-03-28 2008-06-17 Xilinx, Inc. Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures
US7433909B2 (en) 2002-06-25 2008-10-07 Nvidia Corporation Processing architecture for a reconfigurable arithmetic node
US7535254B1 (en) * 2007-05-14 2009-05-19 Xilinx, Inc. Reconfiguration of a hard macro via configuration registers
US7557607B1 (en) 2007-05-14 2009-07-07 Xilinx, Inc. Interface device reset
US7573295B1 (en) 2007-05-14 2009-08-11 Xilinx, Inc. Hard macro-to-user logic interface
US7577799B1 (en) 2003-08-19 2009-08-18 Nvidia Corporation Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture
US20090227839A1 (en) * 2005-06-21 2009-09-10 Olympus Medical Systems Corp. Electronic endoscopic apparatus
US7620678B1 (en) 2002-06-12 2009-11-17 Nvidia Corporation Method and system for reducing the time-to-market concerns for embedded system design
US7626418B1 (en) 2007-05-14 2009-12-01 Xilinx, Inc. Configurable interface
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7653710B2 (en) 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US7668229B2 (en) 2001-12-12 2010-02-23 Qst Holdings, Llc Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US20100076911A1 (en) * 2008-09-25 2010-03-25 Microsoft Corporation Automated Feature Selection Based on Rankboost for Ranking
US20100076915A1 (en) * 2008-09-25 2010-03-25 Microsoft Corporation Field-Programmable Gate Array Based Accelerator System
US7702840B1 (en) 2007-05-14 2010-04-20 Xilinx, Inc. Interface device lane configuration
US20100161775A1 (en) * 2002-01-04 2010-06-24 Qst Holdings, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US7802108B1 (en) 2002-07-18 2010-09-21 Nvidia Corporation Secure storage of program code for an embedded system
US7809050B2 (en) 2001-05-08 2010-10-05 Qst Holdings, Llc Method and system for reconfigurable channel coding
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7865847B2 (en) 2002-05-13 2011-01-04 Qst Holdings, Inc. Method and system for creating and programming an adaptive computing engine
US7893712B1 (en) 2009-09-10 2011-02-22 Xilinx, Inc. Integrated circuit with a selectable interconnect circuit for low power or high performance operation
US7904603B2 (en) 2002-10-28 2011-03-08 Qst Holdings, Llc Adaptable datapath for a digital processing system
US7937539B2 (en) 2002-11-22 2011-05-03 Qst Holdings, Llc External memory controller node
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US20110161389A1 (en) * 2006-12-05 2011-06-30 Altera Corporation Large multiplier for programmable logic device
US7987065B1 (en) 2007-04-17 2011-07-26 Nvidia Corporation Automatic quality testing of multimedia rendering by software drivers
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
USRE42743E1 (en) 2001-11-28 2011-09-27 Qst Holdings, Llc System for authorizing functionality in adaptable hardware devices
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
WO2011147442A1 (en) * 2010-05-25 2011-12-01 Panasonic Corporation Indirect register access for a programmable logic device
WO2011147443A1 (en) * 2010-05-25 2011-12-01 Panasonic Corporation Extended bitmaps for a programmable logic device
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
US8117137B2 (en) 2007-04-19 2012-02-14 Microsoft Corporation Field-programmable gate array based accelerator system
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US8225073B2 (en) 2001-11-30 2012-07-17 Qst Holdings Llc Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US8276135B2 (en) 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US8296764B2 (en) 2003-08-14 2012-10-23 Nvidia Corporation Internal synchronization control for adaptive integrated circuitry
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8533431B2 (en) 2001-03-22 2013-09-10 Altera Corporation Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US20130305199A1 (en) * 2010-09-29 2013-11-14 The Regents Of The University Of California In-place resynthesis and remapping techniques for soft error mitigation in fpga
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US8909941B1 (en) 2011-03-31 2014-12-09 Xilinx, Inc. Programmable integrated circuit and a method of enabling the detection of tampering with data provided to a programmable integrated circuit
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US8966253B1 (en) * 2010-06-01 2015-02-24 Xilinx, Inc. Method and apparatus for authenticating a programmable device bitstream
US8987868B1 (en) 2009-02-24 2015-03-24 Xilinx, Inc. Method and apparatus for programmable heterogeneous integration of stacked semiconductor die
US9000490B2 (en) 2013-04-19 2015-04-07 Xilinx, Inc. Semiconductor package having IC dice and voltage tuners
US9015023B2 (en) 2010-05-05 2015-04-21 Xilinx, Inc. Device specific configuration of operating voltage
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9563565B2 (en) 2013-08-14 2017-02-07 Micron Technology, Inc. Apparatuses and methods for providing data from a buffer
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
US9734097B2 (en) 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
US20170249412A1 (en) * 2007-09-14 2017-08-31 Agate Logic Inc. Memory Controller For Heterogeneous Configurable Integrated Circuit
US9754648B2 (en) 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849760A (en) * 1971-07-12 1974-11-19 Hitachi Ltd Multi-dimensional pattern recognition processor
US5394031A (en) * 1993-12-08 1995-02-28 At&T Corp. Apparatus and method to improve programming speed of field programmable gate arrays
US5457408A (en) * 1994-11-23 1995-10-10 At&T Corp. Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849760A (en) * 1971-07-12 1974-11-19 Hitachi Ltd Multi-dimensional pattern recognition processor
US5394031A (en) * 1993-12-08 1995-02-28 At&T Corp. Apparatus and method to improve programming speed of field programmable gate arrays
US5457408A (en) * 1994-11-23 1995-10-10 At&T Corp. Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA

Non-Patent Citations (10)

* Cited by examiner, † Cited by third party
Title
"New IEEE Standard Dictionary of Electrical and Electronics Terms", Fifth Edition, 1993, p. 1011.
"The Programmable Logic Data Book" copyright 1994, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 2-105 to 2-132.
D.D. Gajski, et al, "Computer Architecture" IEEE Tutorial Manual, IEEE Computer Society, 1987, pp. v-i.
D.D. Gajski, et al, Computer Architecture IEEE Tutorial Manual, IEEE Computer Society, 1987, pp. v i. *
David A. Patterson and John L. Hennessy, "Computer Architecture: A Quantitive Approach", pp. 200-201, 1990.
David A. Patterson and John L. Hennessy, Computer Architecture: A Quantitive Approach , pp. 200 201, 1990. *
Hodges, et al, "Analog MOS Integrated Circuits" IEEE Press, 1980, pp, 2-11.
Hodges, et al, Analog MOS Integrated Circuits IEEE Press, 1980, pp, 2 11. *
New IEEE Standard Dictionary of Electrical and Electronics Terms , Fifth Edition, 1993, p. 1011. *
The Programmable Logic Data Book copyright 1994, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 2 105 to 2 132. *

Cited By (263)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026481A (en) * 1995-04-28 2000-02-15 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
US6859869B1 (en) * 1995-11-17 2005-02-22 Pact Xpp Technologies Ag Data processing system
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US8156312B2 (en) 1996-12-09 2012-04-10 Martin Vorbach Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
US6425068B1 (en) 1996-12-09 2002-07-23 Pact Gmbh Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)
US6728871B1 (en) 1996-12-09 2004-04-27 Pact Xpp Technologies Ag Runtime configurable arithmetic and logic cell
US6513077B2 (en) 1996-12-20 2003-01-28 Pact Gmbh I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US6721830B2 (en) 1996-12-20 2004-04-13 Pact Xpp Technologies Ag I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US7337249B2 (en) 1996-12-20 2008-02-26 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7243175B2 (en) 1996-12-20 2007-07-10 Pact Xpp Technologies Ag I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US8195856B2 (en) 1996-12-20 2012-06-05 Martin Vorbach I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US20040199688A1 (en) * 1996-12-20 2004-10-07 Martin Vorbach I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures
US7899962B2 (en) 1996-12-20 2011-03-01 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US6477643B1 (en) 1996-12-27 2002-11-05 Pact Gmbh Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US6526520B1 (en) 1997-02-08 2003-02-25 Pact Gmbh Method of self-synchronization of configurable elements of a programmable unit
USRE44383E1 (en) 1997-02-08 2013-07-16 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US20040083399A1 (en) * 1997-02-08 2004-04-29 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE45109E1 (en) 1997-02-08 2014-09-02 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE45223E1 (en) 1997-02-08 2014-10-28 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
US20040052130A1 (en) * 1997-02-08 2004-03-18 Martin Vorbach Method of self-synchronization of configurable elements of a programmable unit
US20030135686A1 (en) * 1997-02-11 2003-07-17 Martin Vorbach Internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US6405299B1 (en) * 1997-02-11 2002-06-11 Pact Gmbh Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US7010667B2 (en) * 1997-02-11 2006-03-07 Pact Xpp Technologies Ag Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US20040181726A1 (en) * 1997-12-22 2004-09-16 Martin Vorbach Method and system for alternating between programs for execution by cells of an integrated circuit
US6697979B1 (en) 1997-12-22 2004-02-24 Pact Xpp Technologies Ag Method of repairing integrated circuits
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US6097988A (en) * 1998-02-10 2000-08-01 Advanced Micro Devices, Inc. Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic
US6687788B2 (en) 1998-02-25 2004-02-03 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
US6571381B1 (en) 1998-02-25 2003-05-27 Pact Xpp Technologies Ag Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US6480937B1 (en) 1998-02-25 2002-11-12 Pact Informationstechnologie Gmbh Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--
US6445205B1 (en) * 1998-11-26 2002-09-03 Telefonaktiebolaget Lm Ericsson Method of testing integrated circuits
US6721884B1 (en) * 1999-02-15 2004-04-13 Koninklijke Philips Electronics N.V. System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time
US8468329B2 (en) 1999-02-25 2013-06-18 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8726250B2 (en) 1999-06-10 2014-05-13 Pact Xpp Technologies Ag Configurable logic integrated circuit having a multidimensional structure of configurable elements
US8312200B2 (en) 1999-06-10 2012-11-13 Martin Vorbach Processor chip including a plurality of cache elements connected to a plurality of processor cores
US6553523B1 (en) * 1999-08-13 2003-04-22 Jeffrey V. Lindholm System and method for verifying configuration of a programmable logic device
US6496971B1 (en) 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6772230B2 (en) * 2000-05-26 2004-08-03 Lattice Semiconductor Corp. Field programmable gate array (FPGA) bit stream format
US7343483B1 (en) 2000-06-12 2008-03-11 Altera Corporation Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
US6732263B1 (en) 2000-06-12 2004-05-04 Altera Corporation Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
US6745369B1 (en) 2000-06-12 2004-06-01 Altera Corporation Bus architecture for system on a chip
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US6665766B1 (en) * 2000-08-14 2003-12-16 Xilinx, Inc. Adaptable configuration interface for a programmable logic device
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US8471593B2 (en) 2000-10-06 2013-06-25 Martin Vorbach Logic cell array and bus system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US9047440B2 (en) 2000-10-06 2015-06-02 Pact Xpp Technologies Ag Logical cell array and bus system
US7024653B1 (en) * 2000-10-30 2006-04-04 Cypress Semiconductor Corporation Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD)
US7058177B1 (en) 2000-11-28 2006-06-06 Xilinx, Inc. Partially encrypted bitstream method
US7117372B1 (en) 2000-11-28 2006-10-03 Xilinx, Inc. Programmable logic device with decryption and structure for preventing design relocation
US6981153B1 (en) 2000-11-28 2005-12-27 Xilinx, Inc. Programmable logic device with method of preventing readback
US7117373B1 (en) * 2000-11-28 2006-10-03 Xilinx, Inc. Bitstream for configuring a PLD with encrypted design data
US6965675B1 (en) 2000-11-28 2005-11-15 Xilinx, Inc. Structure and method for loading encryption keys through a test access port
US6957340B1 (en) 2000-11-28 2005-10-18 Xilinx, Inc. Encryption key for multi-key encryption in programmable logic device
US6931543B1 (en) 2000-11-28 2005-08-16 Xilinx, Inc. Programmable logic device with decryption algorithm and decryption key
US20040153608A1 (en) * 2001-01-09 2004-08-05 Martin Vorbach Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US20050257009A9 (en) * 2001-01-09 2005-11-17 Martin Vorbach Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (fpgas, dpgas, etc.)
US20050066213A1 (en) * 2001-03-05 2005-03-24 Martin Vorbach Methods and devices for treating and processing data
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US8312301B2 (en) 2001-03-05 2012-11-13 Martin Vorbach Methods and devices for treating and processing data
US8145881B2 (en) 2001-03-05 2012-03-27 Martin Vorbach Data processing device and method
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7325123B2 (en) 2001-03-22 2008-01-29 Qst Holdings, Llc Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements
US8533431B2 (en) 2001-03-22 2013-09-10 Altera Corporation Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US8543795B2 (en) 2001-03-22 2013-09-24 Altera Corporation Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US8543794B2 (en) 2001-03-22 2013-09-24 Altera Corporation Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US9665397B2 (en) 2001-03-22 2017-05-30 Cornami, Inc. Hardware task manager
US20030135743A1 (en) * 2001-03-22 2003-07-17 Quicksilver Technology Inc. Hardware implementation of the secure hash standard
US9164952B2 (en) 2001-03-22 2015-10-20 Altera Corporation Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US9037834B2 (en) 2001-03-22 2015-05-19 Altera Corporation Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US20030154357A1 (en) * 2001-03-22 2003-08-14 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7624204B2 (en) 2001-03-22 2009-11-24 Nvidia Corporation Input/output controller node in an adaptable computing environment
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7489779B2 (en) * 2001-03-22 2009-02-10 Qstholdings, Llc Hardware implementation of the secure hash standard
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US8356161B2 (en) 2001-03-22 2013-01-15 Qst Holdings Llc Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements
US20040181614A1 (en) * 2001-03-22 2004-09-16 Quicksilver Technology, Inc. Input/output controller node in an adaptable computing environment
US9015352B2 (en) 2001-03-22 2015-04-21 Altera Corporation Adaptable datapath for a digital processing system
US9396161B2 (en) 2001-03-22 2016-07-19 Altera Corporation Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US8589660B2 (en) 2001-03-22 2013-11-19 Altera Corporation Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US20020138716A1 (en) * 2001-03-22 2002-09-26 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7584447B2 (en) 2001-05-06 2009-09-01 Altera Corporation PLD architecture for flexible placement of IP function blocks
US9094014B2 (en) 2001-05-06 2015-07-28 Altera Corporation PLD architecture for flexible placement of IP function blocks
US8201129B2 (en) 2001-05-06 2012-06-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
US8732646B2 (en) 2001-05-06 2014-05-20 Altera Corporation PLD architecture for flexible placement of IP function blocks
US7058920B2 (en) 2001-05-06 2006-06-06 Altera Corporation Methods for designing PLD architectures for flexible placement of IP function blocks
US8407649B2 (en) 2001-05-06 2013-03-26 Altera Corporation PLD architecture for flexible placement of IP function blocks
US20090224800A1 (en) * 2001-05-06 2009-09-10 Altera Corporation Pld architecture for flexible placement of ip function blocks
US7809050B2 (en) 2001-05-08 2010-10-05 Qst Holdings, Llc Method and system for reconfigurable channel coding
US7822109B2 (en) 2001-05-08 2010-10-26 Qst Holdings, Llc. Method and system for reconfigurable channel coding
US8249135B2 (en) 2001-05-08 2012-08-21 Qst Holdings Llc Method and system for reconfigurable channel coding
US8767804B2 (en) 2001-05-08 2014-07-01 Qst Holdings Llc Method and system for reconfigurable channel coding
US20060236018A1 (en) * 2001-05-18 2006-10-19 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US7076595B1 (en) 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US7266632B2 (en) 2001-05-18 2007-09-04 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US20070255886A1 (en) * 2001-05-18 2007-11-01 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US7406557B2 (en) 2001-05-18 2008-07-29 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US20020184291A1 (en) * 2001-05-31 2002-12-05 Hogenauer Eugene B. Method and system for scheduling in an adaptable computing engine
US6618434B2 (en) * 2001-05-31 2003-09-09 Quicksilver Technology, Inc. Adaptive, multimode rake receiver for dynamic search and multipath reception
US20020181559A1 (en) * 2001-05-31 2002-12-05 Quicksilver Technology, Inc. Adaptive, multimode rake receiver for dynamic search and multipath reception
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US20030046607A1 (en) * 2001-09-03 2003-03-06 Frank May Method for debugging reconfigurable architectures
US8407525B2 (en) 2001-09-03 2013-03-26 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US8429385B2 (en) 2001-09-03 2013-04-23 Martin Vorbach Device including a field having function cells and information providing cells controlled by the function cells
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
US8069373B2 (en) 2001-09-03 2011-11-29 Martin Vorbach Method for debugging reconfigurable architectures
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US20050022062A1 (en) * 2001-09-03 2005-01-27 Martin Vorbach Method for debugging reconfigurable architectures
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7420392B2 (en) 2001-09-28 2008-09-02 Xilinx, Inc. Programmable gate array and embedded circuitry initialization and processing
US20050040850A1 (en) * 2001-09-28 2005-02-24 Xilinx, Inc. Programmable gate array and embedded circuitry initialization and processing
US6798239B2 (en) 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US20030062922A1 (en) * 2001-09-28 2003-04-03 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6996758B1 (en) 2001-11-16 2006-02-07 Xilinx, Inc. Apparatus for testing an interconnecting logic fabric
US7080300B1 (en) 2001-11-16 2006-07-18 Xilinx, Inc. Testing a programmable logic device with embedded fixed logic using a scan chain
US6983405B1 (en) 2001-11-16 2006-01-03 Xilinx, Inc., Method and apparatus for testing circuitry embedded within a field programmable gate array
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US7539848B1 (en) 2001-11-19 2009-05-26 Xilinx, Inc. Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor
US7194600B2 (en) 2001-11-19 2007-03-20 Xilinx, Inc. Method and apparatus for processing data with a programmable gate array using fixed and programmable processors
USRE42743E1 (en) 2001-11-28 2011-09-27 Qst Holdings, Llc System for authorizing functionality in adaptable hardware devices
US6986021B2 (en) 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US20030105949A1 (en) * 2001-11-30 2003-06-05 Quicksilver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US9594723B2 (en) 2001-11-30 2017-03-14 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements
US8225073B2 (en) 2001-11-30 2012-07-17 Qst Holdings Llc Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US8880849B2 (en) 2001-11-30 2014-11-04 Altera Corporation Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US9330058B2 (en) 2001-11-30 2016-05-03 Altera Corporation Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US8250339B2 (en) 2001-11-30 2012-08-21 Qst Holdings Llc Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US7644279B2 (en) 2001-12-05 2010-01-05 Nvidia Corporation Consumer product distribution in the embedded system market
US20040132479A1 (en) * 2001-12-05 2004-07-08 Rubin Owen Robert Consumer product distribution in the embedded system market
US8442096B2 (en) 2001-12-12 2013-05-14 Qst Holdings Llc Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US7668229B2 (en) 2001-12-12 2010-02-23 Qst Holdings, Llc Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US20100161775A1 (en) * 2002-01-04 2010-06-24 Qst Holdings, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
US9002998B2 (en) 2002-01-04 2015-04-07 Altera Corporation Apparatus and method for adaptive multimedia reception and transmission in communication environments
US6781407B2 (en) 2002-01-09 2004-08-24 Xilinx, Inc. FPGA and embedded circuitry initialization and processing
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US6820248B1 (en) 2002-02-14 2004-11-16 Xilinx, Inc. Method and apparatus for routing interconnects to devices with dissimilar pitches
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US6996796B2 (en) 2002-02-22 2006-02-07 Xilinx, Inc. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
US6976160B1 (en) 2002-02-22 2005-12-13 Xilinx, Inc. Method and system for controlling default values of flip-flops in PGA/ASIC-based designs
US20040225992A1 (en) * 2002-02-22 2004-11-11 Xilinx, Inc. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
US7552415B2 (en) 2002-02-22 2009-06-23 Xilinx, Inc. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
US6754882B1 (en) 2002-02-22 2004-06-22 Xilinx, Inc. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
US7254794B1 (en) 2002-02-27 2007-08-07 Xilinx, Inc. Timing performance analysis
US6934922B1 (en) 2002-02-27 2005-08-23 Xilinx, Inc. Timing performance analysis
US7007121B1 (en) 2002-02-27 2006-02-28 Xilinx, Inc. Method and apparatus for synchronized buses
US6839874B1 (en) 2002-02-28 2005-01-04 Xilinx, Inc. Method and apparatus for testing an embedded device
US7111217B1 (en) 2002-02-28 2006-09-19 Xilinx, Inc. Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC)
US7187709B1 (en) 2002-03-01 2007-03-06 Xilinx, Inc. High speed configurable transceiver architecture
US7111220B1 (en) 2002-03-01 2006-09-19 Xilinx, Inc. Network physical layer with embedded multi-standard CRC generator
US7088767B1 (en) 2002-03-01 2006-08-08 Xilinx, Inc. Method and apparatus for operating a transceiver in different data rates
US6961919B1 (en) 2002-03-04 2005-11-01 Xilinx, Inc. Method of designing integrated circuit having both configurable and fixed logic circuitry
US6732354B2 (en) 2002-04-23 2004-05-04 Quicksilver Technology, Inc. Method, system and software for programming reconfigurable hardware
US20030200538A1 (en) * 2002-04-23 2003-10-23 Quicksilver Technology, Inc. Method, system and language structure for programming reconfigurable hardware
US7865847B2 (en) 2002-05-13 2011-01-04 Qst Holdings, Inc. Method and system for creating and programming an adaptive computing engine
US6973405B1 (en) 2002-05-22 2005-12-06 Xilinx, Inc. Programmable interactive verification agent
US7620678B1 (en) 2002-06-12 2009-11-17 Nvidia Corporation Method and system for reducing the time-to-market concerns for embedded system design
US6772405B1 (en) 2002-06-13 2004-08-03 Xilinx, Inc. Insertable block tile for interconnecting to a device embedded in an integrated circuit
US8200799B2 (en) 2002-06-25 2012-06-12 Qst Holdings Llc Hardware task manager
US8782196B2 (en) 2002-06-25 2014-07-15 Sviral, Inc. Hardware task manager
US7653710B2 (en) 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US7433909B2 (en) 2002-06-25 2008-10-07 Nvidia Corporation Processing architecture for a reconfigurable arithmetic node
US7526689B1 (en) 2002-07-09 2009-04-28 Xilinx, Inc. Testing address lines of a memory controller
US7085973B1 (en) 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
US7802108B1 (en) 2002-07-18 2010-09-21 Nvidia Corporation Secure storage of program code for an embedded system
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US8281265B2 (en) 2002-08-07 2012-10-02 Martin Vorbach Method and device for processing data
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
US7099426B1 (en) 2002-09-03 2006-08-29 Xilinx, Inc. Flexible channel bonding and clock correction operations on a multi-block data path
US7928763B2 (en) 2002-09-06 2011-04-19 Martin Vorbach Multi-core processing system
US8310274B2 (en) 2002-09-06 2012-11-13 Martin Vorbach Reconfigurable sequencer structure
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US8803552B2 (en) 2002-09-06 2014-08-12 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US20060192586A1 (en) * 2002-09-06 2006-08-31 Martin Vorbach Reconfigurable sequencer structure
US7092865B1 (en) 2002-09-10 2006-08-15 Xilinx, Inc. Method and apparatus for timing modeling
US7379855B1 (en) 2002-09-10 2008-05-27 Xilinx, Inc. Method and apparatus for timing modeling
US7502915B2 (en) 2002-09-30 2009-03-10 Nvidia Corporation System and method using embedded microprocessor as a node in an adaptable computing machine
US20040143724A1 (en) * 2002-09-30 2004-07-22 Quicksilver Technology, Inc. System and method using embedded microprocessor as a node in an adaptable computing machine
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US7904603B2 (en) 2002-10-28 2011-03-08 Qst Holdings, Llc Adaptable datapath for a digital processing system
US8706916B2 (en) 2002-10-28 2014-04-22 Altera Corporation Adaptable datapath for a digital processing system
US8380884B2 (en) 2002-10-28 2013-02-19 Altera Corporation Adaptable datapath for a digital processing system
US20060015701A1 (en) * 2002-11-01 2006-01-19 Quicksilver Technology, Inc. Arithmetic node including general digital signal processing functions for an adaptive computing machine
US8949576B2 (en) * 2002-11-01 2015-02-03 Nvidia Corporation Arithmetic node including general digital signal processing functions for an adaptive computing machine
US8276135B2 (en) 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
US7937539B2 (en) 2002-11-22 2011-05-03 Qst Holdings, Llc External memory controller node
US7941614B2 (en) 2002-11-22 2011-05-10 QST, Holdings, Inc External memory controller node
US7984247B2 (en) 2002-11-22 2011-07-19 Qst Holdings Llc External memory controller node
US7937538B2 (en) 2002-11-22 2011-05-03 Qst Holdings, Llc External memory controller node
US8266388B2 (en) 2002-11-22 2012-09-11 Qst Holdings Llc External memory controller
US7979646B2 (en) 2002-11-22 2011-07-12 Qst Holdings, Inc. External memory controller node
US8769214B2 (en) 2002-11-22 2014-07-01 Qst Holdings Llc External memory controller node
US20050039155A1 (en) * 2003-03-03 2005-02-17 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
US7138828B2 (en) 2003-03-03 2006-11-21 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
US20050040851A1 (en) * 2003-03-03 2005-02-24 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
US6960934B2 (en) 2003-03-03 2005-11-01 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
US20040174187A1 (en) * 2003-03-03 2004-09-09 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
US6930510B2 (en) * 2003-03-03 2005-08-16 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US8296764B2 (en) 2003-08-14 2012-10-23 Nvidia Corporation Internal synchronization control for adaptive integrated circuitry
US7577799B1 (en) 2003-08-19 2009-08-18 Nvidia Corporation Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US20050058186A1 (en) * 2003-09-11 2005-03-17 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
US7421014B2 (en) 2003-09-11 2008-09-02 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
US7243312B1 (en) 2003-10-24 2007-07-10 Xilinx, Inc. Method and apparatus for power optimization during an integrated circuit design process
US20060070016A1 (en) * 2003-12-04 2006-03-30 International Business Machines Corporation Data processing in digital systems
US20080134126A1 (en) * 2003-12-04 2008-06-05 Goodnow Kenneth J Data processing in digital systems
US20050125760A1 (en) * 2003-12-04 2005-06-09 International Business Machines Corporation Data processing in digital systems
US6996795B2 (en) 2003-12-04 2006-02-07 International Business Machines Corporation Data processing in digital systems
US7353486B2 (en) 2003-12-04 2008-04-01 International Business Machines Corporation Data processing in digital systems
US7314174B1 (en) * 2004-10-22 2008-01-01 Xilinx, Inc. Method and system for configuring an integrated circuit
US20090227839A1 (en) * 2005-06-21 2009-09-10 Olympus Medical Systems Corp. Electronic endoscopic apparatus
US8764636B2 (en) * 2005-06-21 2014-07-01 Olympus Medical Systems Corp. Electronic endoscopic apparatus
US20070123091A1 (en) * 2005-11-18 2007-05-31 Swedberg Benjamin D Releasable Wire Connector
US20070139074A1 (en) * 2005-12-19 2007-06-21 M2000 Configurable circuits with microcontrollers
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US7389485B1 (en) 2006-03-28 2008-06-17 Xilinx, Inc. Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures
US20070245049A1 (en) * 2006-04-12 2007-10-18 Dell Products L.P. System and method for transferring serial data
US7840726B2 (en) 2006-04-12 2010-11-23 Dell Products L.P. System and method for identifying and transferring serial data to a programmable logic device
WO2007120439A3 (en) * 2006-04-14 2008-03-20 Peter F Acsadi Data storing
WO2007120439A2 (en) * 2006-04-14 2007-10-25 Raytheon Company Data storing
US20110161389A1 (en) * 2006-12-05 2011-06-30 Altera Corporation Large multiplier for programmable logic device
US7987065B1 (en) 2007-04-17 2011-07-26 Nvidia Corporation Automatic quality testing of multimedia rendering by software drivers
US8117137B2 (en) 2007-04-19 2012-02-14 Microsoft Corporation Field-programmable gate array based accelerator system
US8583569B2 (en) 2007-04-19 2013-11-12 Microsoft Corporation Field-programmable gate array based accelerator system
US7573295B1 (en) 2007-05-14 2009-08-11 Xilinx, Inc. Hard macro-to-user logic interface
US7702840B1 (en) 2007-05-14 2010-04-20 Xilinx, Inc. Interface device lane configuration
US7557607B1 (en) 2007-05-14 2009-07-07 Xilinx, Inc. Interface device reset
US7626418B1 (en) 2007-05-14 2009-12-01 Xilinx, Inc. Configurable interface
US7535254B1 (en) * 2007-05-14 2009-05-19 Xilinx, Inc. Reconfiguration of a hard macro via configuration registers
US20170249412A1 (en) * 2007-09-14 2017-08-31 Agate Logic Inc. Memory Controller For Heterogeneous Configurable Integrated Circuit
US8131659B2 (en) 2008-09-25 2012-03-06 Microsoft Corporation Field-programmable gate array based accelerator system
US20100076915A1 (en) * 2008-09-25 2010-03-25 Microsoft Corporation Field-Programmable Gate Array Based Accelerator System
US8301638B2 (en) 2008-09-25 2012-10-30 Microsoft Corporation Automated feature selection based on rankboost for ranking
US20100076911A1 (en) * 2008-09-25 2010-03-25 Microsoft Corporation Automated Feature Selection Based on Rankboost for Ranking
US8987868B1 (en) 2009-02-24 2015-03-24 Xilinx, Inc. Method and apparatus for programmable heterogeneous integration of stacked semiconductor die
US7893712B1 (en) 2009-09-10 2011-02-22 Xilinx, Inc. Integrated circuit with a selectable interconnect circuit for low power or high performance operation
US9015023B2 (en) 2010-05-05 2015-04-21 Xilinx, Inc. Device specific configuration of operating voltage
WO2011147443A1 (en) * 2010-05-25 2011-12-01 Panasonic Corporation Extended bitmaps for a programmable logic device
WO2011147442A1 (en) * 2010-05-25 2011-12-01 Panasonic Corporation Indirect register access for a programmable logic device
US8966253B1 (en) * 2010-06-01 2015-02-24 Xilinx, Inc. Method and apparatus for authenticating a programmable device bitstream
US20130305199A1 (en) * 2010-09-29 2013-11-14 The Regents Of The University Of California In-place resynthesis and remapping techniques for soft error mitigation in fpga
US9047429B2 (en) * 2010-09-29 2015-06-02 The Regents Of The University Of California In-place resynthesis and remapping techniques for soft error mitigation in FPGA
US8909941B1 (en) 2011-03-31 2014-12-09 Xilinx, Inc. Programmable integrated circuit and a method of enabling the detection of tampering with data provided to a programmable integrated circuit
US9754648B2 (en) 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9734097B2 (en) 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
US9000490B2 (en) 2013-04-19 2015-04-07 Xilinx, Inc. Semiconductor package having IC dice and voltage tuners
US9710192B2 (en) 2013-08-14 2017-07-18 Micron Technology, Inc. Apparatuses and methods for providing data from a buffer
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
US9563565B2 (en) 2013-08-14 2017-02-07 Micron Technology, Inc. Apparatuses and methods for providing data from a buffer
US9928171B2 (en) 2013-08-14 2018-03-27 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area

Similar Documents

Publication Publication Date Title
Blodget et al. A lightweight approach for embedded reconfiguration of FPGAs
US5352940A (en) Ram convertible look-up table based macrocell for PLDs
US6487709B1 (en) Run-time routing for programmable logic devices
US5598109A (en) Programmable logic array device with grouped logic regions and three types of conductors
US6396302B2 (en) Configurable logic element with expander structures
US6467017B1 (en) Programmable logic device having embedded dual-port random access memory configurable as single-port memory
US6429682B1 (en) Configuration bus interface circuit for FPGAs
US6526461B1 (en) Interconnect chip for programmable logic devices
US6247110B1 (en) Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US5970254A (en) Integrated processor and programmable data path chip for reconfigurable computing
US6191611B1 (en) Driver circuitry for programmable logic devices with hierarchical interconnection resources
US7126856B2 (en) Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array
US5986465A (en) Programmable logic integrated circuit architecture incorporating a global shareable expander
US6400180B2 (en) Configurable lookup table for programmable logic devices
US6020759A (en) Programmable logic array device with random access memory configurable as product terms
US5835998A (en) Logic cell for programmable logic devices
US5677864A (en) Intelligent memory architecture
US6483342B2 (en) Multi-master multi-slave system bus in a field programmable gate array (FPGA)
US6888375B2 (en) Tileable field-programmable gate array architecture
US6122720A (en) Coarse-grained look-up table architecture
US4791602A (en) Soft programmable logic array
US6289494B1 (en) Optimized emulation and prototyping architecture
US6359468B1 (en) Programmable logic device with carry look-ahead
US5815003A (en) Programmable logic integrated circuits with partitioned logic element using shared lab-wide signals
US6108760A (en) Method and apparatus for position independent reconfiguration in a network of multiple context processing elements

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12