US5802350A - System and method for selecting an interrupt system based upon the operating system of a multiprocessor system - Google Patents

System and method for selecting an interrupt system based upon the operating system of a multiprocessor system Download PDF

Info

Publication number
US5802350A
US5802350A US08/591,245 US59124596A US5802350A US 5802350 A US5802350 A US 5802350A US 59124596 A US59124596 A US 59124596A US 5802350 A US5802350 A US 5802350A
Authority
US
United States
Prior art keywords
interrupt
detecting
utilized
operating system
operating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/591,245
Inventor
Keenan Wynn Franz
John David Purcell
Kevin F. Reick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US08/591,245 priority Critical patent/US5802350A/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: REICK, KEVIN F., PURCELL, JOHN DAVID, FRANZ, KEENAN WYNN
Priority to KR1019960047595A priority patent/KR100259456B1/en
Priority to JP31398596A priority patent/JP3525984B2/en
Application granted granted Critical
Publication of US5802350A publication Critical patent/US5802350A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Definitions

  • the present invention relates generally to a multiprocessor system and more particularly to a system for selecting an interrupt system in a multiprocessor system.
  • the PowerPCTM Architecture Specification defines a distributed interrupt method designed for high-performance multiprocessor computers.
  • CHRP Converged Hardware Reference Platform
  • PC Personal Computer
  • OS Operating Systems
  • the PowerPCTM Architecture interrupt method is expected to yield higher performance in a multi-processor computer than the PC interrupt method; however, hardware compatibility with PC OS's demands implementation of the PC interrupt method.
  • a system and method for allowing different operating systems to be utilized in a multiprocessing system is provided in which each of the different operating systems requires different types of interrupt controllers.
  • the system and method comprises detecting which of the different operating systems is utilized within the multiprocessing system, and then selecting the appropriate interrupt controller from the different types of interrupt controllers.
  • the circuitry for both interrupt controllers is preferably implemented on a single computer design with a registered bit that may be toggled to invoke either interrupt method.
  • This register bit is logically located in the reserved system address space and thus protected from errant or malicious application software. Since PC-origin OS's such as Microsoft's Windows NTTM or IBM's OS/2TM are unaware of other interrupt methods and expect a hardware implementation of the PC interrupt method, any system implementing the bimodal interrupt structure described herein will default to the PC interrupt method.
  • the default method is set by the Initial Program Load (IPL) code which is customized to the specific host system and is contained in Read Only Memory (ROM) hardware.
  • IPL code can examine the boot record from the operating system about to be loaded and if the IPL code recognizes the operating system type, it can then select the proper interrupt controller via the register bit.
  • Other OS's can be made "aware" of the bimodal nature of the interrupt hardware and can switch into the high-performance PowerPCTM interrupt mode.
  • FIG. 1 is a block diagram of a system for selecting an interrupt system in a multiprocessor in accordance with the present invention.
  • the present invention is directed toward an improvement in a multiprocessor system.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
  • Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments.
  • the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
  • a system and method is provided that allows for the detection of operating systems that are being utilized in the multiprocessing environment, and then the selection of the appropriate interrupt controller.
  • circuitry is utilized to implement the present invention.
  • the present invention could be implemented on a computer readable medium and that use would be within the spirit and scope of the present invention.
  • the circuitry for both interrupt controllers is implemented on a single computer design with a registered bit that may be toggled to invoke either interrupt controller.
  • This register bit is logically located in the reserved system address space and thus protected from errant or malicious application software.
  • FIG. 1 is a block diagram of a multiprocessor system (MP) 10 including an interrupt selection system.
  • the MP system includes a plurality of central processing units CPUs 12.
  • the CPU 12 shares memory and I/O space 15 of the addressable memory space 14.
  • the MP system includes a selector, in this case multiplexer 16 which is controlled by a bit in a system control register 18 in the addressable space 14.
  • the multiplexer 16 receives interrupt signals from interrupt controllers 20 and 22 where each of the interrupt controllers 20 and 22 are utilized for different types of operating systems. Through the use of a bit within the register 18 to select the appropriate interrupt system 20 and 22 a multiprocessing system is provided that has improved performance.
  • the register 18 is in a reserved system space 19 that is at a higher privilege level than application software.
  • the circuitry for selecting both interrupt controllers is implemented on a single computer design with a registered bit that may be toggled to invoke either interrupt method.
  • This register bit is logically located in the reserved system address space and thus protected from errant or malicious application software.
  • any system implementing the bimodal interrupt structure described herein will default to the PC interrupt method.
  • the default method is set by the Initial Program Load (IPL) code which is customized to the specific host system and is contained in Read Only Memory (ROM) hardware.
  • IPL Initial Program Load
  • ROM Read Only Memory
  • the IPL code can examine the boot record from the operating system about to be loaded and if the IPL code recognizes the operating system type, it can then select the proper interrupt controller via the register bit.
  • Other OS's can be made "aware" of the bimodal nature of the interrupt hardware and can switch into the high-performance PowerPCTM architecture interrupt mode.
  • the present invention has been described herein with reference to a particular embodiment for a particular application.
  • the selection system has been described in the context of operating systems compatible with the PowerPCTM architecture and Intel X86 compatible architectures, the selection system could be utilized with a variety of operating systems and their use would be within the spirit and scope of the present invention.
  • the present invention has been discussed in the context of two different types of interrupt controllers, one of ordinary skill in the art will readily recognize that any number of controllers could be utilized. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications applications and embodiments within the scope thereof.

Abstract

A system and method for allowing different operating systems to be utilized in a multiprocessing system is provided in which each of the different operating systems requires different types of interrupt controllers. The system and method comprises detecting which of the at least two different types of operating systems is utilized within the multiprocessing system, and then selecting the appropriate interrupt controller from the different types of interrupt controllers.

Description

FIELD OF THE INVENTION
The present invention relates generally to a multiprocessor system and more particularly to a system for selecting an interrupt system in a multiprocessor system.
BACKGROUND OF THE INVENTION
As different computer architectures are utilized, it has become important to provide functionality across those architectures. This is increasingly significant when these different computer architectures can be utilized in the same multiprocessing environment.
For example, the PowerPC™ Architecture Specification defines a distributed interrupt method designed for high-performance multiprocessor computers. However, the Converged Hardware Reference Platform (CHRP) agreed to by IBM and Apple Computer defines an interrupt method that carries a legacy from the Personal Computer (PC) architecture, which is Intel X86 compatible which is incompatible with the PowerPC™ Architecture interrupt method. Operating Systems (OS) that have ancestry in the PC expect the host system to implement the PC interrupt method, whereas other OS's may expect the host system to implement the PowerPC™ Architecture interrupt method. The PowerPC™ Architecture interrupt method is expected to yield higher performance in a multi-processor computer than the PC interrupt method; however, hardware compatibility with PC OS's demands implementation of the PC interrupt method.
Therefore in order for a computer to be compatible with OS's of either heritage an interrupt system is needed that allows a computer to personalize itself depending on what OS is loaded. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A system and method for allowing different operating systems to be utilized in a multiprocessing system is provided in which each of the different operating systems requires different types of interrupt controllers. The system and method comprises detecting which of the different operating systems is utilized within the multiprocessing system, and then selecting the appropriate interrupt controller from the different types of interrupt controllers.
The circuitry for both interrupt controllers is preferably implemented on a single computer design with a registered bit that may be toggled to invoke either interrupt method. This register bit is logically located in the reserved system address space and thus protected from errant or malicious application software. Since PC-origin OS's such as Microsoft's Windows NT™ or IBM's OS/2™ are unaware of other interrupt methods and expect a hardware implementation of the PC interrupt method, any system implementing the bimodal interrupt structure described herein will default to the PC interrupt method.
The default method is set by the Initial Program Load (IPL) code which is customized to the specific host system and is contained in Read Only Memory (ROM) hardware. The IPL code can examine the boot record from the operating system about to be loaded and if the IPL code recognizes the operating system type, it can then select the proper interrupt controller via the register bit. Other OS's can be made "aware" of the bimodal nature of the interrupt hardware and can switch into the high-performance PowerPC™ interrupt mode.
These and other advantages of the aspects of the present invention will be more fully understood in conjunction with the following detailed description and accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a system for selecting an interrupt system in a multiprocessor in accordance with the present invention.
DESCRIPTION OF THE INVENTION
The present invention is directed toward an improvement in a multiprocessor system. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
A system and method is provided that allows for the detection of operating systems that are being utilized in the multiprocessing environment, and then the selection of the appropriate interrupt controller. In a preferred embodiment, circuitry is utilized to implement the present invention. However, one of ordinary skill in the art recognizes that the present invention could be implemented on a computer readable medium and that use would be within the spirit and scope of the present invention.
In a preferred embodiment, the circuitry for both interrupt controllers is implemented on a single computer design with a registered bit that may be toggled to invoke either interrupt controller. This register bit is logically located in the reserved system address space and thus protected from errant or malicious application software.
To more particularly describe the present invention, refer now to FIG. 1, which is a block diagram of a multiprocessor system (MP) 10 including an interrupt selection system. The MP system includes a plurality of central processing units CPUs 12. The CPU 12 shares memory and I/O space 15 of the addressable memory space 14.
The MP system includes a selector, in this case multiplexer 16 which is controlled by a bit in a system control register 18 in the addressable space 14. The multiplexer 16 receives interrupt signals from interrupt controllers 20 and 22 where each of the interrupt controllers 20 and 22 are utilized for different types of operating systems. Through the use of a bit within the register 18 to select the appropriate interrupt system 20 and 22 a multiprocessing system is provided that has improved performance. The register 18 is in a reserved system space 19 that is at a higher privilege level than application software.
In a preferred embodiment, the circuitry for selecting both interrupt controllers is implemented on a single computer design with a registered bit that may be toggled to invoke either interrupt method. This register bit is logically located in the reserved system address space and thus protected from errant or malicious application software.
Since PC-origin OS's such as Microsoft's Windows NT™ or IBM's OS/2™ which are compatible with Intel X86 based architectures are unaware of other interrupt methods and expect a hardware implementation of the PC interrupt method, any system implementing the bimodal interrupt structure described herein will default to the PC interrupt method. In a preferred embodiment, the default method is set by the Initial Program Load (IPL) code which is customized to the specific host system and is contained in Read Only Memory (ROM) hardware. The IPL code can examine the boot record from the operating system about to be loaded and if the IPL code recognizes the operating system type, it can then select the proper interrupt controller via the register bit. Other OS's can be made "aware" of the bimodal nature of the interrupt hardware and can switch into the high-performance PowerPC™ architecture interrupt mode.
Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. For example, one of ordinary skill in the art will readily recognize that although the selection system has been described in the context of operating systems compatible with the PowerPC™ architecture and Intel X86 compatible architectures, the selection system could be utilized with a variety of operating systems and their use would be within the spirit and scope of the present invention. In addition, although the present invention has been discussed in the context of two different types of interrupt controllers, one of ordinary skill in the art will readily recognize that any number of controllers could be utilized. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications applications and embodiments within the scope thereof.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims (15)

We claim:
1. A system for allowing different operating systems to be utilized in a multiprocessing system, each of the different types of operating systems requiring different types of interrupt controllers, the system comprising:
means for detecting which of the different operating systems is utilized within the multiprocessing system; and
means responsive to the detecting means for selecting the appropriate interrupt controller from the different types of interrupt controllers.
2. The system of claim 1 in which different types of processor architectures can be utilized.
3. The system of claim 1 in which the detecting means comprises an internal program load code for detecting the operating system by examining a boot record for the operating system.
4. The system of claim 1 in which the detecting means comprises the operating system detecting a bimodal nature of an interrupt and then switching into a particular interrupt mode.
5. The system of claim 3 in which the selector means comprises a multiplexer which is responsive to a bit being toggled to invoke the appropriate interrupt controller.
6. The system of claim 5 in which the different processor architectures comprise an Intel X86 compatible architecture and an architecture utilizing a distributed interrupt method.
7. A method for allowing different operating systems to be utilized in a multiprocessing system, each of the different operating systems requiring different types of interrupt controllers, the method comprising the steps of:
(a) detecting which of the different operating systems is utilized within the multiprocessing system; and
(b) selecting the appropriate interrupt controller from the different types of interrupt controllers.
8. The method of claim 7 in which different types of processor architectures can be utilized.
9. The method of claim 7 in which the detecting step (a) comprises detecting the operating system by examining a boot record for the operating system.
10. The method of claim 7 in which the detecting step comprises the operating system detecting a bimodal nature of an interrupt and then switching into a particular interrupt mode.
11. The method of claim 10 in which the selecting step (b) comprises toggling a bit to invoke the appropriate interrupt controller.
12. The method of claim 11 in which the different processor architectures comprise an Intel X86 compatible architecture and an architecture utilizing a distributed interrupt method.
13. A system for allowing an operating system for an architecture utilizing a distributed interrupt method and an Intel X86 compatible operating system to be selectively utilized in a multiprocessing system, the system comprising:
means for detecting which of the operating system for the architecture utilizing a distributed interrupt method and the Intel X86 compatible operating system is utilized within the multiprocessing system; and
a multiplexer responsive to the state of a bit for selecting an appropriate interrupt controller.
14. The system of claim 13 in which the detecting means comprise an internal program load code for detecting the operating system by examining a boot record for the operating system.
15. The system of claim 13 in which the detecting means comprises the operating system detecting a bimodal nature of the interrupt and then switching into a particular interrupt mode.
US08/591,245 1996-01-18 1996-01-18 System and method for selecting an interrupt system based upon the operating system of a multiprocessor system Expired - Lifetime US5802350A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US08/591,245 US5802350A (en) 1996-01-18 1996-01-18 System and method for selecting an interrupt system based upon the operating system of a multiprocessor system
KR1019960047595A KR100259456B1 (en) 1996-01-18 1996-10-23 A system and method for selecting an interrupt system for a high performance multiprocessor system
JP31398596A JP3525984B2 (en) 1996-01-18 1996-11-25 System and method for selecting an interrupt system for a high performance multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/591,245 US5802350A (en) 1996-01-18 1996-01-18 System and method for selecting an interrupt system based upon the operating system of a multiprocessor system

Publications (1)

Publication Number Publication Date
US5802350A true US5802350A (en) 1998-09-01

Family

ID=24365700

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/591,245 Expired - Lifetime US5802350A (en) 1996-01-18 1996-01-18 System and method for selecting an interrupt system based upon the operating system of a multiprocessor system

Country Status (3)

Country Link
US (1) US5802350A (en)
JP (1) JP3525984B2 (en)
KR (1) KR100259456B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6357003B1 (en) * 1998-10-21 2002-03-12 Silicon Graphics, Inc. Advanced firmware boot sequence x86 computer system that maintains legacy hardware and software compatibility
EP3255544A1 (en) * 2016-06-08 2017-12-13 Virtual Open Systems Interrupt controller

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4261034A (en) * 1979-07-02 1981-04-07 Computer Automation, Inc. Remote distributed interrupt control for computer peripherals
US4482954A (en) * 1979-09-27 1984-11-13 U.S. Philips Corporation Signal processor device with conditional interrupt module and multiprocessor system employing such devices
US5099414A (en) * 1988-06-24 1992-03-24 International Computers Limited Interrupt handling in a multi-processor data processing system
US5129064A (en) * 1988-02-01 1992-07-07 International Business Machines Corporation System and method for simulating the I/O of a processing system
US5175853A (en) * 1990-10-09 1992-12-29 Intel Corporation Transparent system interrupt
US5179707A (en) * 1990-06-01 1993-01-12 At&T Bell Laboratories Interrupt processing allocation in a multiprocessor system
US5187802A (en) * 1988-12-26 1993-02-16 Hitachi, Ltd. Virtual machine system with vitual machine resetting store indicating that virtual machine processed interrupt without virtual machine control program intervention
US5297282A (en) * 1991-05-29 1994-03-22 Toshiba America Information Systems, Inc. Resume processing function for the OS/2 operating system
US5452462A (en) * 1992-05-15 1995-09-19 Fujitsu Limited Global communication interrupt control system for communication between real and virtual machine systems using global communication functions of a shared memory
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5511200A (en) * 1993-12-01 1996-04-23 Intel Corporation Method and apparatus for providing an enhanced programmable priority interrupt controller
US5590312A (en) * 1992-12-07 1996-12-31 Intel Corporation Method and apparatus for emulating circuitry in a computer system using a system management interrupt
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831044B2 (en) * 1989-09-18 1996-03-27 日本電気株式会社 Interrupt processing completion monitoring method

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4261034A (en) * 1979-07-02 1981-04-07 Computer Automation, Inc. Remote distributed interrupt control for computer peripherals
US4482954A (en) * 1979-09-27 1984-11-13 U.S. Philips Corporation Signal processor device with conditional interrupt module and multiprocessor system employing such devices
US5129064A (en) * 1988-02-01 1992-07-07 International Business Machines Corporation System and method for simulating the I/O of a processing system
US5099414A (en) * 1988-06-24 1992-03-24 International Computers Limited Interrupt handling in a multi-processor data processing system
US5187802A (en) * 1988-12-26 1993-02-16 Hitachi, Ltd. Virtual machine system with vitual machine resetting store indicating that virtual machine processed interrupt without virtual machine control program intervention
US5179707A (en) * 1990-06-01 1993-01-12 At&T Bell Laboratories Interrupt processing allocation in a multiprocessor system
US5175853A (en) * 1990-10-09 1992-12-29 Intel Corporation Transparent system interrupt
US5297282A (en) * 1991-05-29 1994-03-22 Toshiba America Information Systems, Inc. Resume processing function for the OS/2 operating system
US5452462A (en) * 1992-05-15 1995-09-19 Fujitsu Limited Global communication interrupt control system for communication between real and virtual machine systems using global communication functions of a shared memory
US5590312A (en) * 1992-12-07 1996-12-31 Intel Corporation Method and apparatus for emulating circuitry in a computer system using a system management interrupt
US5511200A (en) * 1993-12-01 1996-04-23 Intel Corporation Method and apparatus for providing an enhanced programmable priority interrupt controller
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6357003B1 (en) * 1998-10-21 2002-03-12 Silicon Graphics, Inc. Advanced firmware boot sequence x86 computer system that maintains legacy hardware and software compatibility
EP3255544A1 (en) * 2016-06-08 2017-12-13 Virtual Open Systems Interrupt controller

Also Published As

Publication number Publication date
JP3525984B2 (en) 2004-05-10
KR970059924A (en) 1997-08-12
KR100259456B1 (en) 2000-06-15
JPH09204313A (en) 1997-08-05

Similar Documents

Publication Publication Date Title
US5729760A (en) System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode
US6408386B1 (en) Method and apparatus for providing event handling functionality in a computer system
US6219774B1 (en) Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture
US5987604A (en) Method and apparatus for providing execution of system management mode services in virtual mode
EP0382470B1 (en) Computer with improved keyboard password functions
JP3364495B2 (en) Additional board
US7917740B1 (en) Virtualization assist for legacy x86 floating point exception handling
KR950002945B1 (en) Apparatus and method for loading a system reference diskette image from a system partition in a personal computer system
US7467285B2 (en) Maintaining shadow page tables in a sequestered memory region
JP3364496B2 (en) Additional board
US5692219A (en) System and method for disabling or re-enabling PCI-compliant devices in a computer system by masking the idsel signal with a disable or re-enable signal
EP0382468A2 (en) Power-on password functions for computer system
US20010018721A1 (en) Upgrade card for a computer system
US6775734B2 (en) Memory access using system management interrupt and associated computer system
EP0437550B1 (en) Information processing system emulation apparatus and method
JP2002539524A (en) Apparatus and method for handling peripheral device interrupts
CN116583840A (en) Fast peripheral component interconnect protection controller
WO2006069364A2 (en) System and method for control registers accessed via private operations
JP3003968B2 (en) Interrupt processing program selection device and processing method
US5802350A (en) System and method for selecting an interrupt system based upon the operating system of a multiprocessor system
KR920008457B1 (en) Multi-bus microcomputer system
EP0575171B1 (en) Enhanced system management method and apparatus
US6105101A (en) 16 bit bios interrupt calls under 32 bit protected mode application
US6263412B1 (en) Method and apparatus for RAM emulation using a processor register set
JP2535086B2 (en) Ring reduction logic device

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FRANZ, KEENAN WYNN;PURCELL, JOHN DAVID;REICK, KEVIN F.;REEL/FRAME:007841/0634;SIGNING DATES FROM 19951130 TO 19951204

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12