US5760662A - Methods and apparatus for improving frequency response of integrated RC filters with additional ground pins - Google Patents
Methods and apparatus for improving frequency response of integrated RC filters with additional ground pins Download PDFInfo
- Publication number
- US5760662A US5760662A US08/608,433 US60843396A US5760662A US 5760662 A US5760662 A US 5760662A US 60843396 A US60843396 A US 60843396A US 5760662 A US5760662 A US 5760662A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/06—Frequency selective two-port networks including resistors
Definitions
- the present invention relates generally to techniques for improving the integrity of integrated resistor/capacitor (IRC) networks. More particularly, the present invention relates to techniques for improving the amplitude versus frequency response (AFR) of IRC networks at ultra-high frequencies, e.g., above 1 GHz.
- IRC integrated resistor/capacitor
- Resistor/capacitor networks have long been employed as cost-effective frequency filters in electromagnetic interference (EMI) applications, radio frequency interference (RFI) applications, or the like.
- EMI electromagnetic interference
- RFID radio frequency interference
- resistor/capacitor low pass filters are implemented by discrete components on a circuit board.
- designers have employed thin film technologies to implement the resistor/capacitor networks in integrated form.
- IRC integrated resistor/capacitor networks
- the amplitude versus frequency response refers to the ability of the integrated resistor/capacitor (IRC) filter to pass signals having frequencies below a certain threshold with minimum attenuation, while increasing the attenuation of signals above a certain threshold.
- the AFR is important because, for example, in EMI/RFI filtering applications, standards, rules and regulations promulgated by the regulatory bodies, e.g., the Federal Communication Commission (FCC), dictate that electronic devices must be shielded and/or filtered to minimize or attenuate signals having frequencies above a certain threshold frequency limit.
- FCC Federal Communication Commission
- FIG. 1 illustrates the schematic of the ideal RC low-pass filter 102.
- resistors R1 and R2 are typically substantially equal in value and, together with capacitor C, determine the value of the threshold frequency.
- the input terminal and the output terminal are labeled as such for ease of discussion, either terminal 104 or terminal 106 can act as the input terminal with the other acting as the output terminal since ideal RC filters are typically symmetrical.
- FIG. 2 shows the relative amplitude (in dB) versus frequency of the ideal RC filter of FIG. 1 with specific values of R1, R2, and C for the frequency range from 0 to 3 GHz.
- the relative amplitude is expressed as 20 log (output/input) versus frequency. Note that at about 3 GHz, the relative amplitude of the output signal is slightly above about -36 dB.
- FIG. 3 illustrates the equivalent circuit of the IRC that results when ideal RC filter 102 of FIG. 1 is implemented in an integrated circuit package.
- FIG. 3 also shows a parasitic resistor R P , representing the equivalent parasitic resistance associated with the resistance of the semiconductor RC structure.
- R P the resistance associated with the bottom plate of the capacitor in the RC semiconductor structure may contribute to the resistance value of parasitic resistor R P .
- parasitic capacitors C P1 and C P2 , representing the parasitic capacitance attributed to the bond pads of the RC network when the network is fabricated on the semiconductor wafer.
- Parasitic inductance L IN (bond) represents the inductance associated with the bonding wire employed to bond the input pin on the IC package to its associated bonding pad on the semiconductor die that implements the RC filters.
- parasitic inductor L OUT (bond) represents the inductance due to the bonding structure in the package, particularly due to the bonding wire between the output pin and its associated bonding pad on the die.
- Inductor L GROUND is a function of the inductance of the bonding wires from the ground pins of the IC package to the grounded leadframe.
- Parasitic inductor L GROUND and capacitor C of the RC filter act as a tuned circuit.
- the inductance value associated with parasitic inductor L GROUND appears to be the critical inductance in terms of the high frequency performance of the integrated RC network. To improve the attenuation of the output signal of the integrated RC network, particularly at the ultra-high frequency ranges, the inductance associated with parasitic inductor L GROUND should be substantially minimized or eliminated.
- QSOP Quarter Size Small Outline Package
- SSOP Small Outline Packaging
- JDEC Joint Electronic Device Engineering Committee
- EIA Electronic Industry Association
- FIG. 4A schematically illustrates a prior art integrated circuit, which implements 8 integrated resistor/capacitor (IRC) filters on a 20-pin QSOP package.
- IRC integrated resistor/capacitor
- FIG. 4B The frequency response of the integrated RC network of FIG. 4A is shown in FIG. 4B. Because of the existence of the tuned circuit comprising parasitic inductor L GROUND and capacitor C of the RC filter (see FIG. 3), the AFR of FIG. 4B has a point 402 of maximum attenuation. Point 402 may be thought of as the mathematical zero of the AFR. The frequency of this point 402 is called the frequency of maximum rejection. As the value of parasitic inductor L GROUND is reduced, the maximum rejection frequency becomes higher, i.e., point 402 moves to the right on the frequency axis, and results in an improvement of the frequency response at the higher frequency ranges. With reference to FIGS.
- the maximum rejection frequency at test pins 5 and 16 (which together forms an RC filter) is about 915 MHz.
- the attenuation of the input signal at 3 GHz for this integrated resistor/capacitor network at the above test pins is about 15 dB (point 404 in FIG. 4B).
- the attenuation would have been, as shown in FIG. 2, about 36 dB at 3 GHz.
- the 15 dB of attenuation at 3 GHz provided by the prior art IRC has proven to be less than satisfactory for applications involving modern high speed/data devices.
- manufacturers e.g., those involved in telecommunication and portable telephone applications, to require that integrated resistor/capacitor networks must have an attenuation of no less than about 30 dB at 3 GHz.
- the invention relates, in one embodiment, to a method for maximizing the attenuation of ultra-high frequency signals filtered through resistor/capacitor filters of an integrated resistor/capacitor network.
- the integrated resistor/capacitor network is implemented in a QSOP package.
- the method includes the step of employing at least six pins of the QSOP package as ground pins for the integrated resistor/capacitor network.
- the method relates to a QSOP integrated resistor/capacitor network.
- the QSOP integrated resistor/capacitor network includes resistor/capacitor filters implemented in a QSOP package in integrated form.
- the QSOP integrated resistor/capacitor network includes at least six ground pins for coupling capacitors of the resistor/capacitor filters with a common ground to maximize the attenuation of ultra-high frequency signals filtered through the resistor/capacitor filters.
- FIG. 1 illustrates the schematic of the ideal RC low-pass filter.
- FIG. 2 shows the relative amplitude (in dB) versus frequency response curve of the ideal RC filter of FIG. 1 for the frequency range from 0 to 3 GHz.
- FIG. 3 illustrates the equivalent circuit of the IRC that results when ideal RC filter of FIG. 1 is implemented in an integrated circuit package.
- FIG. 4A schematically illustrates a prior art integrated circuit, which implements 8 integrated resistor/capacitor (IRC) filters on a 20-pin QSOP package.
- IRC integrated resistor/capacitor
- FIG. 4B The relative amplitude versus frequency response of the integrated RC network of FIG. 4A is shown in FIG. 4B.
- FIG. 5A illustrates, in accordance with one aspect of the present invention, a technique for improving the ultra-high frequency AFR of integrated resistor/capacitor networks that are implemented in 20-pin QSOP packages.
- FIG. 5B shows the AFR of the integrated RC network of FIG. 5A.
- FIG. 6 illustrates the leadframe of a typical 20-pin QSOP package.
- FIG. 7A illustrates an embodiment wherein pins 5, 6, 7, 14, 15, and 16 of the 20-pin QSOP package are employed as the ground pins.
- FIG. 7B shows the AFR of the integrated RC network of FIG. 7A.
- FIG. 8A illustrates in yet another embodiment of the present invention an integrated RC network wherein four of the six ground pins are corner pins of the 20-pin QSOP package.
- FIG. 8B is the AFR obtained for the IRC network of FIG. 8A
- FIG. 9A illustrates in yet another embodiment of the present invention an integrated RC network wherein four of the eight ground pins are corner pins of the 20-pin QSOP package.
- FIG. 9B is the AFR obtained for the IRC network of FIG. 9A
- FIG. 10A illustrates in yet another embodiment of the present invention an integrated RC network which employs 8 ground pins in a 24-pin QSOP package.
- FIG. 10B shows the AFR that results when pins 2, 5, 8, 11, 14, 17, 20, and 23 are employed to ground the 24-pin QSOP IRC network, as is done in the embodiment of FIG. 10A.
- FIG. 11 shows the leadframe of a representative 24-pin QSOP package.
- FIG. 12A illustrates yet another embodiment of the 24-pin QSOP integrated RC network wherein four of the eight ground pins are the corner pins of the QSOP package.
- FIG. 12B shows the AFR of the IRC network of FIG. 12A.
- FIG. 5A illustrates, in accordance with one aspect of the present invention, a technique for improving the ultra-high frequency AFR of integrated resistor/capacitor networks that are implemented in 20-pin QSOP packages.
- pins 2, 9, 12, and 19 are employed as the ground pins that couple to the common ground plane, i.e., the common back plane, of the integrated RC network.
- FIG. 5B shows the AFR of the integrated RC network of FIG. 5A taken at arbitrary test pins, e.g., pins 5 and 16.
- the maximum rejection frequency has moved from approximately 950 MHz (point 402 of FIG. 4B) to over 1.2 GHz (point 502 of FIG. 5B).
- the attenuation at 3 GHz is also improved, from about 15 dB at 3 GHz (point 404 of FIG. 4B), to about 25 dB at 3 GHz (point 504 of FIG. 5B).
- the improvement in the AFR over prior art IRC network of FIG. 4A is, at least in part, a result of the reduction in the value of parasitic inductor L GROUND .
- the shorter pins 2, 9, 12, and 19 of the 20-pin QSOP package are advantageously employed as ground pins instead of pins 1, 10, 11, and 20 (as in the case of prior art FIG. 4A). Since the ground pins are shorter in the present embodiment of the present invention, the value of parasitic inductor L GROUND is correspondingly lower.
- pins 2, 9, 12, and 19 are employed as ground pins (as in the case of the prior art FIG. 4A).
- the shorter bonding wires also contribute to the reduction in the value of parasitic inductor L GROUND .
- pins 2, 9, 12, and 19 which are employed as ground pins in the inventive IRC configuration of FIG. 5A, are shorter than pins 1,10, 11, and 20, which are employed as ground pins in the prior art IRC of FIG. 4A.
- the total length of the bonding wires between pins 2, 9, 12, and 19 to the pad of the leadframe are also shorter than the total length of the bonding wires from pins 1, 10, 11, and 20 to their respective bonding pads on die 602.
- the shorter pins and shorter bonding wires result in a smaller inductance value for parasitic inductor L GROUND thereby improving the frequency response of the IRC network of FIG. 5A at the ultra-high frequency range, e.g., above 1 GHz.
- pins 5, 6, 7, 14, 15, and 16 are employed as the ground pins that couple each RC filter to the common ground plane of the integrated RC network.
- the semiconductor die employed in this embodiment is substantially similar to that employed in the embodiment of FIG. 5A, and is indeed substantially similar to the dies employed the other IRC's described herein. Since the dies employed in the other IRC's described herein are substantially similar, the frequency response effect attributed to the die can be ruled out when comparing the AFR's of the various embodiments.
- any of these pins 5, 6, 7, 14, 15, and 16 is shorter than any of pins 2, 9, 12, and 19, which are employed as the ground pins in the IRC network of FIG. 5A. Consequently, it is expected that the frequency response at the ultra-high frequency range should improve due to the expected reduction in the value of parasitic capacitance L GROUND . Further, since six pins are employed as ground pins in the embodiment of FIG. 7A, it is expected that the effective inductance that contributes to L GROUND would be less than that associated with the four ground pins of FIG. 5A (due to the nature of inductors in parallel).
- the amplitude versus frequency response plot of FIG. 7B which is obtained at arbitrary test pins, e.g., pins 2 and 19, shows that the maximum rejection frequency is worse, i.e., about 915 MHz in FIG. 7B (versus over 1.2 GHz in FIG. 5B).
- the attenuation of about 21 dB at 3 GHz in FIG. 7B is an improvement over the 15 dB attenuation achieved by the prior art IRC of FIGS. 4A and 4B, it is substantially below the 24 dB of attenuation seen in the embodiment of FIGS. 5A and 5B.
- the AFR result shown in FIG. 7B being counter to expectation, is therefore surprising and serves to illustrate the unpredictable nature of the frequency response of IRC's in the higher frequency ranges. As the drawing indicates, pins 1, 10, 11, 20 are not connected in FIG. 7 to simplify the experiment.
- the six pins are again employed as ground pins.
- the six ground pins of FIG. 8A now include the four corner pins, i.e., pins 1, 10, 11, and 20 of the 20-pin QSOP package.
- the two other ground pins are arranged in equal numbers on opposite sides of the QSOP package. In the embodiment of FIG. 7A, they are pins 7 and 14.
- the total length of the six ground pins employed in the IRC configuration of FIG. 8A is longer than the total length of the six ground pins employed in the IRC configuration of FIG. 7A. Therefore, one would expect that the inductance associated with parasitic inductor L GROUND would increase and the attenuation of the IRC configuration of FIG. 8A would be worse at the higher frequency ranges than that associated with the embodiment of FIG. 7A.
- FIG. 8B is the AFR obtained from arbitrary test pins, e.g., pins 5 and 16 of FIG. 8A.
- the attenuation at 3 GHz is better (about 28 dB) than that seen in FIG. 7B (about 21 dB).
- the maximum rejection frequency at point 802 of FIG. 8B (above about 1.6 GHz) is an improvement over that of FIG. 7B (about 915 MHz). This unexpected result again illustrates the unpredictable nature of the frequency response of the IRC networks at the high frequency ranges.
- FIG. 9A eight pins are employed to ground the IRC network.
- the eight ground pins include the four corner pins of the 20-pin QSOP package, i.e., pins 1, 10, 11, and 20.
- the four other ground pins are arranged in equal numbers on opposite sides of the QSOP package. In the embodiment of FIG. 9A, they are implemented by pins 4, 7, 14, and 17. In this configuration, it is expected that the parasitic inductance associated with parasitic inductor L GROUND would be substantially less than that of prior art FIG. 4A, since there are more inductors in parallel to reduce the effective inductance contributed by the ground pins.
- FIG. 9B illustrates the relative amplitude versus frequency response of the integrated resistor/capacitor network of FIG. 9A.
- the maximum rejection frequency at point 902 is shown to be over about 2 GHz, and the attenuation at 3 GHz is about 36 dB.
- this result represents a significant improvement over the prior art configuration of FIG. 4A.
- the configuration shown in FIG. 9A also has routing advantages when the IC package that implements the integrated resistor/capacitor network of FIG. 9A is placed on the circuit board. This is because the RC filters are coupled in pairs, and the terminals to each pair are separated and isolated from the terminals of other pairs by ground pins. It is contemplated that changes to the locations of the interior ground pins, i.e., those not disposed at the corners of the QSOP package, may be made without significantly impacting the frequency response of the resulting IRC configurations.
- changing the ground pins from pin 4 to pin 2 or from pin 7 to pin 8 may not have a significant impact on the frequency response as long as the corner pins of the 20-pin QSOP package, i.e., pins 1, 10, 11, and 20, are still employed as four of the eight ground pins.
- FIG. 9A results in a significantly improved AFR at the ultra-high frequency range, the use of eight pins out of twenty as ground pins in a 20-pin QSOP package leaves only twelve pins remaining to implement the RC filters. As a result, the maximum number of RC filters that can be achieved in this embodiment is six.
- a 24-pin QSOP package is advantageously employed to increase the number of filters that can be implemented when more than four pins are employed as ground pins.
- FIG. 10B shows the AFR that results when pins 2, 5, 8, 11, 14, 17, 20, and 23 are employed to ground the 24-pin QSOP IRC network, as is done in the embodiment of FIG. 10A.
- the attenuation is about 24 dB at 3 GHz
- the rejection frequency is about 1 GHz at test pin 1 and test pin 12.
- pins 1 and 12 represent the pins where the frequency response appears to be the worst.
- the frequency response at 3 GHz in FIG. 10B is about the same as that obtained by the configuration of FIG. 5A, i.e., about 24 dB.
- FIG. 11 shows the leadframe of a representative 24-pin QSOP package to facilitate understanding. Note that the 24-pin QSOP package occupies substantially the same footprint as the 20-pin QSOP package. Thus, the use of a 24-pin QSOP package to implement IRC's is particularly advantageous since it can accommodate more filters per IC without taking up additional room on the circuit board.
- FIG. 12A illustrates, in one embodiment of the invention, a novel IRC network configuration wherein four of the eight ground pins are the corner pins of the 24-pin QSOP package, i.e., pins 1, 12, 13, and 24.
- the other four ground pins are arranged in equal numbers on opposite sides of the QSOP package. In the embodiment of FIG. 12A, they are pins 5, 8, 17, and 20.
- changes to the locations of the interior ground pins i.e., those not disposed at the corners of the QSOP package, may be made without significantly impacting the frequency response of the resulting IRC configurations.
- changing the ground pins from pin 5 to pin 4 or from pin 17 to pin 16 may not have a significant impact on the frequency response as long as the corner pins of the 24-pin QSOP package, i.e., pins 1, 12, 13, and 24 are still employed as four of the eight ground pins.
- FIG. 12B shows the AFR of the IRC network of FIG. 12A.
- the maximum rejection frequency is shown to be almost 1.8 GHz, and the attenuation at 3 GHz is about 31 dB. This is clearly an improvement over the results obtained in FIG. 10B.
- the ground pins in FIG. 12A are longer than those employed in FIG. 10A, and since the same number of pins, i.e., eight, are employed to ground the IRC networks, one would expect that the effective inductance associated with the IRC network of FIG. 12A would be larger than that associated with the IRC network of FIG. 10A. Nevertheless, FIG. 12B shows that the frequency response is improved.
- the corner pins are employed as ground pins.
- the use of corner pins of the QSOP package irrespective whether the QSOP package has 20 pins or 24 pins, appears to provide the best AFR when combined with additional ground pins in between. These results appear to be true although these corner pins are longer than other non-corner pins in the QSOP package.
- the attenuation at 3 GHz for the IRC network of FIG. 12A is somewhat worse than that associated with the IRC network of FIG. 9A. This is surprising, since both QSOP IRC packages employ the same number of pins, employ four corner pins to ground their IRC networks, and they both have approximately the same footprint on the circuit board.
- the frequency response of the embodiment shown in FIG. 12A is slightly worse than that of FIG. 9A
- the use of the 24-pin QSOP package advantageously allows the designer to put eight RC filters in the same amount of space while still achieving an attenuation of above 30 dB at 3 GHz.
Abstract
Description
Claims (20)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/608,433 US5760662A (en) | 1996-02-28 | 1996-02-28 | Methods and apparatus for improving frequency response of integrated RC filters with additional ground pins |
EP97914806A EP0883929A4 (en) | 1996-02-28 | 1997-02-28 | Methods and apparatus for improving frequency response of integrated rc filters |
PCT/US1997/003090 WO1997032395A1 (en) | 1996-02-28 | 1997-02-28 | Methods and apparatus for improving frequency response of integrated rc filters |
JP9531119A JP2000506331A (en) | 1996-02-28 | 1997-02-28 | Method and apparatus for improving the frequency characteristics of an integrated RC filter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/608,433 US5760662A (en) | 1996-02-28 | 1996-02-28 | Methods and apparatus for improving frequency response of integrated RC filters with additional ground pins |
Publications (1)
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US5760662A true US5760662A (en) | 1998-06-02 |
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Application Number | Title | Priority Date | Filing Date |
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US08/608,433 Expired - Lifetime US5760662A (en) | 1996-02-28 | 1996-02-28 | Methods and apparatus for improving frequency response of integrated RC filters with additional ground pins |
Country Status (4)
Country | Link |
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US (1) | US5760662A (en) |
EP (1) | EP0883929A4 (en) |
JP (1) | JP2000506331A (en) |
WO (1) | WO1997032395A1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6194979B1 (en) * | 1999-03-18 | 2001-02-27 | Cts Corporation | Ball grid array R-C network with high density |
US6326677B1 (en) | 1998-09-04 | 2001-12-04 | Cts Corporation | Ball grid array resistor network |
FR2817412A1 (en) * | 2000-11-30 | 2002-05-31 | St Microelectronics Sa | INTEGRATED LOW PASS OR BAND PASS FILTER |
US6657522B2 (en) * | 2002-02-01 | 2003-12-02 | M/A-Com | Wide bandwidth bias tee |
US20050024839A1 (en) * | 2003-07-31 | 2005-02-03 | Bloom Terry R. | Ball grid array package |
US20050035450A1 (en) * | 2003-08-13 | 2005-02-17 | David Poole | Ball grid array package having testing capability after mounting |
US20140167883A1 (en) * | 2012-12-17 | 2014-06-19 | Continental Automotive Systems, Inc. | Fast response high-order low-pass filter |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2007221812B2 (en) * | 2000-01-18 | 2010-04-29 | Isis Pharmaceuticals, Inc. | Antisense modulation of PTP1B expression |
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US3775838A (en) * | 1972-04-24 | 1973-12-04 | Olivetti & Co Spa | Integrated circuit package and construction technique |
US4937660A (en) * | 1988-12-21 | 1990-06-26 | At&T Bell Laboratories | Silicon-based mounting structure for semiconductor optical devices |
US5338974A (en) * | 1993-03-17 | 1994-08-16 | Spectrian, Inc. | RF power transistor package |
US5355014A (en) * | 1993-03-03 | 1994-10-11 | Bhasker Rao | Semiconductor device with integrated RC network and Schottky diode |
US5370766A (en) * | 1993-08-16 | 1994-12-06 | California Micro Devices | Methods for fabrication of thin film inductors, inductor networks and integration with other passive and active devices |
US5493259A (en) * | 1992-10-13 | 1996-02-20 | The Whitaker Corporation | High voltage, low pass filtering connector with multiple ground planes |
US5495387A (en) * | 1991-08-09 | 1996-02-27 | Murata Manufacturing Co., Ltd. | RC array |
US5514612A (en) * | 1993-03-03 | 1996-05-07 | California Micro Devices, Inc. | Method of making a semiconductor device with integrated RC network and schottky diode |
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JP2938344B2 (en) * | 1994-05-15 | 1999-08-23 | 株式会社東芝 | Semiconductor device |
-
1996
- 1996-02-28 US US08/608,433 patent/US5760662A/en not_active Expired - Lifetime
-
1997
- 1997-02-28 WO PCT/US1997/003090 patent/WO1997032395A1/en not_active Application Discontinuation
- 1997-02-28 JP JP9531119A patent/JP2000506331A/en active Pending
- 1997-02-28 EP EP97914806A patent/EP0883929A4/en not_active Withdrawn
Patent Citations (8)
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US3775838A (en) * | 1972-04-24 | 1973-12-04 | Olivetti & Co Spa | Integrated circuit package and construction technique |
US4937660A (en) * | 1988-12-21 | 1990-06-26 | At&T Bell Laboratories | Silicon-based mounting structure for semiconductor optical devices |
US5495387A (en) * | 1991-08-09 | 1996-02-27 | Murata Manufacturing Co., Ltd. | RC array |
US5493259A (en) * | 1992-10-13 | 1996-02-20 | The Whitaker Corporation | High voltage, low pass filtering connector with multiple ground planes |
US5355014A (en) * | 1993-03-03 | 1994-10-11 | Bhasker Rao | Semiconductor device with integrated RC network and Schottky diode |
US5514612A (en) * | 1993-03-03 | 1996-05-07 | California Micro Devices, Inc. | Method of making a semiconductor device with integrated RC network and schottky diode |
US5338974A (en) * | 1993-03-17 | 1994-08-16 | Spectrian, Inc. | RF power transistor package |
US5370766A (en) * | 1993-08-16 | 1994-12-06 | California Micro Devices | Methods for fabrication of thin film inductors, inductor networks and integration with other passive and active devices |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6326677B1 (en) | 1998-09-04 | 2001-12-04 | Cts Corporation | Ball grid array resistor network |
US6194979B1 (en) * | 1999-03-18 | 2001-02-27 | Cts Corporation | Ball grid array R-C network with high density |
US6788168B2 (en) | 2000-11-30 | 2004-09-07 | Stmicroelectronics S.A. | Integrated low-pass or band-pass filter |
WO2002045263A1 (en) * | 2000-11-30 | 2002-06-06 | Stmicroelectronics S.A. | Integrated low-pass or band-pass filter |
US20030001693A1 (en) * | 2000-11-30 | 2003-01-02 | Fabrice Guitton | Integrated low-pass or band-pass filter |
FR2817412A1 (en) * | 2000-11-30 | 2002-05-31 | St Microelectronics Sa | INTEGRATED LOW PASS OR BAND PASS FILTER |
US6657522B2 (en) * | 2002-02-01 | 2003-12-02 | M/A-Com | Wide bandwidth bias tee |
US20050024839A1 (en) * | 2003-07-31 | 2005-02-03 | Bloom Terry R. | Ball grid array package |
US7180186B2 (en) | 2003-07-31 | 2007-02-20 | Cts Corporation | Ball grid array package |
US20070164433A1 (en) * | 2003-07-31 | 2007-07-19 | Bloom Terry R | Ball grid array package |
US20050035450A1 (en) * | 2003-08-13 | 2005-02-17 | David Poole | Ball grid array package having testing capability after mounting |
US6946733B2 (en) | 2003-08-13 | 2005-09-20 | Cts Corporation | Ball grid array package having testing capability after mounting |
US20140167883A1 (en) * | 2012-12-17 | 2014-06-19 | Continental Automotive Systems, Inc. | Fast response high-order low-pass filter |
US9431998B2 (en) * | 2012-12-17 | 2016-08-30 | Continental Automotive Systems, Inc. | Fast response high-order low-pass filter |
Also Published As
Publication number | Publication date |
---|---|
JP2000506331A (en) | 2000-05-23 |
EP0883929A1 (en) | 1998-12-16 |
WO1997032395A1 (en) | 1997-09-04 |
EP0883929A4 (en) | 2001-10-04 |
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