US5424652A - Method and apparatus for testing an unpackaged semiconductor die - Google Patents

Method and apparatus for testing an unpackaged semiconductor die Download PDF

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Publication number
US5424652A
US5424652A US07/896,297 US89629792A US5424652A US 5424652 A US5424652 A US 5424652A US 89629792 A US89629792 A US 89629792A US 5424652 A US5424652 A US 5424652A
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United States
Prior art keywords
traces
die
housing
interconnect
lid
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US07/896,297
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David R. Hembree
Warren M. Farnworth
Alan G. Wood
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Micron Technology Inc
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Micron Technology Inc
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Priority to US07/896,297 priority Critical patent/US5424652A/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: FARNWORTH, WARREN M., HEMBREE, DAVID R., WOOD, ALAN G.
Priority claimed from US08/192,391 external-priority patent/US5483174A/en
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433Sockets for IC's or transistors
    • G01R1/0483Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Abstract

A method and apparatus for testing a singularized semiconductor die prior to packaging the die, thereby allowing for the packaging or other use of only known good die. The apparatus employs a housing of ceramic or other workable material. Contact pads on the interior of the package are coupled to exterior leads with conductive traces. The back side of a semiconductor die to be tested is removably mounted to a lid, and the bond pads on the die are aligned with the contact pads on the interior of the package. The lid is attached to the package thereby electrically coupling the contact pads with the bond pads on the die. Since the package has conventional exterior form and function the package is operational as a functioning device.

Description

FIELD OF THE INVENTION

This invention relates to the field of semiconductor device testing. More specifically, a method and apparatus for testing an unpackaged semiconductor die is described.

BACKGROUND OF THE INVENTION

Many types of semiconductor devices are made using similar manufacturing procedures. A starting substrate, usually a thin wafer of silicon, is doped, masked, and etched through several process steps, the steps depending on the type of devices being manufactured. This process yields a number of die on each wafer produced. Each die on the wafer is given a brief test for full functionality, and the nonfunctional die are mechanically marked or mapped in software. This brief test is only a gross measure of functionality, and does not insure that a die is completely functional or has specifications that would warrant its assembly in a package.

If the wafer has a yield of grossly functional die which indicates that a good quantity of die from the wafer are likely to be fully operative, the die are separated with a die saw, and the nonfunctional die are scrapped while the rest are individually encapsulated in plastic packages or mounted in ceramic packages with one die in each package. After the die are packaged they are rigorously electrically tested. Components which turn out to be nonfunctional or which operate at questionable specifications are scrapped or devoted to special uses.

Packaging unusable die only to scrap them after testing is a waste of time and materials, and is therefore costly. Given the relatively low profit margins of commodity semiconductor components such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), this practice is uneconomical. However, no thorough and cost effective method of testing an unpackaged die is available which would prevent this unnecessary packaging of nonfunctional and marginally functional die.

It is proposed that multiple integrated circuit devices be packaged as a single unit, known as a multi chip module (MCM). This can be accomplished with or without conventional lead frames. This creates two problems compared to conventional test methods. Firstly, discrete testing is more difficult because the conventional lead frame package is not used. Furthermore, when multiple devices are assembled into a single package, the performance of the package is reduced to that of the die with the lowest performance. In other words, the ability to presort the individual dice is limited to that obtained through probe testing. Secondly, the packaging may have other limitations which are aggravated by burn-in stress conditions so that the packaging becomes a limitation for burn-in testing.

The practice of packaging die only to find the component must be scrapped can especially adversely affect yields on multi-chip modules (MCMs). With MCMs, several unpackaged die are assembled into a single component, then the component is tested as a single functional unit. If a single die is nonfunctional or operates outside of acceptable specifications, the entire component fails and all die in the package are scrapped or an attempt is made to "re-work" the MCM. There is presently no cost-effective way to reclaim the functioning die. Statistically, the yields of MCMs decrease in proportion to the increasing number of die in each module. The highest density modules have the lowest yields due to their increased total silicon surface area. For discretely packaged parts, if the product yield of good parts from preliminary testing to final shipment (probe-to-ship) is, for example, 95%, one would not be particularly concerned with packaging costs for the failed parts, if packaging costs are 10% of the product manufacturing costs. Where packaging costs are considerably higher, however, as in ceramic packaged parts, testing a die before packaging is economical when the cost of packaging divided by the package yield is equal to or greater than the cost of testing:

C.sub.DIE ×(C.sub.PACKAGE /Package Yield)=C.sub.DIE ×C.sub.ADDL.KGD

where

C=cost

CDIE =manufacturing cost of functional site

CADDL.KGD =additional cost of testing unpackaged die in order to produce known good die (KGD)

Note that in the case of discretely packaged parts, the cost of the die (CDIE) is essentially not a factor since it is the same on both sides of the equation. This changes in the case of MCMs having more than one part type, for example memory and a microprocessor. Scrapping (or reclaiming) the microprocessor after packaging because of malfunctioning memory is much more costly than scrapping a module containing only memory:

(C.sub.DIE)×(Number of Die/Die Yield)×C.sub.PACKAGE =C.sub.DIE ×C.sub.ADDL.KGD

The above equation must be modified to account for varied costs and yields of die in modules with mixed part types. With MCMs, the cost of packaging a failed part is proportional to the number of die in the module. In the case of a memory module having 16 die, where probe-to-ship yield of the die is 95%, the costs are:

16/0.95×C.sub.PACKAGE =C.sub.ADDL.KGD

so the additional costs of testing for known good die (KGD) may be 16 times the cost of testing an unrepairable module and still be economical. This, of course, is modified by the ability to repair failed modules.

Testing of unpackaged die before packaging would be desirable as it would result in reduced material waste, increased profits, and increased throughput. Using only known good die in multichip modules would increase yields significantly.

SUMMARY OF THE INVENTION

An object of the invention is to provide a means for testing and burning in a semiconductor die before it is packaged.

This and other objects of the invention were realized by temporarily placing a die in a ceramic package, then testing the assembled package. To temporarily package the die, a ceramic housing was manufactured having input/output leads electrically coupled with contacts on the interior of the package. In one embodiment, gold alloy was chosen as a material from which to manufacture the bumps because of its soft, conductive properties, but other workable materials are possible.

The back (noncircuit) side of a discrete semiconductor die was mounted to a lid, and bond pads on the die were aligned with the contacts on the interior of the package. The bond pads were then contacted with the contacts to form a temporary electrical contact therebetween. Since the semiconductor package had the form of a conventional package, conventional functional and parametric testing means was possible and completed. After testing the package, the lid was removed from the ceramic package body, and the gold bumps yielded without resulting damage to the die bond pads. The known good die is then available for packaging in a multichip module, for assembly in a conventional package, or for use in other systems using unpackaged die.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section of a first embodiment of the invention having a die mounted to a lid;

FIG. 2 is a top view of the FIG. 1 embodiment;

FIG. 3 is a cross section of a second embodiment of the invention in which a vacuum is used to secure a die to the lid during placement into a carrier;

FIG. 4 is a cross section of a third embodiment of the invention having a die mounted to the package housing; and

FIG. 5 is a cross section of a fourth embodiment of the invention in which metal contacts couple an interconnect with a lower housing member.

It should be emphasized that the drawings of the instant application are not to scale but are merely schematic representations and are not intended to portray the specific parameters or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a cross section, and FIG. 2 is a top view, describing an embodiment of the present invention. A housing 10 was manufactured from ceramic having a bottom shelf 12 for receiving a substrate insert 14 and a pair of "bond" shelves 16. Upon the bond shelves 16 were housing connection points 18 coupled with traces (not shown), the traces running through the housing 10 and terminating externally to the housing 10. In the instant case the traces manufactured within the housing comprised a gold alloy and the housing 10 was manufactured using standard technology used in the art of ceramic packaging of semiconductor die. Other materials may function adequately for the housing 10 and the traces.

The bottom shelf 12 of the housing 10 received the insert interconnect substrate 14, the insert 14 being permanently attached to the bottom shelf 14 of the housing 10. This attachment is preferably accomplished with a room temperature vulcanizing silicone rubber (RTV, not shown) or with an adhesive epoxy, although other attachment technology or materials can be used. The insert 14 comprised a nonconductive support structure 14A, in the instant case manufactured from ceramic, having electrically conductive gold interconnection circuitry 14B, although other conductive materials may be used. Precision contacts 20, manufactured in the instant case from an alloy of gold, platinum, and palladium allowed for coupling with the bond pads 22 on the semiconductor die 24 to be tested. The contacts 20 were approximately 0.001" in diameter, and extended 0.001" to 0.002" high above the insert trace circuitry 14B. The contacts 20 were all coplanar to within 10% across the contact pattern. An insert 14 thickness of approximately 0.015" was sufficient, with outside dimensions being slightly smaller than the cavity in the bottom of the housing 10. The contacts 20 mirrored the bond pads 22 on the die 24, and were spaced so as to contact the bond pads 22 on the semiconductor die 24 directly. The contacts 20 were coupled with the insert substrate electrical traces 14B, the insert traces 14B running from the contacts 20 to the edge of the insert substrate 14A. The insert traces 14B terminated near the edge of the insert substrate 14A.

In this embodiment, the interconnect insert 14 is a separate component which is bonded to the bottom shelf 12 of the housing 10. It is also possible to construct the invention with an interconnect structure incorporated into the housing 10, rather than as a separate component.

The insert traces 14B which terminated near the edge of the insert substrate 14A were wire bonded 26 to the connection points 18 within the housing 10, and were therefore electrically coupled with leads 28 attached to the traces (not shown) on the exterior of the housing 10. The leads 28 were coupled to the package using side brazing, but other coupling means may be available. The leads 28 allow for coupling of the package with a test fixture.

A package lid structure 30 was used upon which was mounted the semiconductor die 24. The back (noncircuit) side of the die 24 was attached to the lid 30 with a flat, soft sheet of a flexible adhesive polymer material 32 that performed as both an adhesive tape and a force loading material, although the use of such an adhesive material may not be necessary. A semi-cured silicone material was used, and in the instant case was silicone elastomer, from Gel Pak Corporation of Stanford, Calif. The polymer allowed for the removal of the die 24 when desired, but provided a sufficiently firm attachment to keep the die from shifting once it was attached. The adhesive properties of the polymer, therefore, were relatively strong in shear but relatively weak in tension and allowed for separation from the die with no residual adhesive material left on the back of the die. This property also allowed the polymer sheet to be removed from the lid and replaced, since the material may cure and lose its adhesive properties over time, or with elevated temperatures which may be present during the testing phase of the assembled package. Curing of the silicone material to a point that it is no longer sufficiently flexible and soft can cause problems with cushioning the semiconductor die and force loading of the insert substrate contacts.

The lid 30 was a commercially available, low cost metal item. A lid approximately 0.01" in thickness was found to be sufficient, although any reasonable lid thickness would function sufficiently, and in the embodiment, the lid was a 0.045" thick austenitic stainless steel. Other materials may function adequately.

Once the die 24 was attached to the lid 30, the lid 30 was positioned over the insert 14. The bond pads 22 on the die 24 were aligned with the insert contacts 20 on the insert 14. In the instant case, an alignment system, available from Research Devices of Piscataway, N.J., was used to vertically align the bond pads 22 on the die 24 with the contacts 20 on the insert 14. The alignment system is usually used for flip chip die attachment, but functions sufficiently in the inventive capacity. After vertical alignment, the alignment system lowered the lid assembly to contact the bond pads 22 on the die 24 with the contacts 20 on the insert 14. The "bumps" that made up the contacts 20 contacted the metal bond pads 22 of the die 24 sufficiently to ensure a good electrical contact. Sufficient contact force must be maintained to insure good electrical contact between the insert contacts 20 and the die bond pads 22. Excessive contact force, however, will cause damage to the die bond pads 22 (usually manufactured from aluminum) and underlying die circuitry. The contact force must be sufficient to push the insert substrate contacts 20 through the layer of aluminum oxide (not shown) which typically forms on the aluminum bond pads 22. Penetration of the aluminum oxide layer is necessary for good electrical contact, since aluminum oxide is a poor electrical conductor. A force of about 80 grams per contact was found to be sufficient for contacts and bond pads as described above.

After mating the bond pads 22 with the contacts 20, metal clips 34 held the lid 30 in place to prevent shifting of the lid 30, and therefore the die 24, during testing. Removably "tacking" the lid 30 to the housing 10, for example with solder or epoxy, may also be sufficient as long as the lid 30 can be removed from the housing 10 without damage to the lid 30 or housing 10.

Since the assembled package was similar to a conventional ceramic semiconductor package, a conventional test sequence, including burning in, was used to ensure functionality of the die. After the die was tested, the lid was removed from the package by removing the clips, and the die was removed from the lid. Nonfunctional die can be discarded while the known good die can be packaged or shipped directly to customers. In any case, packaging only known good die increases the yield of packaged devices. As long as the die is not damaged before packaging, any malfunctions of the packaged die results from an improperly packaged device. Poor wire bonds, cracked packages, and improper die attachments are the most likely causes of device malfunctions using such die.

It was found that the test package 10, 14, lid 30, and polymer 32 could be used to test a plurality of semiconductor die 24. The substrate contacts 20 flattened out slightly during the first use, but it was found that if the pressure between the lid assembly and the housing 10 are controlled, an adequate electrical contact would be maintained during subsequent die testing.

As shown in FIG. 3 embodiment, a lid 40, for example of a 0.045" thick austenitic stainless steel, had a hole 42 therethrough to aid in securing the die 24 in alignment with the lid 40 during a flip chip process. To attach the die 24 to the lid 40, a vacuum device (not shown) picked up the lid 40 with the vacuum device placed over the hole 42. The vacuum was sufficient to hold the lid 40. The die 24 was then aligned with the lid 40, and the vacuum also picked up the die 24 thereby holding the die 24 in aligned contact with the lid 40. The lid 40 and die 24 were then lowered onto the insert 14, thereby permitting the alignment of the bond pads with the insert contacts 20. This vacuum arrangement was found to preclude the need for the adhesive polymer which was used in the previous embodiment.

A third embodiment of the invention, described in FIG. 4, may also be used to test a discrete semiconductor die 24. In this embodiment, a housing 10 with traces within as described for a first embodiment was formed. A layer of adhesive polymer 32 was placed on the bottom shelf 12 of the housing 10, and the noncircuit side of a die 24 is attached to the housing 10 with the polymer 32.

Next, a lid 30 was formed and an insert 14 of ceramic or other workable material was permanently attached thereto with epoxy or other material (not shown). The insert 14 had traces and contacts 20 thereon as previously described for the embodiment of FIGS. 1 and 2. To electrically couple the bond pads of the die 24 to the input/output leads 28 that are attached to the traces (not shown) running through the housing 10, the contacts 20 on the insert 14 were aligned with the bond pads of the die 24. The lid 30 was lowered, and the contacts 20 on the insert 14 contacted the bond pads on the die 24, forming an electrical connection therewith. The insert 14 was larger than the insert of the first embodiment, and extended past the edge of the bond shelf 16. The ends of the traces 44 on the insert 14 were aligned with the contact points 18 on the bond shelf 16, and electrical contact was made using a sheet of Z-axis conductive polymer 46, available from A.I. Technology, of Princeton, N.J. Other coupling means are possible, and an alternative is described below. The conductive polymer 46 was interposed between the contact points 18 on the bond shelf 16 and the insert traces 44 which extended to the edge of the insert 14. As long as a minimum force was maintained between the lid 30 and the housing 10, the electrical contact between the insert traces 44 and the contact points 18 was maintained. An electrical pathway extends from the bond pads on the die 24, through the contacts 20 on the insert 14, through the traces 44 on the insert 14, through the Z-axis conductive polymer 46 to the contact points 18 on the bond shelf 16, through the traces (not shown) within the housing 10, and finally to the leads 28 attached thereto.

After assembly, the lid 30 was attached to the housing 30, for example by using clips, by solder tacking the lid 30 to the housing 10, or by other workable means. Any means used, however, must allow for the removal of the lid without damage to either the lid or the housing.

As shown in FIG. 5, a number of folded or curved metal contacts 48 were supported around an elastomer (not shown) and were attached to the contact points 18 on the housing bond shelf 16. The folded contacts 48 made electrical connection with the insert interconnect traces (not shown) when contacts 20 on the insert 14 were brought down into contact with the bond pads on the die 24.

While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention. For example, contacts can be manufactured from another material other than the gold, palladium, and platinum alloy described, and indeed other means for coupling the bond pads with the traces on the insert may be contemplated.

Claims (10)

We claim:
1. An apparatus for testing a semiconductor die, comprising:
a) a lid having a hole therein and a major surface;
b) a housing having an exterior and conductive traces, said traces forming an electrical pathway to said exterior;
c) a semiconductor die having a circuit side, a back side, and a plurality of bond pads, said die being attached to said lied with a vacuum force through said hole;
d) an interconnect having a plurality of conductive traces thereon, said interconnect being attached to said housing, wherein said traces on said interconnect electrically couple said bond pads with said traces of said housing, and said die is removed from said lid after testing.
2. The apparatus of claim 1 wherein said traces on said interconnect are electrically coupled to said traces within said housing with bond wires.
3. The apparatus of claim 1 wherein said traces on said interconnect are electrically coupled to said traces within said housing with a polymer, said polymer being interposed between said traces on said interconnect and said traces within said housing.
4. The apparatus of claim 1 wherein said traces on said interconnect are electrically coupled to said bond pads with conductive bumps interposed between said bond pads and said traces.
5. The apparatus of claim 4 wherein said bumps comprise a material selected from the group consisting of gold, palladium, and platinum.
6. A semiconductor die having a plurality of bond pads, the die tested by a test apparatus, the test apparatus comprising:
a) a lid having a hole therein and a major surface;
b) a housing having an exterior and conductive traces, said traces forming an electrical pathway to said exterior;
c) a semiconductor die having a circuit side and a back side and a plurality of bond pads, said die being attached to said lid with a vacuum force through said hole;
d) an interconnect having a plurality of conductive traces thereon, said interconnect being attached to said housing,
wherein said plurality of said traces on said interconnect electrically couple the bond pads with said traces of said housing, and the die is removed from said lid after testing.
7. A method for testing a semiconductor die, comprising the steps of:
a) forming a lid having a hole therein and a major surface;
b) forming a housing having an exterior and conductive traces, said traces forming an electrical pathway to said exterior;
c) forming a semiconductor die having a plurality of bond pads;
d) removably attaching said die to said lid with a vacuum force through said hole;
e) forming an interconnect having a plurality of conductive traces thereon;
f) attaching said interconnect to said housing such that said traces on said interconnect electrically couple said bond pads with said traces of said housing;
g) electrically analyzing the die for adherence to predetermined specifications;
h) separating said lid from said housing; and
i) removing said die from said lid.
8. The method of claim 7 wherein said traces on said interconnect are coupled with said traces within said housing during a wire bonding step.
9. The method of claim 7 further comprising the step of interposing a polymer between said traces within said housing and said traces on said interconnect thereby coupling said interconnect traces and said housing traces.
10. The method of claim 7 further comprising the step of forming conductive bumps and interposing said conductive bumps between said bond pads and said traces, thereby electrically coupling said bond pads and said traces.
US07/896,297 1992-06-10 1992-06-10 Method and apparatus for testing an unpackaged semiconductor die Expired - Lifetime US5424652A (en)

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US07/896,297 US5424652A (en) 1992-06-10 1992-06-10 Method and apparatus for testing an unpackaged semiconductor die
US08/192,391 US5483174A (en) 1992-06-10 1994-02-03 Temporary connection of semiconductor die using optical alignment techniques
US08/550,340 US5825195A (en) 1992-06-10 1995-10-30 Method and apparatus for testing an unpackaged semiconductor die

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