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US5424570A - Contact structure for improving photoresist adhesion on a dielectric layer - Google Patents

Contact structure for improving photoresist adhesion on a dielectric layer Download PDF

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Publication number
US5424570A
US5424570A US07828608 US82860892A US5424570A US 5424570 A US5424570 A US 5424570A US 07828608 US07828608 US 07828608 US 82860892 A US82860892 A US 82860892A US 5424570 A US5424570 A US 5424570A
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Prior art keywords
layer
dielectric
oxide
photoresist
formed
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Expired - Lifetime
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US07828608
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John C. Sardella
Alexander Kalnitsky
Charels R. Spinner, III
Robert C. Foulks, Sr.
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STMicroelectronics lnc
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STMicroelectronics lnc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90MOSFET type gate sidewall insulating spacer

Abstract

A structure is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Description

FIELD OF THE INVENTION

The present invention relates generally to semiconductor integrated circuit processing, and more specifically to improving photoresist adhesion on a dielectric layer.

BACKGROUND OF THE INVENTION

Insulators or dielectrics have widespread use in semiconductor processing. Silicon dioxide films are best known for their use as passivation to provide physical and chemical protection to the underlying devices and components. Silicon nitride films have also been widely used as a passivation layer providing additional scratch protection due in part to its hardness. The role of silicon dioxide films in processing has expanded. Deposited silicon dioxide films are now used as interlevel dielectrics between polysilicon and metal lines, as isolation films, as dopant barriers and as diffusion sources.

Deposited silicon dioxide films have a different physical structure from thermally grown oxide films. Depending on the deposition temperature, the silicon dioxide may have, among others, a different density, dielectric strength and etch rate. The addition of dopants to deposited silicon dioxide films may change the chemical and physical properties of the films. Deposited silicon dioxide films may also undergo a process called densification. The deposition of films was started to allow for a low-temperature deposition to occur preventing undesirable redistribution of impurities in the underlying regions during the processing steps. The densification of the silicon dioxide after deposition forms a film with physical and chemical properties approximating that of thermally grown oxide films.

There are several benefits of adding dopants to the silicon dioxide films. The moisture barrier properties of the films increase. Contaminants are prevented from entering the underlying layers and the viscosity of the films increase. This last benefit of increasing the flow property enhances the planarization of the surface of the film. Typically, boron and phosphorous are added to the silicon dioxide to enhance the flow property. The resultant film is known as borophosphorous silicate glass (BPSG).

As the concentration of dopants increases in the glass film, the temperature at which the film will reflow decreases. The lower processing temperature to cause reflow will not effect the electrical performance of the devices and components. As additional dopants are added, however, the surface of the glass layer becomes dopant rich. This increased concentration at the surface causes adhesion problems during subsequent contact patterning processes. In other words, the ability of photoresist to adequately adhere to the doped glass layer is significantly reduced. After the photoresist is formed over the glass layer and patterned, the opening formed in the photoresist is cleaned to remove any remaining photoresist residue in the areas where a contact is to be etched. This process, called descuming, enhances the photoresist's ability to adhere to the underlying glass layer. However, during the process of cleaning, a portion of the sidewalls of the photoresist is also removed. The removal of any of the photoresist along the sidewalls is becoming unacceptable in the submicron geometries.

It would be desirable to provide a technique which increases the adhesion of photoresist to the underlying dielectric layer. It would further be desirable for such a technique to be easily adapted for use with standard integrated circuit fabrication process flows without increasing the complexity of the process.

SUMMARY OF THE INVENTION

The invention may be incorporated into a method for forming a semiconductor device structure, and the semiconductor device structure formed thereby, by forming a first dielectric layer over the integrated circuit wherein the dielectric layer has a dopant concentration at an upper surface sufficient enough to allow the layer to be reflowed while partially inhibiting adhesion of the layer to photoresist at the upper surface. A second undoped dielectric layer is formed over the first dielectric layer. An opening is formed in the first and second dielectric layers exposing a portion of an underlying conductive structure wherein a portion of the dielectric layers has outwardly sloping sidewalls at the opening.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:

FIGS. 1-3 are cross-sectional views of the fabrication of a semiconductor device structure according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.

Referring to FIG. 1, an integrated circuit device is to be formed on a silicon substrate 10. A field oxide region 12 is formed on the substrate to separate active areas. A conductive structure such as a transistor gate is formed on the substrate by known methods comprising gate electrode 14 disposed over a gate oxide 16. The transistor will also comprise oxide spacers 18 and source/drain regions 20. Another conductive structure 22, such as a polysilicon signal line, may be formed over the field oxide region 12.

A first conformal dielectric layer 24 is formed over the integrated circuit. Layer 24 may typically comprise an undoped oxide or a silicon nitride having a thickness between approximately 100 to 2000 angstroms. A second dielectric layer 26 is formed over the first dielectric layer. Layer 26 is typically a conformal BPSG layer having a thickness of between approximately 3000 to 8000 angstroms. The BPSG layer may be formed by chemical vapor deposition.

The BPSG layer 26 is then reflowed to form a more planar surface. The BPSG layer will typically have a dopant concentration of 2-4 percent boron and 4-7 percent phosphorous. At this concentration, the BPSG layer will flow at a reasonably low temperature between approximately 850° to 900° C. However, at this concentration, the upper surface of the BPSG layer 26 will become dopant rich. Any photoresist applied to the BPSG layer at this stage would not adequately adhere to the BPSG. Therefore, a third conformal dielectric layer 28 is formed over the BPSG layer. Layer 28 is typically an oxide layer having a thickness of between approximately 50 to 300 angstroms. The etch rate of this oxide layer should be closely matched to that of the BPSG layer 26. A photoresist layer 30 is then spun onto the oxide layer 28 and patterned to form an opening 32 where a contact opening will be subsequently etched through the dielectric layers. The oxide layer 28 is undoped allowing the photoresist layer 30 to adequately adhere to the oxide.

Referring to FIG. 2, the dielectric layers 24, 26 and 28 are etched in opening 32 to expose an underlying conductive structure such as the source/drain region 20 as shown in FIG. 2. The etch process is generally a wet etch followed by a dry etch. The wet etch is an isotropic etch which forms sloped sidewalls 34. The dry etch is an anisotropic etch which forms the vertical sidewalls 36. The undoped oxide layer 28 provides for adequate adhesion of the photoresist layer 30 to the oxide layer 28. This adhesion prevents unwanted undercutting of the upper portion of the dielectric layer 28 during the wet etch step. The contact opening thus remains relatively constant. Moreover, the undoped oxide layer 28 has substantially the same etch rate as the BPSG layer 26.

Referring to FIG. 3, the photoresist layer 30 is removed. the undoped oxide layer 28 does not have to be removed. Thus, at this stage, the complexity of the process is not increased. An alternative to the above process is to carry out the steps as described above up until the reflow of the BPSG layer 26. At this point, the BPSG layer is densified by a high temperature anneal process. The third dielectric layer 28 is then formed over the BPSG layer 26. The photoresist layer 30 is formed and patterned and the contact opening 32 is etched to expose the underlying conductive structure as described above. The reflow step is then performed to planarize the dielectric layers.

The thin undoped oxide layer 28 provides a medium for the photoresist layer to adhere to the interlevel dielectric to insure a higher quality contact opening. The oxide layer 28 does not need to be removed allowing this technique to be used with standard integrated circuit process flows.

As will be appreciated by those skilled in the art, the process steps described above can be used with nearly any conventional process flow. While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (1)

What is claimed is:
1. A contact structure for a semiconductor integrated circuit, comprising:
a substrate having a transistor source/drain region therein;
a transistor gate disposed over a portion of the substrate adjacent the source/drain region;
a conformal deposited oxide layer disposed over and in contact with the substrate and gate;
a BPSG layer disposed over and in contact with the deposited oxide layer and having a planarized upper surface, wherein a higher dopant concentration at the upper surface is sufficient to prevent adhesion thereto by a photoresist;
an undoped oxide layer disposed over and in contact with the BPSG layer and having a thickness of between approximately 50 and 300 angstroms; and
an opening through the oxide and BPSG layers to expose the source/drain region, wherein the opening has outwardly sloping sidewalls in the undoped oxide layer and a first portion of the BPSG layer, and substantially vertical sidewalls in the deposited oxide layer and a second portion of the BPSG layer.
US07828608 1992-01-31 1992-01-31 Contact structure for improving photoresist adhesion on a dielectric layer Expired - Lifetime US5424570A (en)

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US07828608 US5424570A (en) 1992-01-31 1992-01-31 Contact structure for improving photoresist adhesion on a dielectric layer
US08905918 US5877541A (en) 1992-01-31 1997-08-04 Contact structure for improving photoresist adhesion on a dielectric layer
US09152729 US6010959A (en) 1992-01-31 1998-09-14 Method of improving photoresist adhesion on a dielectric layer

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Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5733797A (en) * 1992-12-16 1998-03-31 Yamaha Corporation Method of making a semiconductor device with moisture impervious film
US5793110A (en) * 1995-02-17 1998-08-11 Yamaha Corporation MOS transistor with good hot carrier resistance and low interface state density
US5807660A (en) * 1997-02-03 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Avoid photoresist lifting by post-oxide-dep plasma treatment
US5837603A (en) * 1996-05-08 1998-11-17 Harris Corporation Planarization method by use of particle dispersion and subsequent thermal flow
US5869388A (en) * 1994-12-15 1999-02-09 Stmicroelectronics, Inc. Method of gettering using doped SOG and a planarization technique
US5877541A (en) * 1992-01-31 1999-03-02 Stmicroelectronics, Inc. Contact structure for improving photoresist adhesion on a dielectric layer
US5973385A (en) * 1996-10-24 1999-10-26 International Business Machines Corporation Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby
US5990541A (en) * 1994-06-06 1999-11-23 Sharp Kabushiki Kaisha Semiconductor device and method of fabricating the same
US6037630A (en) * 1997-05-26 2000-03-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with gate electrode portion and method of manufacturing the same
US6091121A (en) * 1997-11-12 2000-07-18 Nec Corporation Semiconductor device and method for manufacturing the same
US6117791A (en) * 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6169026B1 (en) 1995-11-20 2001-01-02 Hyundai Electronics Industries Co., Ltd. Method for planarization of semiconductor device including pumping out dopants from planarization layer separately from flowing said layer
US6340829B1 (en) * 1998-05-06 2002-01-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US6541809B1 (en) * 1998-11-25 2003-04-01 Micron Technology, Inc. Method of making straight wall containers and the resultant containers
US20030129803A1 (en) * 2000-08-30 2003-07-10 Honeycutt Jeffrey W. Transistor Structures
US6875371B1 (en) 1998-06-22 2005-04-05 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US20050142729A1 (en) * 2003-12-30 2005-06-30 Hyunsoo Shin Methods for forming a field effect transistor
US20060148269A1 (en) * 2004-02-27 2006-07-06 Micron Technology, Inc. Semiconductor devices and methods for depositing a dielectric film
US7173339B1 (en) 1998-06-22 2007-02-06 Micron Technology, Inc. Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure
US7208426B2 (en) * 2001-11-13 2007-04-24 Chartered Semiconductors Manufacturing Limited Preventing plasma induced damage resulting from high density plasma deposition
US20080156346A1 (en) * 2006-12-28 2008-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for cleaning a substrate

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JPH10270555A (en) * 1997-03-27 1998-10-09 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

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US3945030A (en) * 1973-01-15 1976-03-16 Signetics Corporation Semiconductor structure having contact openings with sloped side walls
JPS55134975A (en) * 1979-04-09 1980-10-21 Nec Kyushu Ltd Semiconductor device
GB2118777A (en) * 1982-04-23 1983-11-02 Western Electric Co Insulation layer between metallization in a semiconductor integrated circuit structure
JPS6088435A (en) * 1983-10-21 1985-05-18 Toshiba Corp Semiconductor device
US4753709A (en) * 1987-02-05 1988-06-28 Texas Instuments Incorporated Method for etching contact vias in a semiconductor device
JPS63258080A (en) * 1987-04-15 1988-10-25 Hitachi Cable Ltd Light-emitting diode array
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Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877541A (en) * 1992-01-31 1999-03-02 Stmicroelectronics, Inc. Contact structure for improving photoresist adhesion on a dielectric layer
US5733797A (en) * 1992-12-16 1998-03-31 Yamaha Corporation Method of making a semiconductor device with moisture impervious film
US5990541A (en) * 1994-06-06 1999-11-23 Sharp Kabushiki Kaisha Semiconductor device and method of fabricating the same
US5869388A (en) * 1994-12-15 1999-02-09 Stmicroelectronics, Inc. Method of gettering using doped SOG and a planarization technique
US5793110A (en) * 1995-02-17 1998-08-11 Yamaha Corporation MOS transistor with good hot carrier resistance and low interface state density
US6169026B1 (en) 1995-11-20 2001-01-02 Hyundai Electronics Industries Co., Ltd. Method for planarization of semiconductor device including pumping out dopants from planarization layer separately from flowing said layer
US5837603A (en) * 1996-05-08 1998-11-17 Harris Corporation Planarization method by use of particle dispersion and subsequent thermal flow
US5973385A (en) * 1996-10-24 1999-10-26 International Business Machines Corporation Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby
US5807660A (en) * 1997-02-03 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Avoid photoresist lifting by post-oxide-dep plasma treatment
US6037630A (en) * 1997-05-26 2000-03-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with gate electrode portion and method of manufacturing the same
US6503826B1 (en) 1997-11-12 2003-01-07 Nec Corporation Semiconductor device and method for manufacturing the same
US6091121A (en) * 1997-11-12 2000-07-18 Nec Corporation Semiconductor device and method for manufacturing the same
US6699758B2 (en) * 1998-05-06 2004-03-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US6340829B1 (en) * 1998-05-06 2002-01-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US6117791A (en) * 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6121671A (en) * 1998-06-22 2000-09-19 Micron Technology, Inc. Semiconductor device having a substrate, an undoped silicon oxide structure, and an overlying doped silicon oxide structure with a side wall terminating at the undoped silicon oxide structure
US7319075B2 (en) 1998-06-22 2008-01-15 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US7173339B1 (en) 1998-06-22 2007-02-06 Micron Technology, Inc. Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure
US20030203639A1 (en) * 1998-06-22 2003-10-30 Kei-Yu Ko Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6875371B1 (en) 1998-06-22 2005-04-05 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6537922B1 (en) 1998-06-22 2003-03-25 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6541809B1 (en) * 1998-11-25 2003-04-01 Micron Technology, Inc. Method of making straight wall containers and the resultant containers
US6709937B2 (en) 2000-08-30 2004-03-23 Micron Technology, Inc. Transistor structures
US20030129803A1 (en) * 2000-08-30 2003-07-10 Honeycutt Jeffrey W. Transistor Structures
US6734071B1 (en) * 2000-08-30 2004-05-11 Micron Technology, Inc. Methods of forming insulative material against conductive structures
US7208426B2 (en) * 2001-11-13 2007-04-24 Chartered Semiconductors Manufacturing Limited Preventing plasma induced damage resulting from high density plasma deposition
US20050142729A1 (en) * 2003-12-30 2005-06-30 Hyunsoo Shin Methods for forming a field effect transistor
US7402484B2 (en) * 2003-12-30 2008-07-22 Dongbu Electronics Co., Ltd. Methods for forming a field effect transistor
US20060148269A1 (en) * 2004-02-27 2006-07-06 Micron Technology, Inc. Semiconductor devices and methods for depositing a dielectric film
US20080156346A1 (en) * 2006-12-28 2008-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for cleaning a substrate

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US6010959A (en) 2000-01-04 grant

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