US5422512A - Semiconductor device and reticle used for fabricating the same - Google Patents

Semiconductor device and reticle used for fabricating the same Download PDF

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Publication number
US5422512A
US5422512A US07/904,953 US90495392A US5422512A US 5422512 A US5422512 A US 5422512A US 90495392 A US90495392 A US 90495392A US 5422512 A US5422512 A US 5422512A
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Prior art keywords
formation region
device formation
semiconductor device
reticle
light
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Expired - Lifetime
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US07/904,953
Inventor
Koji Yamanaka
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Renesas Electronics Corp
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NEC Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Definitions

  • This invention relates to a semiconductor device, and more particularly to, a shape of a device formation region and a reticle used for fabricating the same.
  • a conventional semiconductor device is positioned on a device formation region of a semiconductor substrate, and is separated by a device separation region thereof.
  • the device formation region is formed by photoetching using a reticle as an etching mask.
  • a conventional reticle is composed of a light transmission layer and a light shield region formed to be a rectangle on the light transmission layer.
  • a first resist pattern is formed on a silicon substrate by photoetching using the reticle as an etching mask. At this time, the first resist pattern is formed to be along a 27% uniform intensity line of light passing through the light transmission layer. Thus, the first resist pattern has two curved portions each having the same radius.
  • a field oxide layer is formed on the silicon substrate as an insulation layer for a device separation region, and a device formation region is formed by etching using the first resist pattern as an etching mask.
  • the device formation region is shaped to be like a concave mirror being encircled with an inner edge of the field oxide layer.
  • a polysilicon layer is formed on the whole process surface of the substrate, and a resist layer is formed on a surface of the polysilicon. After that, the resist layer is etched, so that a second resist pattern for gate electrodes is formed thereon.
  • the polysilicon layer is etched with using the second resist pattern as an etching mask, so that the gate electrodes are formed on the device formation region.
  • the conventional semiconductor device there is a disadvantage in that, when the device formation region is formed, radiation light is converged to an inside of the device formation region by light reflection on the inner edge of the field oxide layer, because the device formation region is shaped to be like a concave mirror. Then, the reflected light is radiated to a side surface of the second resist pattern, so that the side surface which is an inaccurate portion is also etched. Therefore, depressions are formed at the second resist pattern, so that the gate electrodes are provided with depressions corresponding to the depressions of the second resist pattern. As a result, a reliability of the semiconductor device is lowered.
  • semiconductor device including:
  • the device formation region is shaped to have at least two curved portions having different radiuses so that photolithography light is not converged to a point of an inside of the device formation region by light reflection on an inner edge of the insulation layer, when the device pattern is formed.
  • a reticle used for fabricating a semiconductor device including:
  • a light shield region formed at a part of the light transmission area, which is used as an etching mask when a device formation region is formed on a semiconductor substrate by photoetching;
  • the light shield region is shaped to be a predetermined shape so that a uniform intensity line of light passing through the light transmission area has at least two curved portions having different radiuses.
  • FIGS. 1A to 1F are cross-sectional views showing a fabricating process of a conventional semiconductor device
  • FIG. 2 is a plane view showing a conventional reticle used for fabricating the conventional semiconductor device
  • FIG. 3 is a plane view showing the conventional semiconductor device
  • FIGS. 4A and 4B are cross-sectional views showing a fabricating process of a semiconductor device of a first preferred embodiment according to the invention.
  • FIG. 5 is a plane view showing a reticle used for the first preferred embodiment
  • FIG. 6 is a plane view showing the semiconductor device of the first preferred embodiment.
  • FIG. 7 is a plane view showing a reticle used for a second preferred embodiment according to the invention.
  • FIGS. 1A to 1F, 2 and 3 Before describing a semiconductor device according to the invention, the aforementioned conventional semiconductor device will be explained in conjunction with FIGS. 1A to 1F, 2 and 3.
  • the conventional semiconductor device is fabricated by the following process shown in FIGS. 1A to 1F.
  • a resist pattern 10 is formed on a silicon substrate 12 as shown in FIG. 1A by photoetching with using a reticle 14 as an etching mask.
  • the reticle 14 which is shown in FIG. 2 is provided with a light shield region 16 of chrome which is shaped to be rectangle on a light transmission area 18.
  • the resist pattern 10 is shaped along a 27% uniform intensity line 20 of light passing through the light transmission area 18, and has two curved portions each having a radius "R" at both sides.
  • the 27% uniform intensity line 20 becomes a border line of the patterning in a high resolution positive photoresist.
  • a field oxide layer 22 is formed on the silicon substrate 12, and a device formation region 24 is formed thereon by a selective (preferential) oxidation method with using the resist pattern 10 as a mask as shown in FIG. 1B.
  • the device formation region 24 is shaped to be like a concave mirror being encircled with an inner edge of the field oxide layer 22.
  • a polysilicon layer 26 is formed on the whole process surface of the substrate as shown in FIG. 1C, and a resist layer 28 is formed on a surface of the polysilicon layer 26 as shown in FIG. 1D.
  • a resist pattern 30 for gate electrodes 32 and 34 is formed by photoetching as shown in FIG. 1E.
  • radiation light is converged to an inside of the device formation region 24 by light reflection on the inner edge of the field oxide layer 22, so that the reflected light is radiated to a side surface of the resist pattern 30. Therefore, the resist pattern 30 is etched at the side surface, so that depressions 36 and 38 are formed thereat.
  • the polysilicon layer 26 is etched with using the resist pattern 30 as an etching mask, so that the gate electrodes 32 and 34 are formed on the device formation region 24 as shown in FIG. 1F.
  • the gate electrodes 32 and 34 are provided with depressions 40 and 42 as shown in FIGS. 1F and 3.
  • a reticle 52 as shown in FIG. 5, which is provided with a light shield region 53 of chrome in a part of a light transmission area 18 is used.
  • the light shield region 53 is shaped to have two triangular notches 51a and 51b so that a uniform intensity line 55 has two curved portions having different radiuses "R 1 " and "R 2 ".
  • a resist pattern 54 for gate electrodes 56 and 58 are formed to have no depression as shown in FIG. 4A and 6, because a device formation region 50 which is encircled with a field oxide layer 59 is shaped to have two curved portions having different radiuses corresponding to the reticle 52. Therefore, the gate electrodes 56 and 58 are shaped to have no depression as shown in FIG. 4B and FIG. 6.
  • FIG. 7 shows a reticle 60 of a second preferred embodiment according to the invention.
  • the reticle 60 is provided with a light shield region 62 of chrome in a part of a light transmission area 18.
  • the light shield region 62 is shaped to have two rectangular notches 63a and 63b so that a uniform intensity line 64 has two curved portions having different radiuses "R 3 " and "R 4 " as shown in the figure.
  • the same advantage as in the first preferred embodiment can be obtained.
  • the reticles 52 and 62 are provided with the two notches 51a and 52a, and 63a and 63b, however, the reticle may be provided with more than three notches.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

A semiconductor device is provided with a device formation region formed by etching with using a reticle as an etching mask. The device formation region is shaped to have at least two curved portions having different radiuses, being encircled with an insulation layer, so that radiated light is not converged to a point of an inside of the device formation region by light reflection on an inner edge of the insulation layer.

Description

FIELD OF THE INVENTION
This invention relates to a semiconductor device, and more particularly to, a shape of a device formation region and a reticle used for fabricating the same.
BACKGROUND OF THE INVENTION
A conventional semiconductor device is positioned on a device formation region of a semiconductor substrate, and is separated by a device separation region thereof. There are two methods for fabricating a device formation region, that is, one is a selective (preferential) oxidation method and the other is a trench separation method.
According to the selective oxidation method, the device formation region is formed by photoetching using a reticle as an etching mask. A conventional reticle is composed of a light transmission layer and a light shield region formed to be a rectangle on the light transmission layer.
In fabrication of a conventional semiconductor device, a first resist pattern is formed on a silicon substrate by photoetching using the reticle as an etching mask. At this time, the first resist pattern is formed to be along a 27% uniform intensity line of light passing through the light transmission layer. Thus, the first resist pattern has two curved portions each having the same radius.
Next, a field oxide layer is formed on the silicon substrate as an insulation layer for a device separation region, and a device formation region is formed by etching using the first resist pattern as an etching mask. At this time, the device formation region is shaped to be like a concave mirror being encircled with an inner edge of the field oxide layer.
Next, a polysilicon layer is formed on the whole process surface of the substrate, and a resist layer is formed on a surface of the polysilicon. After that, the resist layer is etched, so that a second resist pattern for gate electrodes is formed thereon.
Finally, the polysilicon layer is etched with using the second resist pattern as an etching mask, so that the gate electrodes are formed on the device formation region.
According to the conventional semiconductor device, however, there is a disadvantage in that, when the device formation region is formed, radiation light is converged to an inside of the device formation region by light reflection on the inner edge of the field oxide layer, because the device formation region is shaped to be like a concave mirror. Then, the reflected light is radiated to a side surface of the second resist pattern, so that the side surface which is an inaccurate portion is also etched. Therefore, depressions are formed at the second resist pattern, so that the gate electrodes are provided with depressions corresponding to the depressions of the second resist pattern. As a result, a reliability of the semiconductor device is lowered.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a semiconductor device in which a pattern having a precise shape can be formed on a device formation region.
It is a further object of the invention to provide a reticle for fabricating a device formation region by which a pattern having a precise shape can be formed.
According to a first feature of the invention, semiconductor device, including:
a semiconductor substrate;
an insulation layer formed on the semiconductor substrate for separating a device formation region from another region; and
a device pattern formed on the device formation region by photoetching;
wherein the device formation region is shaped to have at least two curved portions having different radiuses so that photolithography light is not converged to a point of an inside of the device formation region by light reflection on an inner edge of the insulation layer, when the device pattern is formed.
According to a second feature of the invention, a reticle used for fabricating a semiconductor device, including:
a light transmission area through which light is transmitted; and
a light shield region formed at a part of the light transmission area, which is used as an etching mask when a device formation region is formed on a semiconductor substrate by photoetching;
wherein the light shield region is shaped to be a predetermined shape so that a uniform intensity line of light passing through the light transmission area has at least two curved portions having different radiuses.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be explained in more detail in conjunction with appended drawings; wherein:
FIGS. 1A to 1F are cross-sectional views showing a fabricating process of a conventional semiconductor device;
FIG. 2 is a plane view showing a conventional reticle used for fabricating the conventional semiconductor device;
FIG. 3 is a plane view showing the conventional semiconductor device;
FIGS. 4A and 4B are cross-sectional views showing a fabricating process of a semiconductor device of a first preferred embodiment according to the invention;
FIG. 5 is a plane view showing a reticle used for the first preferred embodiment;
FIG. 6 is a plane view showing the semiconductor device of the first preferred embodiment; and
FIG. 7 is a plane view showing a reticle used for a second preferred embodiment according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Before describing a semiconductor device according to the invention, the aforementioned conventional semiconductor device will be explained in conjunction with FIGS. 1A to 1F, 2 and 3.
The conventional semiconductor device is fabricated by the following process shown in FIGS. 1A to 1F. First, a resist pattern 10 is formed on a silicon substrate 12 as shown in FIG. 1A by photoetching with using a reticle 14 as an etching mask. The reticle 14 which is shown in FIG. 2 is provided with a light shield region 16 of chrome which is shaped to be rectangle on a light transmission area 18. The resist pattern 10 is shaped along a 27% uniform intensity line 20 of light passing through the light transmission area 18, and has two curved portions each having a radius "R" at both sides. The 27% uniform intensity line 20 becomes a border line of the patterning in a high resolution positive photoresist.
Next, a field oxide layer 22 is formed on the silicon substrate 12, and a device formation region 24 is formed thereon by a selective (preferential) oxidation method with using the resist pattern 10 as a mask as shown in FIG. 1B. At this time, the device formation region 24 is shaped to be like a concave mirror being encircled with an inner edge of the field oxide layer 22. Then, a polysilicon layer 26 is formed on the whole process surface of the substrate as shown in FIG. 1C, and a resist layer 28 is formed on a surface of the polysilicon layer 26 as shown in FIG. 1D.
After that, a resist pattern 30 for gate electrodes 32 and 34 is formed by photoetching as shown in FIG. 1E. In this process, radiation light is converged to an inside of the device formation region 24 by light reflection on the inner edge of the field oxide layer 22, so that the reflected light is radiated to a side surface of the resist pattern 30. Therefore, the resist pattern 30 is etched at the side surface, so that depressions 36 and 38 are formed thereat.
Finally, the polysilicon layer 26 is etched with using the resist pattern 30 as an etching mask, so that the gate electrodes 32 and 34 are formed on the device formation region 24 as shown in FIG. 1F. In this process, the gate electrodes 32 and 34 are provided with depressions 40 and 42 as shown in FIGS. 1F and 3.
According to the conventional semiconductor device, however, there is a disadvantage in that a reliability thereof is lowered, because the gate electrodes 32 and 34 are provided with the depressions 40 and 42.
Next, a semiconductor device of a first preferred embodiment will be explained in conjunction with FIGS. 4A, 4B, 5 and 6.
In the first preferred embodiment, a reticle 52, as shown in FIG. 5, which is provided with a light shield region 53 of chrome in a part of a light transmission area 18 is used. The light shield region 53 is shaped to have two triangular notches 51a and 51b so that a uniform intensity line 55 has two curved portions having different radiuses "R1 " and "R2 ".
According to the first preferred embodiment, a resist pattern 54 for gate electrodes 56 and 58 are formed to have no depression as shown in FIG. 4A and 6, because a device formation region 50 which is encircled with a field oxide layer 59 is shaped to have two curved portions having different radiuses corresponding to the reticle 52. Therefore, the gate electrodes 56 and 58 are shaped to have no depression as shown in FIG. 4B and FIG. 6.
FIG. 7 shows a reticle 60 of a second preferred embodiment according to the invention. The reticle 60 is provided with a light shield region 62 of chrome in a part of a light transmission area 18. The light shield region 62 is shaped to have two rectangular notches 63a and 63b so that a uniform intensity line 64 has two curved portions having different radiuses "R3 " and "R4 " as shown in the figure. According to the second preferred embodiment, the same advantage as in the first preferred embodiment can be obtained.
According to the first and second preferred embodiments, the reticles 52 and 62 are provided with the two notches 51a and 52a, and 63a and 63b, however, the reticle may be provided with more than three notches.
Although the invention has been described with respect to specific embodiment for complete and a reticle used for clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modification and a reticle used for alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

Claims (1)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor substrate;
a device formation region having a flat top surface;
an insulation layer on said semiconductor substrate for separating said device formation region from another region; and
a device pattern on said top surface of said device formation region,
said top surface of said device formation region being lower than a top surface of said insulation layer, said device formation region being shaped to have at least two curved portions having different radiuses so that photolithography light is not converged to a point where said device pattern is to be located, inside of said device formation region, by light reflection on an inner edge of said insulation layer.
US07/904,953 1991-06-26 1992-06-26 Semiconductor device and reticle used for fabricating the same Expired - Lifetime US5422512A (en)

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JP3-153658 1991-06-26
JP3153658A JP2979731B2 (en) 1991-06-26 1991-06-26 Semiconductor device

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US5422512A true US5422512A (en) 1995-06-06

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EP (1) EP0520817B1 (en)
JP (1) JP2979731B2 (en)
KR (1) KR970009611B1 (en)
DE (1) DE69219818T2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731109A (en) * 1995-06-15 1998-03-24 Hyundai Electronics Industries Co., Ltd. Pattern structure of photomask comprising a sawtooth pattern

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3883948A (en) * 1974-01-02 1975-05-20 Signetics Corp Semiconductor structure and method
US4012764A (en) * 1974-12-04 1977-03-15 Hitachi, Ltd. Semiconductor integrated circuit device
US4763178A (en) * 1982-07-28 1988-08-09 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US5021359A (en) * 1988-06-21 1991-06-04 Harris Corporation Radiation hardened complementary transistor integrated circuits
US5094973A (en) * 1987-11-23 1992-03-10 Texas Instrument Incorporated Trench pillar for wafer processing
US5101261A (en) * 1988-09-09 1992-03-31 Texas Instruments Incorporated Electronic circuit device with electronomigration-resistant metal conductors

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2117175A (en) * 1982-03-17 1983-10-05 Philips Electronic Associated Semiconductor device and method of manufacture
JPH03296247A (en) * 1990-04-13 1991-12-26 Mitsubishi Electric Corp Semiconductor device and its manufacture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3883948A (en) * 1974-01-02 1975-05-20 Signetics Corp Semiconductor structure and method
US4012764A (en) * 1974-12-04 1977-03-15 Hitachi, Ltd. Semiconductor integrated circuit device
US4763178A (en) * 1982-07-28 1988-08-09 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US5094973A (en) * 1987-11-23 1992-03-10 Texas Instrument Incorporated Trench pillar for wafer processing
US5021359A (en) * 1988-06-21 1991-06-04 Harris Corporation Radiation hardened complementary transistor integrated circuits
US5101261A (en) * 1988-09-09 1992-03-31 Texas Instruments Incorporated Electronic circuit device with electronomigration-resistant metal conductors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731109A (en) * 1995-06-15 1998-03-24 Hyundai Electronics Industries Co., Ltd. Pattern structure of photomask comprising a sawtooth pattern
CN1096625C (en) * 1995-06-15 2002-12-18 现代电子产业株式会社 Pattern structure of photomask

Also Published As

Publication number Publication date
JP2979731B2 (en) 1999-11-15
DE69219818T2 (en) 1997-09-04
EP0520817A3 (en) 1993-10-13
KR930001315A (en) 1993-01-16
JPH053247A (en) 1993-01-08
EP0520817A2 (en) 1992-12-30
KR970009611B1 (en) 1997-06-14
DE69219818D1 (en) 1997-06-26
EP0520817B1 (en) 1997-05-21

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