US5377072A - Single metal-plate bypass capacitor - Google Patents
Single metal-plate bypass capacitor Download PDFInfo
- Publication number
- US5377072A US5377072A US08/179,275 US17927594A US5377072A US 5377072 A US5377072 A US 5377072A US 17927594 A US17927594 A US 17927594A US 5377072 A US5377072 A US 5377072A
- Authority
- US
- United States
- Prior art keywords
- capacitor
- metal
- plate
- silicon
- bypass capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Definitions
- This invention relates, in general, to bypass capacitors used in packaged semiconductor devices, and more particularly, to close-attached-capacitors electrically coupled to high-speed semiconductor devices.
- High-speed semiconductor devices are complex and contain thousands or even millions of circuit elements, such as transistors, logic circuits, and the like.
- circuit elements such as transistors, logic circuits, and the like.
- the power supply providing power and ground signals to the circuits is momentarily stressed by the sudden increase in electrical current.
- the momentary degradation in supply voltage caused by the rapid switching of a large number of circuits, can cause performance degradation in the semiconductor device.
- the increased line noise created by a power supply fluctuation can cause a loss in signal transmission speed, rise time degradation, and false switching of logic gates.
- bypass capacitors are incorporated into the package housing of the semiconductor device; or alternatively, the bypass capacitors are located completely external to the device package and are mounted on a printed circuit board.
- bypass capacitors mounted in either the device package or on the circuit board are effective in reducing performance degradation of semiconductor devices operating at low frequency, the self-inductance and line inductance incurred by using remotely located bypass capacitors is too great for high-performance devices operating at high frequencies.
- the line inductance and the capacitor self-inductance limits the use of external capacitors for high speed devices.
- bypass capacitors are mounted directly to the upper surface of the semiconductor device.
- a close-attached-capacitor (CAC) can be used to reduce the length of interconnections and hence the line inductance to the capacitor. This technique is described in U.S. Pat. No. 5,049,979 to S. H. Hashemi, et al., issued Sep. 17, 1991.
- CAC close-attached-capacitor
- CAC improves the operation of a high-performance semiconductor device by reducing line inductance
- the CAC itself continues to have a large amount of internal inductance.
- the high internal inductance of the CAC is similar to that of bypass capacitors mounted in the device package, and on a printed circuit board. These capacitors have a large surface area, yet are internally constructed in such a way as to generate high internal inductance. Accordingly, further development of CAC type bypass capacitors is necessary to meet the performance requirements of high-speed semiconductor devices.
- a single metal-plate bypass capacitor for mounting to the surface of a semiconductor device, which includes a single metal capacitor plate.
- the single metal plate overlies a silicon substrate and is separated from the substrate by a thin, highly-pure silicon dioxide layer.
- the silicon substrate serves as the second capacitor plate.
- a gate dielectric layer overlies a silicon substrate.
- a metal capacitor plate overlies the gate dielectric layer, and a metal contact pad overlies the silicon substrate.
- the metal contact pad is in intimate contact with a portion of the silicon substrate at the periphery of the metal capacitor plate.
- the metal contact pad surrounds the metal capacitor plate and is electrically isolated from the plate by an electrical isolation structure.
- the metal contact pad electrically couples a plurality of bonding wires to the silicon substrate.
- FIG. 1 illustrates, in cross-section, a bypass capacitor of the invention mounted to the surface of a semiconductor device, which is in turn mounted to the bonding area of a device package;
- FIG. 2 illustrates, in plan view, the upper surface of the bypass capacitor of the invention showing in detail the metal plate assembly of the bypass capacitor;
- FIG. 3 illustrates, in cross-section, a portion of the bypass capacitor of the invention taken along section line 3--3 of FIG. 2;
- FIG. 4 illustrates, in cross-section, a bypass capacitor in accordance with another embodiment of the invention having a silicon reference plane intermediate to the metal top plate and the silicon substrate.
- FIG. 1 illustrates, in cross-section, a single metal-plate bypass capacitor 10 of the present invention mounted to the upper surface of a semiconductor device 18.
- Semiconductor device 18 is attached to a die bond area 22 of a device package.
- a metal plate assembly 14 of bypass capacitor 10 overlies a silicon substrate 12, and a capacitor dielectric 16 separates a portion of metal assembly 14 from silicon substrate 12.
- Bypass capacitor 10 is attached to semiconductor device 18 by an adhesive layer 20.
- Semiconductor device 18 is, in turn, attached to die bond area 22 by a bonding compound 24.
- a bonding wire 25 is attached to a portion of metal assembly 14 and to a bonding pad (not shown) on the upper surface of semiconductor device 18.
- Bonding wire 25 is one of a number of bonding wires which electrically couple bypass capacitor 10 to semiconductor device 18. It is important to note that bypass capacitor 10 is mounted on the upper surface of semiconductor device 18 in such a way as to permit a number of bonding wires 25 to be attached to bypass capacitor 10 and to semiconductor device 18, and further that bypass capacitor 10 is positioned in such a way that the length of bonding wires 25 is minimized. Bonding wires 25 interconnect the plates of bypass capacitor 10 with power and ground terminals on semiconductor device 18. The attachment of bypass capacitor 10 on the upper surface of semiconductor device 18 enables bypass capacitor 10 to be electrically coupled to semiconductor device 18 using minimal length bonding wires 25. By reducing the length of bonding wires 18, the inductance of the bonding wires is reduced increasing the overall performance of bypass capacitor 10.
- FIG. 2 A plan view of bypass capacitor 10 is illustrated in FIG. 2.
- the detailed construction of metal assembly 14 is illustrated showing connection portions of a top capacitor plate 26, and a substrate contact pad 28. Bonding wires 25, shown in FIG. 1, are connected to either top plate 26 or to substrate contact pad 28, as required, to interconnect bypass capacitor 10 to power and ground bonding pads on semiconductor device 18.
- An electrical isolation structure 30 electrically separates top plate 26 from substrate contract pad 28.
- a passivation layers 32 overlies a central portion of top plate 26, and a perimeter portion of substrate contact pad 28.
- a portion of the upper surface of silicon substrate 12 extends beyond the perimeter of metal assembly 14.
- Silicon substrate 12 functions as the lower electrode plate for bypass capacitor 10, and also as the substrate upon which metal assembly 14 is fabricated. Exposed surfaces of silicon substrate 12 are coated with a dielectric material (not shown) to prevent unwanted electrical contact to silicon substrate 12 external electrically conductive elements, such as bonding wires 25.
- FIG. 3 illustrates, in cross-section, a portion of bypass capacitor 10 taken along section line 3--3 of FIG. 2.
- the spatial relationship of the various elements comprising bypass capacitor 10 can be understood by reference to FIGS. 2 and 3.
- Top plate 26 is separated from silicon substrate 12 by capacitor dielectric 16.
- capacitor dielectric 16 As previously described, top plate 26, capacitor dielectric 16, and silicon substrate 12 form the functional components of a parallel plate capacitor.
- Electrical contact is made to silicon substrate 12 by substrate contact pad 28.
- a doped contact region 34 resides in silicon substrate 12 directly below substrate contact pad 28 and forms an ohmic contact between contact pad 28 and substrate 12.
- top plate 26 and contact pad 28 is provided by patterned portions of two electrically insulating layers.
- a first electrical isolation layer 31 overlies the surface of substrate 12, and a passivation layer 32 overlies isolation layer 31.
- Dielectric isolation structure 30 includes a portion of isolation region 31 overlying the surface of silicon substrate 12, and a portion of passivation layer 32 overlying isolation region 31.
- Contact pad 28 is similarly electrically protected by a portion of isolation region 31 and together passivation layer 32 formed around the perimeter of contact pad 28.
- Passivation layer 32 also covers a substantial portion of top plate 26, leaving only a narrow region at the perimeter of top plate 26 for contact by bonding wires 25.
- Silicon substrate 12 comprises a silicon wafer commonly used in the fabrication of integrated circuit devices.
- Substrate 12 is (1-0-0) silicon substrate having a resistivity of about 0.10 ohm-cm or less.
- silicon substrate 12 is oxidized in a steam oxidation process to form an isolation oxide layer having a thickness of about 3000 to 9000 angstroms.
- a photolithographic pattern is formed on the isolation oxide layer, and a wet chemical etching process is used to form isolation regions 31.
- a sacrificial oxide layer is grown on the exposed surface of silicon substrate 12 and a photolithographic pattern is formed to define doped contact region 34.
- Doped contact region 34 is formed by an implantation of phosphorus using an implant dose of about 5 ⁇ 10 15 ions per square centimeter.
- capacitor dielectric 16 is thermally grown to a thickness of about 400 to 800 angstroms.
- a distinct advantage of the present invention arises from the formation of the capacitor dielectric by thermal oxidation of a silicon surface. The oxidation process can be highly controlled to form a capacitor dielectric having a precise thickness. Additionally, the dry oxidation process forms a capacitor dielectric of high purity. The ability to form the capacitor dielectric as a very thin, highly-pure silicon dioxide layer enhances the performance of bypass capacitor 10.
- a photolithographic pattern is now formed and a portion of capacitor dielectric layer 16 is etched to expose portions of silicon substrate 12 for the formation of a metal contact to doped region 34.
- a metal deposition process is performed to deposit a layer of metal, which contacts silicon substrate 12 and which overlies remaining portions of capacitor dielectric 16.
- the metal deposition process can be carried out using any conventional metal deposition process.
- the metal can be deposited in an E-beam metal evaporation system, or in an RF sputtering deposition system, or the like.
- a metal alloy layer comprising aluminum, silicon, and copper is sputter deposited onto the substrate.
- other metals such as silicon-aluminum, titanium-tungsten, copper, and the like, can be deposited to form top plate 26.
- a photolithographic pattern is formed and the metal layer is etched to define top plate 26, and to define substrate contact pad 28.
- the metal layer is etched in a wet chemical etching solution appropriate to the particular metal.
- the metal is etched in a solution including phosphoric acid.
- the metal layer can be etched in a dry plasma etch.
- a passivation layer is deposited by either chemical vapor deposition (CVD), or by plasma enhanced chemical vapor deposition (PECVD).
- the passivation layer is doped with phosphorus during the deposition process to have a phosphorous concentration of approximately 2 to 6 weight percent.
- the passivation layer is patterned to form openings exposing contact regions of top plate 26 and substrate contact pad 28.
- bypass capacitor of the invention can be fabricated using conventional, well-developed integrated circuit fabrication processes. Furthermore, the utilization of a silicon substrate as a bottom capacitor plate enables the formation of a thin, high-purity capacitor dielectric layer using a conventional, dry-thermal oxidation process. The fabrication of a very thin capacitor dielectric reduces the internal inductance of the capacitor, reducing the voltage drop during high frequency operation of the semiconductor device. Additionally, the fabrication of the bypass capacitor of the present invention on a silicon substrate using a conventional integrated circuit fabrication process serves to substantially reduce the fabrication costs, as compared with bypass capacitors of the prior art.
- the drop in voltage experienced by the power supply is substantially less than that observed in the absence of a bypass capacitor.
- the drop in voltage is also substantially less than that experienced by a device coupled to a dual-plate capacitor of the prior art.
- Table I provides comparative power supply sag values for the single metal-plate capacitor of the invention, and for a dual-plate capacitor of the prior art. Both capacitors were electrically coupled to a "Motorola Digital Signal Processor" having part number DSP 96002.
- both the single metal-plate capacitor and the dual-plate capacitor were mounted to the upper surface of a standard logic device. Accordingly, both capacitors have a similar amount of inductance rising from bonding wires connecting the capacitor to the standard logic device.
- the data shown in Table I indicates that the voltage-drop is reduced by about half of that experienced in the absence of a bypass capacitor. Furthermore, the single metal-plate bypass capacitor of the invention reduces the voltage drop experienced by the power supply to a substantially lower level than that of the dual metal capacitor of the prior art.
- the superior performance of the present invention relates, in part, to the presence of a thin capacitor dielectric formed by the thermal oxidation of silicon substrate 12.
- FIG. 4 Shown in FIG. 4 is another embodiment of the invention having a silicon plate 36 intermediate to top plate 26 and silicon substrate 12. Silicon plate 36 is separated from top plate 26 by a second dielectric layer 38. A metal contact 40 resides adjacent to top plate 26, and is electrically isolated from top plate 26 by portion of passivation layer 32. Silicon plate 36 can be either polycrystalline silicon, or amorphous silicon. Silicon plate 36 is preferably deposited by a CVD process, and doped with a conductivity determining dopant either during or immediately after deposition.
- second dielectric layer 38 can be grown on silicon plate 36 using a thermal oxidation process.
- the embodiment illustrated in FIG. 4 advantageously benefits from the formation of first and second capacitor dielectric layers formed by a thermal oxidation process.
- the second dielectric layer can be grown to a precisely controlled thickness. Low self-inductance in the bypass capacitor is maintained because all capacitor dielectric layers are thin, high-purity, silicon dioxide.
- the addition of silicon plate 36 provides an additional reference plane for a semiconductor device having two power supplies. For example, a semiconductor device operating at 3.5 volts and 5.0 volts.
- bypass capacitor can be interconnected to a semiconductor device by tape-automated-bonded (TAB) leads. It is therefore intended to include within the invention all such variations and modifications as fall within the scope of the appended claims and equivalents thereof.
- TAB tape-automated-bonded
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
TABLE I ______________________________________ Power Supply Sag (volts) Capacitor connected No Capacitor across guiet supply ______________________________________ Single metal-plate 0.552 0.245 Capacitor Dual-Plate Capacitor 0.552 0.458 (prior art) ______________________________________
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/179,275 US5377072A (en) | 1994-01-10 | 1994-01-10 | Single metal-plate bypass capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/179,275 US5377072A (en) | 1994-01-10 | 1994-01-10 | Single metal-plate bypass capacitor |
Publications (1)
Publication Number | Publication Date |
---|---|
US5377072A true US5377072A (en) | 1994-12-27 |
Family
ID=22655899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/179,275 Expired - Lifetime US5377072A (en) | 1994-01-10 | 1994-01-10 | Single metal-plate bypass capacitor |
Country Status (1)
Country | Link |
---|---|
US (1) | US5377072A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864177A (en) * | 1996-12-12 | 1999-01-26 | Honeywell Inc. | Bypass capacitors for chip and wire circuit assembly |
US20030021096A1 (en) * | 2001-07-26 | 2003-01-30 | Harris Corporation | Decoupling capacitor closely coupled with integrated circuit |
US6614643B1 (en) * | 2002-04-24 | 2003-09-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a capacitor element |
US6822333B1 (en) * | 1999-04-27 | 2004-11-23 | Cypress Semiconductor Corporation | Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit |
US20060214170A1 (en) * | 2004-08-13 | 2006-09-28 | Weidong Tian | Versatile system for charge dissipation in the formation of semiconductor device structures |
US20090108401A1 (en) * | 2007-10-26 | 2009-04-30 | Infineon Technologies Ag | Semiconductor device |
US8556452B2 (en) | 2009-01-15 | 2013-10-15 | Ilumisys, Inc. | LED lens |
US20160260795A1 (en) * | 2015-03-03 | 2016-09-08 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3268744A (en) * | 1964-04-16 | 1966-08-23 | Ibm | High capacitance microelectronic decoupling device with low shunt resistance at high frequencies |
US4167018A (en) * | 1976-02-25 | 1979-09-04 | Hitachi, Ltd. | MIS capacitance element |
US4914546A (en) * | 1989-02-03 | 1990-04-03 | Micrel Incorporated | Stacked multi-polysilicon layer capacitor |
US4929989A (en) * | 1988-05-10 | 1990-05-29 | Nec Corporation | MOS type semiconductor device potential stabilizing circuit with series MOS capacitors |
US5049979A (en) * | 1990-06-18 | 1991-09-17 | Microelectronics And Computer Technology Corporation | Combined flat capacitor and tab integrated circuit chip and method |
US5055905A (en) * | 1989-10-19 | 1991-10-08 | Sony Corporation | Semiconductor device |
US5083184A (en) * | 1989-08-08 | 1992-01-21 | Nec Corporation | Capacitance device |
US5095402A (en) * | 1990-10-02 | 1992-03-10 | Rogers Corporation | Internally decoupled integrated circuit package |
US5140496A (en) * | 1991-01-02 | 1992-08-18 | Honeywell, Inc. | Direct microcircuit decoupling |
US5187637A (en) * | 1992-02-14 | 1993-02-16 | At&T Bell Laboratories | Monolithic high-voltage capacitor |
US5281846A (en) * | 1990-05-29 | 1994-01-25 | Texas Instruments Deutschland Gmbh | Electronic device having a discrete capacitor adherently mounted to a lead frame |
US5311057A (en) * | 1992-11-27 | 1994-05-10 | Motorola Inc. | Lead-on-chip semiconductor device and method for making the same |
US5313693A (en) * | 1991-12-06 | 1994-05-24 | Thomson-Csf | Device for the mounting of very wide-band microwave integrated circuits |
-
1994
- 1994-01-10 US US08/179,275 patent/US5377072A/en not_active Expired - Lifetime
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3268744A (en) * | 1964-04-16 | 1966-08-23 | Ibm | High capacitance microelectronic decoupling device with low shunt resistance at high frequencies |
US4167018A (en) * | 1976-02-25 | 1979-09-04 | Hitachi, Ltd. | MIS capacitance element |
US4929989A (en) * | 1988-05-10 | 1990-05-29 | Nec Corporation | MOS type semiconductor device potential stabilizing circuit with series MOS capacitors |
US4914546A (en) * | 1989-02-03 | 1990-04-03 | Micrel Incorporated | Stacked multi-polysilicon layer capacitor |
US5083184A (en) * | 1989-08-08 | 1992-01-21 | Nec Corporation | Capacitance device |
US5055905A (en) * | 1989-10-19 | 1991-10-08 | Sony Corporation | Semiconductor device |
US5281846A (en) * | 1990-05-29 | 1994-01-25 | Texas Instruments Deutschland Gmbh | Electronic device having a discrete capacitor adherently mounted to a lead frame |
US5049979A (en) * | 1990-06-18 | 1991-09-17 | Microelectronics And Computer Technology Corporation | Combined flat capacitor and tab integrated circuit chip and method |
US5095402A (en) * | 1990-10-02 | 1992-03-10 | Rogers Corporation | Internally decoupled integrated circuit package |
US5140496A (en) * | 1991-01-02 | 1992-08-18 | Honeywell, Inc. | Direct microcircuit decoupling |
US5313693A (en) * | 1991-12-06 | 1994-05-24 | Thomson-Csf | Device for the mounting of very wide-band microwave integrated circuits |
US5187637A (en) * | 1992-02-14 | 1993-02-16 | At&T Bell Laboratories | Monolithic high-voltage capacitor |
US5311057A (en) * | 1992-11-27 | 1994-05-10 | Motorola Inc. | Lead-on-chip semiconductor device and method for making the same |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864177A (en) * | 1996-12-12 | 1999-01-26 | Honeywell Inc. | Bypass capacitors for chip and wire circuit assembly |
US6822333B1 (en) * | 1999-04-27 | 2004-11-23 | Cypress Semiconductor Corporation | Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit |
US20070065983A1 (en) * | 2001-07-26 | 2007-03-22 | Harris Corporation | Decoupling capacitor closely coupled with integrated circuit |
US7642131B2 (en) | 2001-07-26 | 2010-01-05 | Harris Corporation | Decoupling capacitor closely coupled with integrated circuit |
US20040075171A1 (en) * | 2001-07-26 | 2004-04-22 | Harris Corporation | Decoupling capacitor closely coupled with integrated circuit |
US6700794B2 (en) | 2001-07-26 | 2004-03-02 | Harris Corporation | Decoupling capacitor closely coupled with integrated circuit |
US7145233B2 (en) | 2001-07-26 | 2006-12-05 | Harris Corporation | Decoupling capacitor closely coupled with integrated circuit |
US20030021096A1 (en) * | 2001-07-26 | 2003-01-30 | Harris Corporation | Decoupling capacitor closely coupled with integrated circuit |
US7705450B2 (en) | 2001-07-26 | 2010-04-27 | Harris Corporation | Decoupling capacitor closely coupled with integrated circuit |
US6614643B1 (en) * | 2002-04-24 | 2003-09-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a capacitor element |
US20060214170A1 (en) * | 2004-08-13 | 2006-09-28 | Weidong Tian | Versatile system for charge dissipation in the formation of semiconductor device structures |
US7671445B2 (en) * | 2004-08-13 | 2010-03-02 | Texas Instruments Incorporated | Versatile system for charge dissipation in the formation of semiconductor device structures |
US20090108401A1 (en) * | 2007-10-26 | 2009-04-30 | Infineon Technologies Ag | Semiconductor device |
DE102008051443B4 (en) * | 2007-10-26 | 2014-04-03 | Infineon Technologies Ag | Semiconductor module and manufacturing method thereof |
US9331057B2 (en) | 2007-10-26 | 2016-05-03 | Infineon Technologies Ag | Semiconductor device |
US8556452B2 (en) | 2009-01-15 | 2013-10-15 | Ilumisys, Inc. | LED lens |
US20160260795A1 (en) * | 2015-03-03 | 2016-09-08 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100509898B1 (en) | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same | |
US5780930A (en) | Method for direct attachment of an on-chip bypass capacitor in an integrated circuit | |
US8169063B2 (en) | Semiconductor component and method for producing the same | |
US5478773A (en) | Method of making an electronic device having an integrated inductor | |
US4505029A (en) | Semiconductor device with built-up low resistance contact | |
US20050282347A1 (en) | Semiconductor device with inductive component and method of making | |
US5134539A (en) | Multichip module having integral decoupling capacitor | |
EP0583877B1 (en) | Bond pad structure of an integrated circuit and manufacturing method thereof | |
KR20020063675A (en) | Wafer level package including ground metal layer | |
JPH09504909A (en) | Thin film inductor, inductor network, other passive element, method of manufacturing device with integrated active element, and manufactured device | |
US20040217443A1 (en) | Semiconductor device with inductive component and method of making | |
WO1999045588A2 (en) | Semiconductor device comprising a glass supporting body onto which a substrate with semiconductor elements and a metallization is attached by means of an adhesive | |
US5377072A (en) | Single metal-plate bypass capacitor | |
EP0154431B1 (en) | Integrated circuit chip assembly | |
US4596070A (en) | Interdigitated IMPATT devices | |
JP2622156B2 (en) | Contact method and structure for integrated circuit pads | |
KR20010104319A (en) | Methods for forming co-axial interconnect lines in a cmos process | |
JP2001223340A (en) | Capacitor and forming method thereof | |
US6908845B2 (en) | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme | |
US6680519B2 (en) | Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry | |
GB2364170A (en) | Dual damascene bond pad structure for lowering stress and allowing circuitry under pads | |
JP2001502845A (en) | RF power package with double grounding | |
GB2095904A (en) | Semiconductor device with built-up low resistance contact and laterally conducting second contact | |
US6563192B1 (en) | Semiconductor die with integral decoupling capacitor | |
US6285070B1 (en) | Method of forming semiconductor die with integral decoupling capacitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MOTOROLA, INC., ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SPARKMAN, AUBREY K.;CALHOUN, KEVIN A.;DAHM, JONATHAN C.;AND OTHERS;REEL/FRAME:006841/0871 Effective date: 19940106 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 |
|
AS | Assignment |
Owner name: ZOZO MANAGEMENT, LLC, DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:034034/0236 Effective date: 20120814 |
|
AS | Assignment |
Owner name: APPLE INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ZOZO MANAGEMENT, LLC;REEL/FRAME:034732/0019 Effective date: 20141219 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0553 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0143 Effective date: 20151207 |