US5371040A - Method for manufacturing semiconductor components with short switching time - Google Patents
Method for manufacturing semiconductor components with short switching time Download PDFInfo
- Publication number
- US5371040A US5371040A US08/132,912 US13291293A US5371040A US 5371040 A US5371040 A US 5371040A US 13291293 A US13291293 A US 13291293A US 5371040 A US5371040 A US 5371040A
- Authority
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- United States
- Prior art keywords
- semiconductor
- diffusion process
- transition metal
- area
- weakly doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000002800 charge carrier Substances 0.000 claims abstract description 11
- 239000010931 gold Substances 0.000 claims abstract description 11
- 229910052737 gold Inorganic materials 0.000 claims abstract description 11
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 8
- 150000003624 transition metals Chemical class 0.000 claims abstract description 8
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 11
- 229910052742 iron Inorganic materials 0.000 claims description 5
- 238000005496 tempering Methods 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims 1
- 150000002505 iron Chemical class 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/221—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/023—Deep level dopants
Definitions
- the switching time and the switching behavior are determined by the lifetime of the charge carriers; in fast semiconductor components in particular, both a short switching time (low forward voltage) and a good switching behavior (small reverse current peak and soft-recovery behavior) are of interest.
- impurities are selectively placed in the semiconductor array, and the impurity profile should be as inhomogeneous as possible in order to improve the component's properties. Standard diffusion processes with heavy metals do however have the drawback that a fairly homogeneous concentration distribution of the impurities results.
- the object underlying the invention is to provide a method in accordance with the preamble of claim 1, whereby the required charge carrier lifetime profile can be selectively set, and in particular the charge carrier lifetime can be reduced to a particularly high degree in a partial area of the semiconductor array.
- a homogeneous gold diffusion process is carried out for homogeneous placing of impurities in the semiconductor array, where the concentration of gold impurities--which is adjustable using the diffusion temperature--can be relatively low
- a layer of a medium-fast-diffusing 3d transition metal affecting the charge carrier lifetime is deposited (for example by sputtering) onto that side of the semiconductor array having a shorter distance from the weakly doped semiconductor area
- an inhomogeneous short-term diffusion process for example a rapid thermal annealing process (RTA)--the 3d transition metal is provided in the necessary concentration at the required point, i.e. in a partial area of the weakly doped semiconductor area, and hence an inhomogeneous distribution of the impurities or an axial impurity profile is obtained in the semiconductor array
- RTA rapid thermal annealing process
- the impurity complexes thus formed can be retroactively influenced such that the concentration distribution of the impurities can be variably adjusted.
- the diffusion behavior of the additive and lifetime-affecting impurities in the second diffusion process is controllable, so that the lifetime of the charge carriers can be selectively reduced at the required point
- the high concentration of additive impurities is not a big problem, since it is the weakly doped semiconductor area which is crucial for the component properties.
- FIG. 1 shows a section through a semiconductor component, in which an axial impurity profile is to be set
- FIG. 2 the concentration distribution of the charge carriers and impurities.
- the doping diffusions--curve a in FIG. 2 shows the resultant doping profile--a gold layer 5 (for example 10 nm thick) is deposited (for example vapor-deposited) onto the surface of the N + layer 3 and diffused into the semiconductor array (for example for 1 hour at 900° C.); in accordance with curve b, FIG.
- the iron/gold complexes represent considerably stronger recombination centers than the gold impurities, they determine the charge carrier lifetime in the partial area 2a of the weakly doped N - area 2 and hence provide the required axial lifetime profile. Thanks to a tempering process at a temperature of, for example, 300° C., the iron/gold complexes are partially or completely dissociated, such that with this process a certain concentration of iron/gold pairs can be selectively adjusted and hence also the charge carrier lifetime.
- the further manufacturing steps, such as passivation, metallization and assembly, are implemented as standard processes.
- the process in accordance with the invention can be used in all semiconductor components having a short switching time and whose component properties are to be selectively adjusted; for example, components with several PN junctions may be mentioned in addition to the diode described.
Abstract
A method is described for manufacturing semiconductor components with short switching time, having a weakly doped semiconductor area in contact with a PN junction. In order to obtain an inhomogeneous impurity distribution in the axial direction of the semiconductor array, the following process steps are implemented:
a) gold impurities are placed in the semiconductor array and homogeneously distributed there in a first diffusion process,
b) a layer comprising a 3d transition metal affecting the charge carrier lifetime is deposited onto that surface side of the semiconductor array having a shorter distance from the weakly doped semiconductor area,
c) the 3d transition metal is incorporated into the semiconductor array by a second diffusion process and is inhomogeneously distributed there, such that an impurity surplus is generated in a partial area of the weakly doped semiconductor area in the vicinity of the PN junction.
Description
In semiconductor components, the switching time and the switching behavior are determined by the lifetime of the charge carriers; in fast semiconductor components in particular, both a short switching time (low forward voltage) and a good switching behavior (small reverse current peak and soft-recovery behavior) are of interest. To set the charge carrier lifetime or switching time, impurities are selectively placed in the semiconductor array, and the impurity profile should be as inhomogeneous as possible in order to improve the component's properties. Standard diffusion processes with heavy metals do however have the drawback that a fairly homogeneous concentration distribution of the impurities results.
The object underlying the invention is to provide a method in accordance with the preamble of claim 1, whereby the required charge carrier lifetime profile can be selectively set, and in particular the charge carrier lifetime can be reduced to a particularly high degree in a partial area of the semiconductor array.
This object is attained in accordance with the invention by the features and characteristics of claim 1.
Advantageous embodiments of the invention are the subject of sub-claims.
The following process steps for manufacture of the semiconductor component are implemented in accordance with the invention:
first, a homogeneous gold diffusion process is carried out for homogeneous placing of impurities in the semiconductor array, where the concentration of gold impurities--which is adjustable using the diffusion temperature--can be relatively low
then a layer of a medium-fast-diffusing 3d transition metal affecting the charge carrier lifetime is deposited (for example by sputtering) onto that side of the semiconductor array having a shorter distance from the weakly doped semiconductor area
by an inhomogeneous short-term diffusion process--for example a rapid thermal annealing process (RTA)--the 3d transition metal is provided in the necessary concentration at the required point, i.e. in a partial area of the weakly doped semiconductor area, and hence an inhomogeneous distribution of the impurities or an axial impurity profile is obtained in the semiconductor array
by a subsequent tempering process, the impurity complexes thus formed can be retroactively influenced such that the concentration distribution of the impurities can be variably adjusted.
The method in accordance with the invention combines a number of advantages:
the diffusion behavior of the additive and lifetime-affecting impurities in the second diffusion process is controllable, so that the lifetime of the charge carriers can be selectively reduced at the required point
a very effective inhomogeneous impurity profile--in conjunction with optimized component properties (switch-off operation/on-state power losses)--can be selectively adjusted
the homogeneously distributed gold impurities still present in the semiconductor array have the effect that the reverse current does not die away too slowly when the semiconductor component is switched off
in the highly doped surface area, the high concentration of additive impurities is not a big problem, since it is the weakly doped semiconductor area which is crucial for the component properties.
The process is described in further detail on the basis of an embodiment: FIG. 1 shows a section through a semiconductor component, in which an axial impurity profile is to be set, and FIG. 2 the concentration distribution of the charge carriers and impurities.
In accordance with the axial sectional view in FIG. 1, the semiconductor component--for example a diode with a blocking voltage of more than 1000 V--comprises the P+ layer 1, the N- layer 2 and the N+ layer 3, with a PN junction 4 being formed between the P+ layer 1 and the N- layer 2. After implementation of the doping diffusions--curve a in FIG. 2 shows the resultant doping profile--a gold layer 5 (for example 10 nm thick) is deposited (for example vapor-deposited) onto the surface of the N+ layer 3 and diffused into the semiconductor array (for example for 1 hour at 900° C.); in accordance with curve b, FIG. 2, this results in a fairly homogeneous, slightly U-shaped profile of the gold impurity concentration with a mean value of, for example, 1014 cm-3. An iron layer 6 is then deposited (for example sputtered) onto the surface of the P+ layer 1 and diffused in using an RTA process at 950° C. for 10 seconds (the RTA process allows a steeply falling diffusion profile to be obtained in the semiconductor array). With the aid of a selectively controlled cooling phase at the end of the RTA process, it is possible to effect an almost total transformation of the iron atoms and gold atoms into iron/gold complexes that are very efficient recombination centers in silicon. The concentration of iron/gold complexes--cf. curve c, FIG. 2--is around 2×1014 cm-3 with a penetration depth of 10 μm, for example, and drops steeply in the axial direction as the distance from the surface increases. Since the iron/gold complexes represent considerably stronger recombination centers than the gold impurities, they determine the charge carrier lifetime in the partial area 2a of the weakly doped N- area 2 and hence provide the required axial lifetime profile. Thanks to a tempering process at a temperature of, for example, 300° C., the iron/gold complexes are partially or completely dissociated, such that with this process a certain concentration of iron/gold pairs can be selectively adjusted and hence also the charge carrier lifetime. The further manufacturing steps, such as passivation, metallization and assembly, are implemented as standard processes. The process in accordance with the invention can be used in all semiconductor components having a short switching time and whose component properties are to be selectively adjusted; for example, components with several PN junctions may be mentioned in addition to the diode described.
Claims (6)
1. A method for manufacturing semiconductor components with short switching time, having a weakly doped semiconductor area (2) in contact with a PN junction (4), wherein, in order to obtain an inhomogeneous impurity distribution in the axial direction of the semiconductor array
a) gold impurities are placed in said semiconductor array and homogeneously distributed there in a first diffusion process,
b) a layer (6) comprising a 3d transition metal affecting the charge carrier lifetime is deposited onto that surface side of said semiconductor array having a shorter distance from said weakly doped semiconductor area (2),
c) said 3d transition metal is incorporated into said semiconductor array by a second diffusion process and is inhomogeneously distributed there, such that an impurity surplus is generated in a partial area (2a) of said weakly doped semiconductor area (2) in the vicinity of said PN junction (4).
2. A method according to claim 1, wherein said second diffusion process is implemented in the form of a rapid-thermal-annealing process.
3. A method according to claim 1, wherein the concentration of impurities is adjusted in a tempering process following said second diffusion process.
4. A method according to claim 3, wherein said tempering process is implemented at a temperature of 250° C. to 350° C.
5. A method according to claim 1, wherein iron is used as said 3d transition metal in said second diffusion process, and wherein iron/gold impurity pairs are formed in said process.
6. A method according to claim 1, wherein chrome is used as said 3d transition metal of said second diffusion process.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4236300A DE4236300A1 (en) | 1992-10-28 | 1992-10-28 | Fast-switching semiconductor junction device mfr. by double diffusion - by partial or total dissociation of iron-gold complexes during tempering at e.g. 300 deg.C to shorten carrier lifetime |
| DE4236300 | 1992-10-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US5371040A true US5371040A (en) | 1994-12-06 |
Family
ID=6471497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/132,912 Expired - Fee Related US5371040A (en) | 1992-10-28 | 1993-10-07 | Method for manufacturing semiconductor components with short switching time |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5371040A (en) |
| DE (1) | DE4236300A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5441900A (en) * | 1993-03-09 | 1995-08-15 | National Semiconductor Corporation | CMOS latchup suppression by localized minority carrier lifetime reduction |
| US20040192003A1 (en) * | 1996-06-03 | 2004-09-30 | Micron Technology, Inc. | Method for forming a metallization layer |
| US20130228903A1 (en) * | 2007-04-27 | 2013-09-05 | Infineon Technologies Austria Ag | Method of Producing a Vertically Inhomogeneous Platinum or Gold Distribution in a Semiconductor Substrate and in a Semiconductor Device |
| US20150280015A1 (en) * | 2014-03-28 | 2015-10-01 | Stmicroelectronics S.R.L. | Diode with insulated anode regions |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1961739A1 (en) * | 1968-12-11 | 1970-06-18 | Hitachi Ltd | Semiconductor device and method for making the same |
| DE2735769A1 (en) * | 1977-08-09 | 1979-02-22 | Licentia Gmbh | Adjustment of minority charge carrier life - uses platinum for recombination centres, and has another element which is diffused, whose atom dia. is greater than that of silicon |
| JPS56114367A (en) * | 1980-02-14 | 1981-09-08 | Toshiba Corp | Semiconductor device |
| DE3328521A1 (en) * | 1983-08-06 | 1985-02-14 | SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg | EPITAXIAL DIODE FOR HIGH BLOCKING VOLTAGE |
| DE3435464A1 (en) * | 1984-09-27 | 1986-04-10 | Robert Bosch Gmbh, 7000 Stuttgart | Rectifier diode |
| EP0277336A1 (en) * | 1987-01-13 | 1988-08-10 | BBC Brown Boveri AG | Method of making a fast semiconductor device |
| DE3823795A1 (en) * | 1988-07-14 | 1990-01-18 | Semikron Elektronik Gmbh | FAST PERFORMANCE DIODE |
| JPH0251236A (en) * | 1988-08-12 | 1990-02-21 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| DE3832748A1 (en) * | 1988-09-27 | 1990-03-29 | Asea Brown Boveri | PERFORMANCE SEMICONDUCTOR DIODE |
| US4963509A (en) * | 1988-12-16 | 1990-10-16 | Sanken Electric Co., Ltd. | Gold diffusion method for semiconductor devices of high switching speed |
| DE3913123A1 (en) * | 1989-04-21 | 1990-10-25 | Asea Brown Boveri | Generation of recombination centres in semiconductor devices - by electron beam irradiation then stabilisation in medium temp. anneal after metallisation |
-
1992
- 1992-10-28 DE DE4236300A patent/DE4236300A1/en not_active Withdrawn
-
1993
- 1993-10-07 US US08/132,912 patent/US5371040A/en not_active Expired - Fee Related
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| US4009484A (en) * | 1968-12-11 | 1977-02-22 | Hitachi, Ltd. | Integrated circuit isolation using gold-doped polysilicon |
| DE2735769A1 (en) * | 1977-08-09 | 1979-02-22 | Licentia Gmbh | Adjustment of minority charge carrier life - uses platinum for recombination centres, and has another element which is diffused, whose atom dia. is greater than that of silicon |
| JPS56114367A (en) * | 1980-02-14 | 1981-09-08 | Toshiba Corp | Semiconductor device |
| DE3328521A1 (en) * | 1983-08-06 | 1985-02-14 | SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg | EPITAXIAL DIODE FOR HIGH BLOCKING VOLTAGE |
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| EP0277336A1 (en) * | 1987-01-13 | 1988-08-10 | BBC Brown Boveri AG | Method of making a fast semiconductor device |
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| JPH0251236A (en) * | 1988-08-12 | 1990-02-21 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
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| US4963509A (en) * | 1988-12-16 | 1990-10-16 | Sanken Electric Co., Ltd. | Gold diffusion method for semiconductor devices of high switching speed |
| DE3913123A1 (en) * | 1989-04-21 | 1990-10-25 | Asea Brown Boveri | Generation of recombination centres in semiconductor devices - by electron beam irradiation then stabilisation in medium temp. anneal after metallisation |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5441900A (en) * | 1993-03-09 | 1995-08-15 | National Semiconductor Corporation | CMOS latchup suppression by localized minority carrier lifetime reduction |
| US20040192003A1 (en) * | 1996-06-03 | 2004-09-30 | Micron Technology, Inc. | Method for forming a metallization layer |
| US20130228903A1 (en) * | 2007-04-27 | 2013-09-05 | Infineon Technologies Austria Ag | Method of Producing a Vertically Inhomogeneous Platinum or Gold Distribution in a Semiconductor Substrate and in a Semiconductor Device |
| US8999826B2 (en) * | 2007-04-27 | 2015-04-07 | Infineon Technologies Austria Ag | Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate and in a semiconductor device |
| US9263529B2 (en) * | 2007-04-27 | 2016-02-16 | Infineon Technologies Austria Ag | Semiconductor device with vertically inhomogeneous heavy metal doping profile |
| US20150280015A1 (en) * | 2014-03-28 | 2015-10-01 | Stmicroelectronics S.R.L. | Diode with insulated anode regions |
| US20160071984A1 (en) * | 2014-03-28 | 2016-03-10 | Stmicroelectronics S.R.L. | Diode with insulated anode regions |
| US9419148B2 (en) * | 2014-03-28 | 2016-08-16 | Stmicroelectronics S.R.L. | Diode with insulated anode regions |
| US9564541B2 (en) * | 2014-03-28 | 2017-02-07 | Stmicroelectronics S.R.L. | Diode with insulated anode regions |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4236300A1 (en) | 1994-05-11 |
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Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |