US5030857B1 - - Google Patents

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Publication number
US5030857B1
US5030857B1 US39856389A US5030857B1 US 5030857 B1 US5030857 B1 US 5030857B1 US 39856389 A US39856389 A US 39856389A US 5030857 B1 US5030857 B1 US 5030857B1
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US
United States
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
Other languages
English (en)
Inventor
J Sanwo Ikuo
H Milby Gregory
X Le Quynh-Giao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Priority to US07/398,563 priority Critical patent/US5030857A/en
Assigned to NCR CORPORATION reassignment NCR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: LE, QUYNH-GIAO X., MILBY, GREGORY H., SANWO, IKUO J.
Application granted granted Critical
Publication of US5030857A publication Critical patent/US5030857A/en
Publication of US5030857B1 publication Critical patent/US5030857B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
US07/398,563 1989-08-25 1989-08-25 High speed digital computer data transfer system having reduced bus state transition time Expired - Fee Related US5030857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US07/398,563 US5030857A (en) 1989-08-25 1989-08-25 High speed digital computer data transfer system having reduced bus state transition time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/398,563 US5030857A (en) 1989-08-25 1989-08-25 High speed digital computer data transfer system having reduced bus state transition time

Publications (2)

Publication Number Publication Date
US5030857A US5030857A (en) 1991-07-09
US5030857B1 true US5030857B1 (show.php) 1993-02-02

Family

ID=23575857

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/398,563 Expired - Fee Related US5030857A (en) 1989-08-25 1989-08-25 High speed digital computer data transfer system having reduced bus state transition time

Country Status (1)

Country Link
US (1) US5030857A (show.php)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134316A (en) * 1990-12-12 1992-07-28 Vlsi Technology, Inc. Precharged buffer with reduced output voltage swing
US5225722A (en) * 1990-04-24 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Signal transmission circuit and signal transmission method
US5491653A (en) * 1994-10-06 1996-02-13 International Business Machines Corporation Differential carry-save adder and multiplier
US5522081A (en) * 1994-04-28 1996-05-28 Dell Usa, L.P. Drive current detection and optimization circuit for computer systems
US5661417A (en) * 1994-12-20 1997-08-26 Mitsubishi Denki Kabushiki Kaisha Bus system and bus sense amplifier with precharge means
US5781757A (en) * 1994-10-11 1998-07-14 International Business Machines Corporation Adaptive scalable cache coherence network for a multiprocessor data processing system
US5847581A (en) * 1996-12-31 1998-12-08 Intel Corporation Low power CMOS precision input receiver with integrated reference
US8766734B2 (en) 2012-04-27 2014-07-01 Txc Corporation Through silicon via-based oscillator wafer-level-package structure and method for fabricating the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4498021A (en) * 1982-07-13 1985-02-05 Matsushita Electric Industrial Co., Ltd. Booster for transmitting digital signal
US4488066A (en) * 1982-11-08 1984-12-11 At&T Bell Laboratories Databus coupling arrangement using transistors of complementary conductivity type
US4572972A (en) * 1983-01-18 1986-02-25 At&T Laboratories CMOS Logic circuits with all pull-up transistors integrated in separate chip from all pull-down transistors
JPS6134619A (ja) * 1984-07-26 1986-02-18 Mitsubishi Electric Corp Ｍｏｓトランジスタ回路
US4598216A (en) * 1984-08-27 1986-07-01 Ncr Corporation Assist circuit for a data bus in a data processing system
US4763023A (en) * 1987-02-17 1988-08-09 Rockwell International Corporation Clocked CMOS bus precharge circuit having level sensing
US4761567A (en) * 1987-05-20 1988-08-02 Advanced Micro Devices, Inc. Clock scheme for VLSI systems
US4918329B1 (en) * 1988-07-25 1993-06-01 Data transmission system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225722A (en) * 1990-04-24 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Signal transmission circuit and signal transmission method
US5134316A (en) * 1990-12-12 1992-07-28 Vlsi Technology, Inc. Precharged buffer with reduced output voltage swing
US5522081A (en) * 1994-04-28 1996-05-28 Dell Usa, L.P. Drive current detection and optimization circuit for computer systems
US5491653A (en) * 1994-10-06 1996-02-13 International Business Machines Corporation Differential carry-save adder and multiplier
US5781757A (en) * 1994-10-11 1998-07-14 International Business Machines Corporation Adaptive scalable cache coherence network for a multiprocessor data processing system
US5661417A (en) * 1994-12-20 1997-08-26 Mitsubishi Denki Kabushiki Kaisha Bus system and bus sense amplifier with precharge means
US5847581A (en) * 1996-12-31 1998-12-08 Intel Corporation Low power CMOS precision input receiver with integrated reference
US8766734B2 (en) 2012-04-27 2014-07-01 Txc Corporation Through silicon via-based oscillator wafer-level-package structure and method for fabricating the same

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Publication number Publication date
US5030857A (en) 1991-07-09

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Legal Events

Date Code Title Description
AS Assignment

Owner name: NCR CORPORATION, OHIO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:SANWO, IKUO J.;MILBY, GREGORY H.;LE, QUYNH-GIAO X.;REEL/FRAME:005117/0609

Effective date: 19890808

CO Commissioner ordered reexamination

Free format text: 920218

B1 Reexamination certificate first reexamination
FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Lapsed due to failure to pay maintenance fee

Effective date: 19990709

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362