US4663830A - Forming deep buried grids of implanted zones being vertically and laterally offset by mask MEV implant - Google Patents

Forming deep buried grids of implanted zones being vertically and laterally offset by mask MEV implant Download PDF

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US4663830A
US4663830A US06/699,018 US69901885A US4663830A US 4663830 A US4663830 A US 4663830A US 69901885 A US69901885 A US 69901885A US 4663830 A US4663830 A US 4663830A
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grid
mask
semiconductor substrate
structures
buried
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US06/699,018
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Dietrich Braunig
Meinhard Knoll
Joachim Laschinski
Wolfgang Fahrner
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Hahn Meitner Institut Berlin GmbH
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Hahn Meitner Institut fuer Kernforschung Berlin GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation

Definitions

  • the present invention relates to a semiconductor power device, particularly a thyristor or gridistor, and to a method of fabricating such a component.
  • n - doped semiconductor material such as a silicon wafer
  • a masking layer produced by thermal oxidation.
  • Windows are etched into the marginal areas of the wafer, through which the connections for the grid are produced by planar boron diffusion.
  • a p + anode is produced on the underside of the wafer.
  • a pattern corresponding to a metallic grid mask is produced by etching of the oxide mask in the active area of the wafter.
  • the grid is then produced at the wafer surface by boron diffusion between the bars of the grid.
  • a window is etched out of the oxide mask, substantially above the entire area of the surface grid structure thus formed, in which an n + doped layer is grown thereover by silicon liquid phase epitaxy.
  • a buried grid structure is thus obtained in the semiconductor wafer.
  • the not yet covered peripheral areas of the grid structure are provided with conducting connections by contact metallization.
  • a contradoped conductive grid by vacuum tube analogy, is introduced into the semiconductor.
  • a plurality of masking and etching operations is needed for this purpose, since epotaxy requires an array of contradoping material on the semiconductor surface and a subsequent growth of the basic material thereover by further epitaxy, to transform the array into a buried grid structure.
  • the prior art method requires too many working steps, and is therefore very expensive.
  • the present invention is directed to a method of the above mentioned kind requiring a minimum of masking and etching operations to produce a buried grid structure in a semiconductor material, particularly a silicon wafer.
  • an object of the present invention is to provide a method of fabricating a semiconductor power component, particularly a thyristor or gridistor, by introducing into a semiconductor substrate, particularly a silicon wafer, burried grid structure, and using a metallic grid mask, characterized in that the buried grid structure is reproduced directly within the semiconductor substrate by contradoping ion implantation through the metallic grid mask, by a high energy accelerator.
  • the wire thickness in the depth direction, i.e. in the direction of implantation, of the buried grid is determined by the physical limits of the half-value width of the ions, as has been described in German Pat. No. P 33 23 672.0 of July 1, 1983.
  • the lateral wire thickness must be determined by a definite metallic grid mask. The problems arising in this regard are the accuracy of the metallic grid mask, and the looping of the grid wires to an outer contact for the control electrode. It must be taken into account that the lateral spacing in the grid must not exceed the value of twice the space charge zone obtained by an applied typical blocking voltage. Depending on the doping and voltage, these values are in the 10 ⁇ m range.
  • the thickness or depth of the bars of the mask must substantially exceed the penetration depth of the ions into the mask (which latter typically lies at 100 ⁇ m).
  • the grid mask must be rectangular exactly enough to eliminate half-shadow effects, and thus avoid short circuiting.
  • Such masks having a mask depth-to-grid spacing ratio larger than 10 cannot be produced in practice.
  • the material thickness of the gride mask is selected to permit the ion to become implanted in the semiconductor substrate also through the bars of the grid mask so that two buried grid structures are produced in the semiconductor substrate which are vertically spaced from each other and laterally offset relative to each other.
  • the peripheral edge of the semiconductor substrate is beveled at an acute angle measured from a top plane thereof and the control/switch electrodes formed on the underside of the semiconductor substrate.
  • the ion implantation simultaneously produces buried conductive structures which extend parallel to the bevels, between the buried grid structure and the control/switch electrode.
  • the bevel angle is 10° to 60°, preferably 10° to 30°.
  • a further object of the invention is to provide a semiconductor power component, particularly a thyristor or gridistor, which comprises a buried grid structure and a control electrode which is conductively connected to the buried grid structure.
  • the peripheral edge of the semiconductor substrate is beveled at an acute angle with respect to a top surface thereof and a control/switch electrode is provided on the underside of the semiconductor substrate.
  • Two buried grid structures are provided in the semiconductor substrate which are vertically separated from each other and laterally offset relative to each other. The two buried grid structures are connected to the control/switch electrode by conductive structures which extend within the semiconductor substrate parallel to the beveled edge.
  • a still further object of the invention is to provide a method of fabrication which is simple, effective and economical, while providing a semiconductor component which is simple in design, rugged in construction and economical to manufacture.
  • FIGS. 1 to 4 are sequential vertical sectional view of the power device during the various steps of the process
  • FIG. 5 is an enlarged partial view of the device during the ion implantation through a metallic grid mask, effected to produce two buried grid structures;
  • FIG. 6 is a perspective view of a semiconductor power device during the ion implantation of a single grid structure with the use of a metallic grid mask of large thickness or depth.
  • the invention illustrated and embodied therein includes a method of fabricating a power component shown sequentially in FIGS. 1, 2, 3 and 4, as well as a power component partially illustrated in FIGS. 5 and 6.
  • the n - doped starting material or semiconductor substrate 1 shown in FIG. 1 is silicon doped with phosphorus at a concentration of 10 13 /cm 3 .
  • the starting material is a cylindrical wafer having a diameter of 3/4 of an inch (19 mm) and a thickness of about 900 ⁇ m.
  • n + contacts with a concentration of 10 19 /cm 3 and a penetration depth of 50 to 80 ⁇ m are diffused.
  • a boron doped p + contact 4 with a concentration of 10 18 /cm 3 to 10 19 /cm 3 and in the shape of a ring is established by diffusion.
  • the next operation is metallizing of the top side 3 by vapor deposition, i.e. coating with a 50 to 100 ⁇ m metallic layer 5, particularly of aluminum.
  • the next operation is producing of the grid pattern in metallic layer 5.
  • FIG. 3 which is turned through 90° relative to FIG. 2
  • an array of strips is etched out of metallic layer 5 to form ribs 8.
  • the spacing of the ribs and the thickness of each of the ribs (with the exception of the marginal ones near the beveled edge is 100 ⁇ m.
  • the etching is performed in a plasm etching unit.
  • the next step of counterdoping ion implantation is performed according to FIG. 4 showing the wafer again turned through 90° relative to FIG. 3.
  • the wafer is exposed in a high energy accelerator to a high energy ion radiation 9.
  • the employed high energy accelerator is a Van-de-Graaf Cyclotron-Combination for heavy ions (VICKSI), operating in the range of 80 to 100 MeV and achieving an ion penetration depth of 200 ⁇ m, considering boron, as in the present example.
  • the ion concentration is 10 14 /cm 2 to 10 15 /cm 2 .
  • the counterdoping ion implantation produces within the semiconductor substrate 1 directly two buried grid structures 10, 11 which are vertically separated as well as laterally spaced from each other.
  • FIG. 5 which again is turned through 90° relative to FIG. 4, shows, in an enlarged partial sectional view of wafer 1, the individual wires or rows of each of the buried grid structures 10, 11 which extend spaced from each other in depth by a distance d S as desired, namely within the detection limit of 4 ⁇ m.
  • the grid spacing d G corresponds to the width of ribs 8 of metallic mask 5 provided on the top of wafer 1.
  • the beveled edge 7 makes it possible to produce contacting connections 12, 13 between the two buried grid structures 10, 11 and the p + doped control of switch electrode 4. These connections are formed as self-adjusted connections directly by the ions penetrating into the substrate and becoming implanted in two parallel planes.
  • FIG. 6 shows the use of a metallic grid mask 8' having a depth dimension t M which substantially exceeds the penetration depth of the ions into the mask. Therefore, only one buried grid structure 11' can be produced with a spacing d G corresponding to the width of a rib 8' of the mask.
  • the ions passing through ribs 8' are stopped by the material of the ribs and become implanted in the rib as a layer 10'. However, in the following process of the wafer, this implanted ion layer 10' is etched away along with the entire mask including ribs 8'.
  • the invention is a method of fabricating a semiconductor power component from a semiconductor substrate 1, having a top surface 3, an undersurface 2 and a side surface 6, comprising: forming a metallic grid mask 5, 8 on the top surface 3 and using a high energy accelerator to bury a grid structure 10, 11 directly into the substrate through the top surface by contradoping ion implantation.
  • the present invention also includes the semiconductor power component itself which comprises: a semiconductor substrate 1 having a top surface 3, an undersurface 2 and a side surface 6 which is beveled at an acute angle ⁇ with respect to the top surface; a control/switch electrode 4 on the undersurface 2; two buried grid structures 10,11 each including a multitude of elements implanted in the substrate with the elements of one grid structure being vertically spaced from the elements of the other grid structure and the elements of the one grid structure being laterally spaced from the elements of the other grid structure; and a conductive structure implanted in the substrate and extending parallel to the beveled edges for connecting the control/switch electrode to the grid structures.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A buried grid structure is produced in a semiconductor material particularly a silicon wafer, while using a metallic grid mask. The buried grid is formed directly within the semiconductor material by contradoping ion implantation by means of a high energy accelerator through the metallic grid mask. The bars or ribs of the metallic grid mask stop the ions passing therethrough so that two vertically separated and laterally offset buried grid structures are produced. By beveling the periphery of the wafer, buried conductive structures are formed at the same time as connections between the buried grid structures and a control electrode provided on the back side of the wafer.

Description

FIELD AND BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor power device, particularly a thyristor or gridistor, and to a method of fabricating such a component.
Two kinds of grid structures are known for semiconductor power devices, namely the surface grid structure and the buried grid structure (see IEEE Transactions on Electron Devices, Vol. ED-27, No. A, Nov. 1980, pages 2141 to 2145). To fabricate the semiconductor power component with a buried grid structure, an n- doped semiconductor material, such as a silicon wafer, is provided on its surface with a masking layer produced by thermal oxidation. Windows are etched into the marginal areas of the wafer, through which the connections for the grid are produced by planar boron diffusion. At the same time, within the same boron diffusion cycle, a p+ anode is produced on the underside of the wafer. Thereupon a pattern corresponding to a metallic grid mask is produced by etching of the oxide mask in the active area of the wafter. The grid is then produced at the wafer surface by boron diffusion between the bars of the grid. Further, a window is etched out of the oxide mask, substantially above the entire area of the surface grid structure thus formed, in which an n+ doped layer is grown thereover by silicon liquid phase epitaxy. A buried grid structure is thus obtained in the semiconductor wafer. In further working steps, the not yet covered peripheral areas of the grid structure are provided with conducting connections by contact metallization.
With this prior art method, for example, during the fabrication of a gridistor, a contradoped conductive grid, by vacuum tube analogy, is introduced into the semiconductor. A plurality of masking and etching operations is needed for this purpose, since epotaxy requires an array of contradoping material on the semiconductor surface and a subsequent growth of the basic material thereover by further epitaxy, to transform the array into a buried grid structure. The prior art method requires too many working steps, and is therefore very expensive.
SUMMARY OF THE INVENTION
The present invention is directed to a method of the above mentioned kind requiring a minimum of masking and etching operations to produce a buried grid structure in a semiconductor material, particularly a silicon wafer.
Accordingly, an object of the present invention is to provide a method of fabricating a semiconductor power component, particularly a thyristor or gridistor, by introducing into a semiconductor substrate, particularly a silicon wafer, burried grid structure, and using a metallic grid mask, characterized in that the buried grid structure is reproduced directly within the semiconductor substrate by contradoping ion implantation through the metallic grid mask, by a high energy accelerator.
This requires a single masking step, namely the etching of a metallic grid mask out of a metallic layer covering an oxide surface of the semiconductor material. Due to the inventive contradoping ion implantation through the metallic grid mask, a buried grid can be formed directly within the semiconductor material. The mask permits an ion implantation only between the bars of the metallic grid. Since the grid is to be produced at a depth of more than 10 μm, preferably more than 50 μm, the use of a high energy accelerator of the 100 MeV range is necessary.
The wire thickness in the depth direction, i.e. in the direction of implantation, of the buried grid is determined by the physical limits of the half-value width of the ions, as has been described in German Pat. No. P 33 23 672.0 of July 1, 1983. The lateral wire thickness must be determined by a definite metallic grid mask. The problems arising in this regard are the accuracy of the metallic grid mask, and the looping of the grid wires to an outer contact for the control electrode. It must be taken into account that the lateral spacing in the grid must not exceed the value of twice the space charge zone obtained by an applied typical blocking voltage. Depending on the doping and voltage, these values are in the 10 μm range. At the same time, the thickness or depth of the bars of the mask must substantially exceed the penetration depth of the ions into the mask (which latter typically lies at 100 μm). Also, the grid mask must be rectangular exactly enough to eliminate half-shadow effects, and thus avoid short circuiting. Such masks having a mask depth-to-grid spacing ratio larger than 10 cannot be produced in practice. To overcome these problems, a vertical separation in addition to the lateral one, and beveling of the semiconductor wafer has been considered.
Consequently, the material thickness of the gride mask is selected to permit the ion to become implanted in the semiconductor substrate also through the bars of the grid mask so that two buried grid structures are produced in the semiconductor substrate which are vertically spaced from each other and laterally offset relative to each other. The peripheral edge of the semiconductor substrate is beveled at an acute angle measured from a top plane thereof and the control/switch electrodes formed on the underside of the semiconductor substrate. The ion implantation simultaneously produces buried conductive structures which extend parallel to the bevels, between the buried grid structure and the control/switch electrode. The bevel angle is 10° to 60°, preferably 10° to 30°. Tests with a similar system of SiO2 with masks have shown that the separation in depth of the two buried gride structures has the desired dimension, namely within the detection limit of 4 μm. No short circuiting may therefore be expected between the two buried grid structures. The fabrication of a corresponding metallic grid mask is practicable without difficulties. To produce a semiconductor power component, particularly a gridistor, in accordance with the invention, a single masking step, and a beveling operation, are needed, so that the fabrication is very simple. At the same time, a self-adjusting connection to the control electrode is produced.
A further object of the invention is to provide a semiconductor power component, particularly a thyristor or gridistor, which comprises a buried grid structure and a control electrode which is conductively connected to the buried grid structure. The peripheral edge of the semiconductor substrate is beveled at an acute angle with respect to a top surface thereof and a control/switch electrode is provided on the underside of the semiconductor substrate. Two buried grid structures are provided in the semiconductor substrate which are vertically separated from each other and laterally offset relative to each other. The two buried grid structures are connected to the control/switch electrode by conductive structures which extend within the semiconductor substrate parallel to the beveled edge.
A still further object of the invention is to provide a method of fabrication which is simple, effective and economical, while providing a semiconductor component which is simple in design, rugged in construction and economical to manufacture.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descriptive matter in which preferred embodiments of the invention are illustrated.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following the inventive method and device is explained in more detail with reference to an embodiment of a gridistor shown in the drawings in which:
FIGS. 1 to 4 are sequential vertical sectional view of the power device during the various steps of the process;
FIG. 5 is an enlarged partial view of the device during the ion implantation through a metallic grid mask, effected to produce two buried grid structures; and
FIG. 6 is a perspective view of a semiconductor power device during the ion implantation of a single grid structure with the use of a metallic grid mask of large thickness or depth.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to the drawings in particular, the invention illustrated and embodied therein includes a method of fabricating a power component shown sequentially in FIGS. 1, 2, 3 and 4, as well as a power component partially illustrated in FIGS. 5 and 6.
The n- doped starting material or semiconductor substrate 1 shown in FIG. 1 is silicon doped with phosphorus at a concentration of 1013 /cm3. The starting material is a cylindrical wafer having a diameter of 3/4 of an inch (19 mm) and a thickness of about 900 μm. In the central area of the underside or under surface 2, and over the entire topside or top surface 3, n+ contacts with a concentration of 1019 /cm3 and a penetration depth of 50 to 80 μm are diffused. Along the periphery of the underside 2, a boron doped p+ contact 4 with a concentration of 1018 /cm3 to 1019 /cm3 and in the shape of a ring is established by diffusion. The next operation is metallizing of the top side 3 by vapor deposition, i.e. coating with a 50 to 100 μm metallic layer 5, particularly of aluminum.
This is followed, according to FIG. 2, by beveling of the circumferential edge or side 6 at an angle α ranging between 10° and 60°, preferably 10° to 30° measured from the plane of topside 3. The beveling gives the wafer 1 the shape of a truncated cone 7. The beveling is performed on a grinding machine. The component is then coated with a photoresist layer in the μ-thickness range.
The next operation is producing of the grid pattern in metallic layer 5. To this end, as shown in FIG. 3 which is turned through 90° relative to FIG. 2, an array of strips is etched out of metallic layer 5 to form ribs 8. The spacing of the ribs and the thickness of each of the ribs (with the exception of the marginal ones near the beveled edge is 100 μm. The etching is performed in a plasm etching unit.
Finally, the next step of counterdoping ion implantation is performed according to FIG. 4 showing the wafer again turned through 90° relative to FIG. 3. To perform this step, the wafer is exposed in a high energy accelerator to a high energy ion radiation 9. The employed high energy accelerator is a Van-de-Graaf Cyclotron-Combination for heavy ions (VICKSI), operating in the range of 80 to 100 MeV and achieving an ion penetration depth of 200 μm, considering boron, as in the present example. The ion concentration is 1014 /cm2 to 1015 /cm2.
The counterdoping ion implantation produces within the semiconductor substrate 1 directly two buried grid structures 10, 11 which are vertically separated as well as laterally spaced from each other.
FIG. 5, which again is turned through 90° relative to FIG. 4, shows, in an enlarged partial sectional view of wafer 1, the individual wires or rows of each of the buried grid structures 10, 11 which extend spaced from each other in depth by a distance dS as desired, namely within the detection limit of 4 μm. The grid spacing dG corresponds to the width of ribs 8 of metallic mask 5 provided on the top of wafer 1.
The beveled edge 7 makes it possible to produce contacting connections 12, 13 between the two buried grid structures 10, 11 and the p+ doped control of switch electrode 4. These connections are formed as self-adjusted connections directly by the ions penetrating into the substrate and becoming implanted in two parallel planes.
FIG. 6 shows the use of a metallic grid mask 8' having a depth dimension tM which substantially exceeds the penetration depth of the ions into the mask. Therefore, only one buried grid structure 11' can be produced with a spacing dG corresponding to the width of a rib 8' of the mask. The ions passing through ribs 8' are stopped by the material of the ribs and become implanted in the rib as a layer 10'. However, in the following process of the wafer, this implanted ion layer 10' is etched away along with the entire mask including ribs 8'.
Accordingly, the invention is a method of fabricating a semiconductor power component from a semiconductor substrate 1, having a top surface 3, an undersurface 2 and a side surface 6, comprising: forming a metallic grid mask 5, 8 on the top surface 3 and using a high energy accelerator to bury a grid structure 10, 11 directly into the substrate through the top surface by contradoping ion implantation.
The present invention also includes the semiconductor power component itself which comprises: a semiconductor substrate 1 having a top surface 3, an undersurface 2 and a side surface 6 which is beveled at an acute angle α with respect to the top surface; a control/switch electrode 4 on the undersurface 2; two buried grid structures 10,11 each including a multitude of elements implanted in the substrate with the elements of one grid structure being vertically spaced from the elements of the other grid structure and the elements of the one grid structure being laterally spaced from the elements of the other grid structure; and a conductive structure implanted in the substrate and extending parallel to the beveled edges for connecting the control/switch electrode to the grid structures.
While specific embodimetns of the invention have been shown and described in detail to illustrate the application of the principles of the invention, it will be understood that the invention may be embodied otherwise without departing from such principles.

Claims (7)

What is claimed is:
1. A process for preparing a semiconductor power component in a body of a semiconductor substrate having a top surface, a back surface and side surfaces, comprising:
forming a control/switch electrode on the back surface of the substrate;
bevelling the side surfaces of the semiconductor substrate so that the side surfaces form an acute angle with respect to the top surface of the semiconductor substrate;
forming a single metallic grid mask on the top surface of the semiconductor substrate, said grid mask comprising a multitude of spaced apart bars and being formed to have a thickness which is selected to permit ions irradiated by a high energy accelerator to pass through the top surface of the substrate both between the bars and through the bars of said grid mask; and
burying by counterdoping, two grid structures which each have elements that are vertically spaced from each other and laterally offset relative to each other, directly into the substrate through the top surface using a high energy accelerator, said burying of said grid structures being through said mask to form a shallower one of said grid structures and through spaces between said mask to form a deeper one of said grid structures, said burying also implanting conductive structures through the bevelled side surfaces, which conductive structures extend parallel to the bevelled surfaces and function to connect the control/switch electrode to the buried grid structures.
2. A process according to claim 1, wherein the high energy accelerator is operated in the 80 to 100 MeV range.
3. A process according to claim 1, wherein a penetration depth of ions to bury the grid structures exceeds 10 μm.
4. A process according to claim 2, wherein a penetration depth of ions for burying the grid structures exceeds 50 μm.
5. A process according to claim 1, including burying said grid structures by operating the high energy accelerator at 80 to 100 MeV, a penetration depth of ions of the accelerator exceeding 50 μm, the material and the thickness of the grid mask being selected to permit ions to become implanted in the semiconductor substrate through the bars of the grid mask so that the two buried grid structures are produced in the semiconductor substrate which are vertically spaced from each other and laterally offset relative to each other.
6. A process according to claim 1, wherein the acute angle is between about 10° and 60°.
7. A process according to claim 5, wherein said bevelling of the side surfaces of the semiconductor substrate forms an acute angle of from 10° to 30°.
US06/699,018 1984-02-08 1985-02-07 Forming deep buried grids of implanted zones being vertically and laterally offset by mask MEV implant Expired - Fee Related US4663830A (en)

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US6168983B1 (en) * 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
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EP0153902A2 (en) 1985-09-04
IL74217A0 (en) 1985-05-31
JPS60189263A (en) 1985-09-26
CA1226968A (en) 1987-09-15
DE3404834C2 (en) 1989-05-18
EP0153902A3 (en) 1987-08-19
DE3404834A1 (en) 1985-08-08
IL74217A (en) 1988-07-31

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