US4521866A - Distributed arithmetic oversampling recursive digital filter - Google Patents

Distributed arithmetic oversampling recursive digital filter Download PDF

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US4521866A
US4521866A US06/293,606 US29360681A US4521866A US 4521866 A US4521866 A US 4521866A US 29360681 A US29360681 A US 29360681A US 4521866 A US4521866 A US 4521866A
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Jean-Pierre Petit
Xavier Maitre
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0238—Measures concerning the arithmetic used
    • H03H17/0241—Distributed arithmetic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/04—Recursive filters
    • H03H17/0416—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0427—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0438—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
    • H03H17/0444—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation

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  • the present invention relates to a distributed arithmetic oversampling recursive digital filter. In general terms, it is used in the processing of signals and more particularly in telecommunications.
  • undersampling and oversampling digital filters are used. These are filters for which the sampling frequency of the input signals f E and that of the output signals f S are not identical. For undersampling we obtain f E >f S and for oversampling f E ⁇ f S .
  • FIG. 1 shows the organization of such systems. They comprise a coding chain and a decoding chain.
  • the coding chain is constituted by an analog input EA, an RC type filter 1, a double integration delta-sigma coder 2 operating for example at 2048 kHz and supplying one-bit signals at 2048 kHz, a triangular undersampling digital filter 3 supplying 13-bit signals at 16 kHz, and undersampling digital filter 4 supplying 13-bit signals at 8 kHz, a circuit 5 for compressing the linear law into law A, whose digital output SN supplies 8-bit signals at 8 kHz.
  • the decoding chain comprises a digital input EN, a circuit 6 for extending law A towards the linear law, an oversampling digital filter 7 operating at 32 kHz and supplying 13-bit signals at 32 kHz, a double integration delta-sigma decoder 8 operating at 2048 KHz and supplying 1-bit signals at this frequency and finally an RC type filter 9, whose output SA supplies the restored analog signal.
  • the digital values given are only of an exemplary nature.
  • the present invention again takes up the idea of the distributed arithmetic recursive filter, but provides an improvement in that by a careful adaptation of the circuits inherent in distributed arithmetic and circuits which permit oversampling, it is possible to bring about a by no means negligible saving as regards the means used (particularly the number of input registers) whilst retaining a very considerable flexibility of use.
  • Recursive digital filtering is conventionally characterized by an expression of the following form: ##EQU1## in which x n-k designates the input signals of rank n-k, y n-k output signals of rank n-k reinjected at the input of the filters, a k coefficients of the non-recursive part, whose order is p, and b k coefficients of the recursive part, whose order is q, n assuming whole values and characterizing the output signal.
  • Expression (1) is a particular case of a more general expression expressing a weighted sum which can be expressed by: ##EQU2##
  • a recursive digital filter comprises p+1 inputs receiving signals x k and q inputs receiving signals y k , i.e., in all, p+q+1 inputs. It also comprises an output supplying the sequence of signals y n .
  • the invention relates to a special digital processing method called "distributed arithmetic".
  • distributed arithmetic The latter is described in U.S. Pat. No. 3,777,130 granted on Dec. 4, 1973, to A. CROISIER, D. J. ESTEBAN, M. E. LEVILION and V. RISO, entitled “Digital filter for PCM encoded signals” as well as in the article by A. PELED and B. LIU entitled “A new hardware realization of digital filters” published in the Journal “IEEE Trans. on ASSP,” Vol. ASSP-22, pp.456-462, December 1974.
  • the invention consists of forming a weighted sum of the signals expressed by the relation (2). It is assumed that u k are coded on r bits in code complement 2, but naturally other codes are also possible. The sign bit is designated u k (0) and the bits representing the absolute value of u k are designated u k (j), j being between 0 (exclusive) and r-1 (inclusive). It is then possible to write: ##EQU4## if -1 ⁇ u k ⁇ 1.
  • the term u k (j) appearing in the expression in brackets is the bit of rank j of u k and this bit can only assume the two values 0 or 1.
  • the product u 2 (j)a 2 can only assume the two values 0 and a 2 .
  • there are only four possible values for the sum of these two products namely 0, a 1 , a 2 or a 1 +a 2 . Step by step, it is possible to see that there are finally two possible values for the sum: ##EQU6##
  • Whichever of these 2 P values is to be retained for forming w j is defined by the group of p bits of rank j of the input signals, namely u 1 (j), u 2 (j) . . . u p (j).
  • the quantities w j are entered in a memory of 2 p words of m bits, if m is the number of bits necessary for expressing these partial sums.
  • the word corresponding to a particular w j is located in said memory at the address corresponding to the p bits of rank j of input signals u k .
  • the number m is determined on the basis of the constraints of the problem to be dealt with and can be deduced in two different ways, namely by truncating coefficients a k as in a conventional realization or by direct truncation of the quantities w j (but then processing is no longer strictly linear).
  • the latter method is described in the article by R. LAGADEC and D. PELLONI entitled “A model for distributed arithmetic for filters with post-quantized look-up table" published in "National Telecommunications Conference," 1977, pp.29: 3-1 to 29: 3-6.
  • the material organization of such a circuit is illustrated in FIG. 2.
  • the represented circuit comprises p series registers 10/1, 10/2 . . . 10/p of r bits receiving the p input signals, a read-only memory 20 of 2 p words of m bits, an adder-subtractor 30, a register 40 with parallel inputs and parallel outputs which can be shifted and a timing circuit or clock 50.
  • the memory has p inputs connected to the outputs of the p input registers and contains the 2 p following quantities: ##EQU8## in which ⁇ k assumes the values 0 or 1, the address of each quantity being constituted by p bits applied to the p inputs.
  • the quantities u k have a low head weight in registers 10/1 . . . 10/p.
  • the first calculated quantity is: ##EQU9## then, after shifting the register 40, we calculate: 2 -1 w r-1 , w r-2 , then the sum w r-2 +2 -1 w r-1 , then after a further shift,
  • the operation to be performed is then in accordance with relation (1) and the corresponding circuit is that of FIG. 3. It comprises a non-recursive part constituted by p+1 series registers 10/0, 10/1 . . . 10/p receiving the signals x n , x n-1 . . . x n-p and a recursive part constituted by q registers 11/1, 11/2 . . . 11/q receiving the signals y n-1 , y n-2 . . . y n-q register 11/1 having parallel loading and the other registers series loading.
  • the output of registers 10/0 to 10/p-1 is connected to the input of the following register, in the same way as registers 11/1 to 11/q-1.
  • the circuit then comprises a memory 20 with p+q+1 inputs connected to the output of the registers, said memory containing 2 p+q+1 words of m bits, said words being the quantities: ##EQU10## in which ⁇ j are equal to 0 or 1, j passing from 1 to p+q+1.
  • the circuit comprises the aforementioned arithmetic processing members, namely an adder-subtractor 30, an accumulator register 40 with parallel inputs and parallel outputs, and a clock 50 ensuring the appropriate performance of the operations (shift of registers, loading of parallel registers, resetting of the accumulator at the end of the cycle).
  • register 11/1 corresponding to y n-1 has parallel loading and the content of the parallel-parallel register 40 must be limited to r bits (by truncating or rounding off) and then, at the end of each cycle of calculations (r elementary operations), loaded into register y n-1 in a parallel manner,
  • the invention is based on a certain number of properties exhibited by recursive filters when using distributed arithmetic. These properties have can be summarized as follows.
  • the output signals y n are sampled at a frequency n times higher than the input signals x n .
  • the calculation of the expression: ##EQU11## then has special features, because the samples x n-k will be zero (N-1) times out of N, whilst the samples y n-k will always be present.
  • index n is a multiple of N.
  • the first summation involves the coefficients a 0 , a 1 , a 2 . . . a p and the samples x tN , x tN-1 , x tN-2 . . .
  • the first summation only involves certain of these products.
  • the summation only contains the terms a 0 x t4 , a 4 x t4-4 . . .
  • everything takes place as if it were an ordinary filter with the set of coefficients a 0 , a 4 . . . (whereby the index naturally may not exceed the order p of the non-recursive part).
  • Table I gives the different input samples x n-k (the non-zero samples being underlined) in the case where the oversampling factor N is equal to 4 for the four values of j.
  • This example corresponds to the case illustrated in FIG. 1, where the sampling frequencies are respectively equal to 32 kHz and 8 kHz at the output and input.
  • the sets of coefficients to be taken into consideration for each value of j (therefore, of n) are indicated at the bottom of each column. There are four different sets and in general terms N.
  • K The order p is still between two successive multiples of N designated (K-1)N and KN with possible equality for the first.
  • the N different sets of coefficients which are to be used in turn when rank n varies are stored in N (in this case 4) blocks of the memory, said blocks having the same size and being addressed in turn in accordance with the value of N.
  • This addressing is obtained by a modulo N counter which receives the control pulses at frequency f S and whose outputs are connected to the addressing inputs of the memory.
  • the counter in question comprises ⁇ outputs and the memory comprises ⁇ addressing inputs of the N memory blocks.
  • said memory must comprise K inputs corresponding to the K series registers of the non-recursive part and also q inputs corresponding to the q registers of the ordinary recursive part.
  • the memory has ⁇ +K+q addressing inputs and a capacity of 2.sup. ⁇ +K+q words of m bits.
  • the invention can be defined in the following way. It relates to a distributed arithmetic oversampling recursive digital filter comprising a recursive part of order q constituted by a register with parallel loading and q-1 series registers, this q registers being of a circulating nature, i.e., connected in cascade; a non-recursive part of order p constituted by series registers; a memory divided into N memory blocks each containing a set of three calculated quantities characterizing the filtering to be carried out; a modulo N counter with ⁇ outputs, the memory having, on the one hand; ⁇ addressing inputs of the different blocks connected to the ⁇ outputs of the counter and, on the other hand, addressing inputs within a block connected to the outputs of the registers of the recursive and non-recursive parts; an adder-subtractor connected to the memory; an accumulator register whose input is connected to the adder-subtractor and to the output of the parallel loading register and
  • switching means able to make these K registers recirculating, i.e., looped onto themselves, N-1 times out of N and circulating, i.e., interconnected in cascade, time out of N, these switching means being controlled by the outputs of the counter.
  • the switching means are constituted by K multiplexers with two signal inputs and one output and a control input connected to the counter.
  • multiplexers can be inserted between the memory and the registers in order to reduce the size of the memory.
  • the invention provides a multiplexing of certain input registers with the outputs of the counter, making it possible to optimize the use of the memory.
  • FIG. 1 shows the coding chain and decoding chain of a coding-decoding-filtering system of the PCM type.
  • FIG. 2 shows a prior art embodiment of a distributed arithmetic processing circuit.
  • FIG. 3 shows a prior art embodiment of a recursive digital filter.
  • FIG. 5 shows a constructional variant of the above filter using multiplexers with two inputs located between the registers and the memory.
  • FIG. 6 another variant of the aforementioned filter using multiplexers with four inputs.
  • FIGS. 7 and 7a show a variant making it possible to optimize the filling of the memory when the oversampling factor is not a power of 2.
  • FIG. 8 shows another constructional variant of the above filter corresponding to the case when the oversampling factor N is not a power of 2 and when a supplementary register multiplexed with one of the outputs of the counter is used.
  • the filter comprises a recursive part constituted by a parallel loading register 11/1 and 5 series registers 11/2, 11/3 . . . 11/6, all of these registers being circulating, i.e., connected in cascade to one another, and a non-recursive part constituted by two series registers 10/1 and 10/2, each associated with a multiplexer having two inputs 12/1 and 12/2.
  • the filter also comprises a memory 20 divided into four memory blocks of the same size, each containing a set of precalculated quantities characteristics of the filtering to be performed and a modulo 4 counter 25 with two outputs ⁇ 0 and ⁇ 1 .
  • Memory 20 has, on the one hand, two addressing inputs f 0 , f 1 of four blocks, these inputs being connected to the two outputs of the counter and said on the other hand 8, addressing inputs e 1 , e 2 . . . e 8 of one word within a block, these inputs being connected to the outputs of 8 registers of the recursive and non-recursive parts.
  • the filter also comprises in a known manner an adder-subtractor 30 and an accumulator register 40, whose output is connected to the parallel loading register 11/1.
  • a clock 50 actuates the registers of the non-recursive and recursive parts at frequency rf S (in each case, r is the number of bits of the processed signal as well as counter 25 and the parallel loading of register 11/1 at frequency f S .
  • the switching means which are able to make the two registers 10/1 and 10/2 recirculating, i.e., looped on themselves three times out of four, and circulating, i.e., interconnected in cascade once out of four, are constituted by the two multiplexers 12/1 and 12/2 and by the NAND gate 13 with two inputs connected to the outputs ⁇ 0 and ⁇ 1 of counter 25.
  • Each multiplexer has two signal inputs m 1 and m 2 , an output m 3 and a control input m 4 .
  • the second input m 2 of each multiplexer is connected to the output of the series register with which it is associated, the first input m 1 being connected to the output of the preceding register, except in the case of the first 12/1, whose input is connected to a general input of the signals to be processed.
  • the control input of the multiplexers is connected to the output of the NAND gate. It is therefore at state 0 only when the two outputs ⁇ 0 and ⁇ 1 are at 1 or in other words when the counter content is at its maximum (N-1 on counting from 0 to N-1, N on counting from 1 to N).
  • the output m 3 of each multiplexer is then connected to the first input m 1 , making the two registers 10/1 and 10/2 circulating. In the three other cases, the output of the NAND gate is at 1 and output m 3 is connected to the second input m 2 , which makes the two registers recirculating.
  • the two possible solutions are either to only effect multiplexing on the (K+q) inputs of the memory connected to the registers or to repeat, if necessary, the ⁇ bits obtained at the output of the counter in such a way that for each x n-k selected by a multiplexer, the ⁇ bits of the counter are also selected.
  • These multiplexers are controlled by a modulo 2 counter 27 working at the frequency 2rf S and which supplies a bit S equal to 0 or 1.
  • Memory 20 then has 6 inputs, respectively, E 1 to E 6 . When S is at 0, these inputs are respectively connected to ⁇ 0 , ⁇ 1 , 10/1, 10/2, 11/6 and 27. When S is at 1, they are connected to 11/5, 11/4, 11/3, 11/2, 11/1 and 27.
  • Three multiplexers 28/1, 28/2 and 28/3 are controlled by a modulo 4 counter 29 with two outputs ⁇ 0 and ⁇ 1 .
  • the memory comprises 2 inputs g 0 and g 1 connected to the outputs of the modulo 4 counter 29 and three inputs F 1 , F 2 , F 3 .
  • the correspondence between the bits supplied by counter 29 and the elements to which the three inputs F 1 to F 3 are connected is as follows:
  • the invention provides for a special arrangement making it possible to optimize the filling of the memory.
  • N differs from 2.sup. ⁇
  • the sequence of samples involved in the summation of the non-recursive part has special features.
  • the number of non-zero x k involved in the summation on k is equal to 2, except on one occasion when it is equal to 3. It is easy to see that in general terms the number of non-zero x k is equal to k or K+1 in which K is defined by the aforementioned inequality:
  • the memory is not then addressed at the same time with the bit which is liable to be non-significant and with the content of the supplementary register and is instead addressed with either the first (when it is significant) or the second (when the bit in question is not significant), making it possible to optimize the use of this memory.
  • FIG. 7a shows the solution consisting of using three series registers 10/1, 10/2, 10/3 associated with their respective multiplexers 12/1, 12/2, 12/3 as described hereinbefore (the auxiliary means are not shown so as to simplify the drawings). These three registers are connected to three addressing inputs e 7 , e 8 and e 9 of memory 20. In addition, the two outputs ⁇ 0 and ⁇ 1 of counter 25 are connected to the two memory inputs f 0 and f 1 . As stated hereinbefore, when ⁇ 1 is at 1, ⁇ 0 is not significant, so that then the memory 20 is poorly used. To obviate this, the variant as shown in FIG. 7b is used, which differs from that of FIG.
  • Input 31/1 is connected to the supplementary series register 10/3, input 31/2 to output ⁇ 0 of counter 25, output 21/3 to an input (f 0 /e 9 ) of the memory, and control input 31/4 to the counter output ⁇ 1 .
  • input (f 0 /e 9 ) of the memory is connected either to the supplementary register 10/3 when bit ⁇ 0 is not significant or to output ⁇ 0 when the bit which it supplies is significant.
  • This arrangement can be used in the same way when the multiplexing factor M of the multiplexers (like 26/1 to 26/5 in FIG. 5 or 28/1 to 28/3 in FIG. 6) is not equal to a power of 2.
  • those bits supplied by counter 29 which may not be significant are multiplexed with inputs connected to registers.
  • Counters 25 and 29 are then modulo 3, and bits ⁇ 0 and ⁇ 0 are not significant when ⁇ 1 and ⁇ 1 are at 1.
  • the multiplexers with three inputs are in reality obtained by two multiplexing stages with two inputs, respectively, 34/1, 34/2, 34/3 and 36/1, 36/2, 36/3.
  • Register 10/3 is multiplexed by the least significant bit ⁇ 0 of counter 25.
  • the convention adopted for the multiplexers is that already used, namely that the upper input is connected to the output when the control signal is at 1.
  • the use of multiplexers multiplies by 3 the calculating frequency.

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FR8018579A FR2495857B1 (fr) 1980-08-27 1980-08-27 Filtre numerique recursif de surechantillonnage en arithmetique distribuee

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US4791596A (en) * 1984-07-25 1988-12-13 Ant Nachrichtentechnik Gmbh Method of linear filtering
US4811262A (en) * 1986-09-19 1989-03-07 Rockwell International Corporation Distributed arithmetic realization of second-order normal-form digital filter
US4928258A (en) * 1989-05-08 1990-05-22 The United States Of America As Represented By The Secretary Of The Air Force Recursive median filtering
US4953118A (en) * 1987-02-19 1990-08-28 Ant Nachrichtentechnik Gmbh Nonrecursive half-band filter
US5191547A (en) * 1989-08-18 1993-03-02 Mitsubishi Denki Kabushiki Kaisha Decimating digital finite impulse response filter
US5258940A (en) * 1992-03-16 1993-11-02 International Business Machines Corporation Distributed arithmetic digital filter in a partial-response maximum-likelihood disk drive system
JP2522899B2 (ja) 1992-09-30 1996-08-07 インターナショナル・ビジネス・マシーンズ・コーポレイション 等化調整方法
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US8230482B2 (en) 2000-03-09 2012-07-24 Pkware, Inc. System and method for manipulating and managing computer archive files
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RU2579982C2 (ru) * 2014-08-06 2016-04-10 Закрытое акционерное общество "Гранит-7" Способ цифровой рекурсивной полосовой фильтрации и цифровой фильтр для реализации способа

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Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791596A (en) * 1984-07-25 1988-12-13 Ant Nachrichtentechnik Gmbh Method of linear filtering
US4811262A (en) * 1986-09-19 1989-03-07 Rockwell International Corporation Distributed arithmetic realization of second-order normal-form digital filter
US4953118A (en) * 1987-02-19 1990-08-28 Ant Nachrichtentechnik Gmbh Nonrecursive half-band filter
US4928258A (en) * 1989-05-08 1990-05-22 The United States Of America As Represented By The Secretary Of The Air Force Recursive median filtering
US5191547A (en) * 1989-08-18 1993-03-02 Mitsubishi Denki Kabushiki Kaisha Decimating digital finite impulse response filter
US5258940A (en) * 1992-03-16 1993-11-02 International Business Machines Corporation Distributed arithmetic digital filter in a partial-response maximum-likelihood disk drive system
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FR2495857A1 (fr) 1982-06-11
EP0047199B1 (fr) 1984-10-17
JPH0235493B2 (fr) 1990-08-10
EP0047199A2 (fr) 1982-03-10
EP0047199A3 (en) 1982-03-17
FR2495857B1 (fr) 1987-11-27
DE3166715D1 (en) 1984-11-22
JPS5773515A (en) 1982-05-08

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