New! View global litigation for patent families

US4517583A - Semiconductor integrated circuit including a fuse element - Google Patents

Semiconductor integrated circuit including a fuse element Download PDF

Info

Publication number
US4517583A
US4517583A US06657478 US65747884A US4517583A US 4517583 A US4517583 A US 4517583A US 06657478 US06657478 US 06657478 US 65747884 A US65747884 A US 65747884A US 4517583 A US4517583 A US 4517583A
Authority
US
Grant status
Grant
Patent type
Prior art keywords
circuit
drain
fuse
formed
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US06657478
Inventor
Yukimasa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor integrated circuit includes a transistor element, an insulating layer formed adjacent to the transistor, and a wiring connected to the transistor element at one end thereof and having a fuse as a part thereof. The wiring is made of monocrystalline silicon and formed on the insulating layer providing a substantially constant burn out current value for the fuse, and thus highly reliable operation of the circuit.

Description

This application is a continuation, of application Ser. No. 351,280, filed Feb. 22, 1982, now abandoned.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuit provided with a fuse.

The density of the semiconductor integrated circuit is continuously being increased and therefore the size of the chip employed is also continuously being enlarged. This makes it difficult to enable all of circuits on a chip to be operated without failure. A semiconductor integrated circuit provided with a fuse has been developed to overcome this problem. Degraded circuit or bit portions are removed by burning out the fuse with the current, and redundant circuits or bits are added to compensate for the degraded circuit or bit portions which are removed.

There has also been developed a PROM (programmable read only memory) in which data is written by burning out the fuse.

A fuse consisting of polycrystalline silicon is employed in conventional semiconductor integrated circuits. Polycrystalline silicon is very sensitive to change and the grain size varies readily upon a slight change in its manufacturing conditions. The variation of the grain size causes the current value for burning out the fuse to become irregular and therefore program error frequently occurs. These conventional semiconductor integrated circuits therefore have low reliability.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a semiconductor integrated circuit provided with a fuse which causes no irregularity in the current value required to burn out the fuse.

In order to achieve this object, monocrystalline silicon wiring provided with a fuse is formed on an insulating layer with one end thereof connected to a transistor element.

The semiconductor integrated circuit thus arranged enables consistent, stable burn out of the fuse, thus allowing the program to be carried out with high reliability. This semiconductor integrated circuit can therefore be used as a relief circuit for degraded decoder circuit, line and column.

BRIEF DESCRIPTION OF THE DRAWINGS

This and other objects as well as merits of the present invention will become apparent from the following detailed description with reference to the accompanying drawings, in which like reference characters designate same or similar parts and wherein:

FIG. 1 is a partial plan view showing a first embodiment of a semiconductor integrated circuit according to the present invention;

FIG. 2 is a sectional view taken along a line II--II in FIG. 1;

FIG. 3 is a partial plan view showing a second embodiment of a semiconductor integrated circuit according to the present invention;

FIG. 4 is a sectional view taken along a line IV--IV in FIG. 3;

FIG. 5 is a partial plan view showing a third embodiment of a semiconductor integrated circuit according to the present invention;

FIG. 6 is a sectional view taken along a line VI--VI in FIG. 5; and

FIG. 7 shows a spare decoder circuit to which the present invention is applied to relieve a degraded one.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to FIGS. 1 and 2 thereof, the first embodiment of a semiconductor integrated circuit according to the present invention will now be described in detail.

An n+ -type source region 12 and an n+ -type drain region 14 are formed on a monocrystalline sapphire substrate 10, the regions 12 and 14 being separated from each other and made of monocrystalline silicon. A p-type monocrystalline silicon base 16 in which a channel is formed is arranged between the source region 12 and the drain region 14. A gate electrode 20 consisting of polycrystalline silicon, for example, is arranged on the monocrystalline silicon base 16 with a gate insulating film 18 interposed therebetween. The source region 12, drain region 14, monocrystalline silicon base 16, gate insulating film 18 and gate electrode 20 form a MOS transistor 22.

Arsenic concentration in n+ -type source and drain regions 12 and 14 is 1020 cm-3, and boron concentration in the p-type base 16 is 1×1016 cm-3. A monocrystalline silicon drain wiring 26 having a narrow fuse portion 24 as a part thereof is arranged on the sapphire substrate 10 and connected integral to the drain region 14. An SiO2 film 28 is coated on the MOS transistor 22 and drain wiring 26. The source region 12, drain region 14, base 16 and drain wiring 26 are formed by a single monocrystalline silicon layer 30 formed 0.4 μm thick, for example, on the sapphire substrate 10. The fuse portion 24 of drain wiring 26 is formed 1 μm wide, for example.

The monocrystalline silicon layer 30 can be formed by vapor-phase epitaxial method on the sapphire substrate 10. A polycrystalline silicon layer may be deposited on the sapphire substrate 10 and irradiated by an energy beam such as laser beam or electron beam to monocrystallize the polycrystalline silicon layer using the sapphire substrate 10 as a crystallizing nucleus. The monocrystalline silicon layer 30 thus formed is patterned by photoetching to form the source region 12, drain region 14, monocrystalline silicon base 16 and drain wiring 26.

In the case of the MOS integrated circuit thus formed according to the present invention, the n+ -type monocrystalline silicon drain wiring 26 having the narrow fuse portion is connected to the drain region 14 of MOS transistor 22. Large current density is needed to burn out the fuse portion. When impurity concentration is the same, monocrystalline silicon can be made lower in resistance as compared with polycrystalline silicon and is therefore more suitable for use as a fuse. In addition, monocrystalline silicon has no grain boundary, thus reducing the irregularity of the current value necessary for burning out the fuse portion. Therefore, the fuse can be burned out reliably and, as a result, the occurrence of defective programs can be reduced. When the sheet resistance of drain wiring 26 is set several tens Ω/□ to several hundreds Ω/□, the monocrystalline silicon fuse 24 can be reliably and consistently burned out by a substantially constant current value of several mAs.

Since the drain wiring 26 is connected integral to the drain region 14 of MOS transistor 22, the number of manufacturing processes can be reduced and the enhancement of integration can be achieved. In addition, the integral connection between the drain wiring 26 and the drain region 14 can prevent the fusing characteristic of the fuse from being influenced by contact resistance at the connected portion.

Further, since it is formed flat, the drain wiring 26 is not broken off.

The gate electrode 20 may be made of molybdenum silicide, refractory metal silicide, refractory metal, aluminum or other alloys.

The monocrystalline silicon layer 30 may be formed on a spinel substrate.

A second embodiment of a semiconductor integrated circuit according to the present invention will be now described referring to FIGS. 3 and 4.

An n+ -type source region 34 and an n+ -type drain region 36 are formed in a p-type semiconductor substrate 32. A gate electrode 40 is formed on the semiconductor substrate 32 with a gate insulating film 38 interposed therebetween. The source region 34, drain region 36 and gate electrode 40 form a MOS transistor 42.

An SiO2 film 44 is formed on the MOS transistor 42. A MOS transistor 22 and a drain wiring 26 having a fuse portion 24 are formed on the SiO2 film 44, as in the case of the first embodiment. Since the MOS transistor 22 and drain wiring 26 are the same as those in the first embodiment, the same parts are represented by the same reference numerals and a description of these parts will be omitted.

Further, with respect to the second embodiment, the drain wiring 26 consisting of monocrystalline silicon is formed on the SiO2 film 44. Another MOS transistor 42 is formed underneath the SiO2 film 44. In the case of forming the semiconductor integrated circuit in this multilayer construction, the number of necessary manufacturing processes can be reduced to increase manufacturing efficiency by forming the drain wiring 26, including the fuse portion 24, integral to the drain region 14 using a monocrystalline silicon layer 30.

In the embodiment described above, the fuse portion 24 is formed on the SiO2 film 44. However, the fuse portion 24 may also be formed on another insulator such as Si3 N4.

A third embodiment of the semiconductor integrated circuit according to the present invention will now be described by referring to FIGS. 5 and 6.

An n+ -type source region 12 and n+ -type drain region 14 are formed in a semiconductor substrate 46 consisting of p-type monocrystalline silicon. On that portion of the substrate which lies between a source region 12 and a drain region 14 and where a channel is formed, a gate electrode 20 is formed with a gate insulating film 18 interposed therebetween. The drain wiring 26 made of monocrystalline silicon is connected to the drain region 14. This drain wiring 26 has a narrow fuse portion 24 as a part thereof and is formed on an SiO2 film 48. An SiO2 film 28 is formed on a MOS transistor 22 and drain wiring 26, the MOS transistor 22 comprising the source region 12, drain region 14 and gate electrode 20. In the SiO2 film 28 is formed a contact hole through which the drain wiring 26 is connected to an Al wiring 50.

The drain wiring 26 consisting of monocrystalline silicon may be formed as follows: a polycrystalline silicon layer is connected to the drain region 14 consisting of monocrystalline silicon; then patterned to form the drain wiring 26 consisting of polycrystalline silicon; and this drain wiring 26 is laser-annealed to monocrystal.

The SiO2 film 48 may be replaced by another insulator such as Si3 N4.

An example, in which the above-described MOS integrated circuit is applied to a spare decoder circuit, will now be described referring to FIG. 7. A load element 52 is connected between a power source terminal Vcc of 5 V, for example, and an output terminal Vout. A plurality of series circuits, each comprising a MOS transistor and a fuse, are connected between the output terminal Vout and a reference potential source Vss. The series circuit of the MOS transistor and the fuse has the same construction as those in the above-described examples.

An address signal or its complementary signal is supplied to the gate electrode of the MOS transistor. Therefore, a series circuit of a MOS transistor Q1 and a monocrystalline silicon fuse F1, a series circuit of a MOS transistor Q2 and a fuse F2, a series circuit of a MOS transistor Q3 and a fuse F3, and a series circuit of a MOS transistor Q4 and a fuse F4 are connected parallel to one another between the output terminal Vout and the reference potential source Vss. Further, an address signal line Ai and its complementary signal line Ai are connected to gate electrodes of MOS transistors Q1 and Q2, while. An address signal line Ai+1 and its complementary signal line Ai+1 are connected to gate electrodes of MOS transistors Q3 and Q4.

This spare decoder circuit is used to form a new decoder output signal Vout which compensates a poor decoder circuit. By applying current larger than a predetermined value to one of the fuses F1 and F2, which are connected in series to MOS transistors Q1 and Q2 or to one of the fuses F3 and F4, connected in series to MOS transistor Q3 and Q4 to burn out each fuse, the new decoder circuit can be formed to compensate for the poor decoder.

Leaving the fuse as it is, whereby the fuse is connected to the MOS transistor to which the same address signal as that of the poor decoder circuit is applied, would permit a current larger than the predetermined value to be supplied to the other fuses to burn them out. Poor lines or columns of the decoder circuit may be replaced by the circuit whose fuse is not burned and thereby form a circuit for correcting poor memory.

Although the n-channel MOS transistor has been described in above-mentioned examples, the present invention can be applied to the p-channel MOS transistor, as well. The drain wiring 26 having the fuse is made of p-type monocrystalline silicon in this case. The fuse may be applied to the source wiring rather than the drain wiring.

The semiconductor integrated circuit according to the present invention can also be applied to the bipolar integrated circuit in addition to the MOS integrated circuit.

Various changes and modifications can be made in view of teachings disclosed above and it should be therefore understood that the present invention can be practiced otherwise without departing from the scope of appended claims.

Claims (10)

What is claimed is:
1. A semiconductor integrated circuit comprising:
a MOS transistor element;
an insulating layer formed adjacent to said transistor element; and
monocrystalline silicon wiring formed on said insulating layer, connected to said transistor element at one end thereof, and having a fuse as a part thereof, said monocrystalline silicon wiring being integrally formed with one of the source and drain of said MOS transistor element.
2. A semiconductor integrated circuit according to claim 1, wherein said insulating layer is an SiO2 layer.
3. A semiconductor integrated circuit according to claim 1, wherein said insulating layer is made of sapphire.
4. A semiconductor integrated circuit according to claim 1, wherein said insulating layer is made of silicon nitride.
5. A semiconductor integrated circuit comprising a first semiconductor region at which a first transistor element is formed; a first insulating layer formed on said first semiconductor region; a second semiconductor region formed on said first insulating layer and at which a second transistor element is formed; a second insulating layer formed on said second semiconductor region; and monocrystalline silicon wiring formed between said first and second insulating layers, connected to said second transistor element at one end thereof, and having a fuse as a part thereof.
6. A semiconductor integrated circuit according to claim 5, wherein said first insulating layer and said second semiconductor region are alternately formed one upon the other to form a multilayer construction.
7. A semiconductor integrated circuit according to claim 5 or 6, wherein said first insulating layer is an SiO2 layer.
8. A semiconductor integrated circuit according to claim 5 or 6, wherein said first insulating layer is made of silicon nitride.
9. A semiconductor integrated circuit comprising:
a MOS transistor element;
an insulating layer formed adjacent to said transistor element; and
monocrystalline silicon wiring formed on said insulating layer, connected to said transistor element at one end thereof, and having a fuse as a part thereof, said monocrystalline silicon wiring and one of the drain and source of said MOS transistor element being integrally formed with each other on said insulating layer in the same manufacturing step.
US06657478 1981-03-03 1984-10-04 Semiconductor integrated circuit including a fuse element Expired - Lifetime US4517583A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56-30207 1981-03-03
JP3020781A JPS5846174B2 (en) 1981-03-03 1981-03-03

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US35128082 Continuation 1982-02-22

Publications (1)

Publication Number Publication Date
US4517583A true US4517583A (en) 1985-05-14

Family

ID=12297282

Family Applications (1)

Application Number Title Priority Date Filing Date
US06657478 Expired - Lifetime US4517583A (en) 1981-03-03 1984-10-04 Semiconductor integrated circuit including a fuse element

Country Status (2)

Country Link
US (1) US4517583A (en)
JP (1) JPS5846174B2 (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2206730A (en) * 1987-05-19 1989-01-11 Gazelle Microcircuits Inc Semiconductor circuit device parameter optimization
US4872140A (en) * 1987-05-19 1989-10-03 Gazelle Microcircuits, Inc. Laser programmable memory array
US5155058A (en) * 1986-11-07 1992-10-13 Canon Kabushiki Kaisha Method of making semiconductor memory device
US5389814A (en) * 1993-02-26 1995-02-14 International Business Machines Corporation Electrically blowable fuse structure for organic insulators
US5420456A (en) * 1992-04-02 1995-05-30 International Business Machines Corporation ZAG fuse for reduced blow-current application
US5428237A (en) * 1991-04-26 1995-06-27 Canon Kabushiki Kaisha Semiconductor device having an insulated gate transistor
US5661323A (en) * 1995-06-30 1997-08-26 Samsung Electrics Co., Ltd. Integrated circuit fuse programming and reading circuits
US5804878A (en) * 1992-12-09 1998-09-08 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US6064095A (en) * 1998-03-10 2000-05-16 United Microelectronics Corp. Layout design of electrostatic discharge protection device
US6238955B1 (en) * 1998-01-29 2001-05-29 Micron Technology, Inc. Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
WO2001073845A1 (en) * 2000-03-28 2001-10-04 Koninklijke Philips Electronics N.V. Integrated circuit with programmable memory element
US6323535B1 (en) * 2000-06-16 2001-11-27 Infineon Technologies North America Corp. Electrical fuses employing reverse biasing to enhance programming
WO2002043152A3 (en) * 2000-11-27 2002-09-19 Koninkl Philips Electronics Nv Poly fuse rom
WO2005008676A2 (en) * 2003-07-16 2005-01-27 Hewlett-Packard Development Company, L.P. A fuse structure
US20060273841A1 (en) * 2005-06-07 2006-12-07 International Business Machines Corporation Programming and determining state of electrical fuse using field effect transistor having multiple conduction states
US20070026579A1 (en) * 2005-07-29 2007-02-01 International Business Machines Corporation Doped single crystal silicon silicided efuse
US20070210411A1 (en) * 2006-03-09 2007-09-13 International Business Machines Corporation Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
US20070247273A1 (en) * 2006-03-09 2007-10-25 International Business Machine Corporation Electrically programmable pi-shaped fuse structures and methods of fabrication thereof
US20080050903A1 (en) * 2006-03-09 2008-02-28 International Business Machines Corporation Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof
US20080052659A1 (en) * 2006-03-09 2008-02-28 International Business Machines Corporation Electrically Programmable pi-Shaped Fuse Structures and Design Process Therefore
US20080258857A1 (en) * 2006-03-09 2008-10-23 International Business Machines Corporation Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
US20090039464A1 (en) * 2007-07-10 2009-02-12 Elpida Memory, Inc. Semiconductor device
US20090078988A1 (en) * 2007-09-21 2009-03-26 Higuchi Yuichiro Semiconductor device and method for manufacturing the same
CN100502007C (en) 2001-12-18 2009-06-17 松下电器产业株式会社 Non-volatile memory
US20120241717A1 (en) * 2009-09-04 2012-09-27 University Of Warwick Organic Photosensitive Optoelectronic Devices
US9059172B2 (en) 2013-10-25 2015-06-16 Nuvoton Technology Corporation Fuse circuit
US9331211B2 (en) * 2009-08-28 2016-05-03 X-Fab Semiconductor Foundries Ag PN junctions and methods

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01160033A (en) * 1987-12-17 1989-06-22 Toshiba Corp Semiconductor memory device
US6911360B2 (en) * 2003-04-29 2005-06-28 Freescale Semiconductor, Inc. Fuse and method for forming
JP2007134373A (en) * 2005-11-08 2007-05-31 Nec Electronics Corp Semiconductor device and fuse treatment method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3533088A (en) * 1967-10-31 1970-10-06 Rca Corp Control circuit for memory
US3584183A (en) * 1968-10-03 1971-06-08 North American Rockwell Laser encoding of diode arrays
CA902796A (en) * 1972-06-13 J. Boleky Edward Fabrication of semiconductor devices
US3699395A (en) * 1970-01-02 1972-10-17 Rca Corp Semiconductor devices including fusible elements
US3792319A (en) * 1972-01-19 1974-02-12 Intel Corp Poly-crystalline silicon fusible links for programmable read-only memories
US4017769A (en) * 1972-02-17 1977-04-12 Siemens Aktiengesellschaft Integrated circuits and method of producing the same
US4045310A (en) * 1976-05-03 1977-08-30 Teletype Corporation Starting product for the production of a read-only memory and a method of producing it and the read-only memory
GB2005078A (en) * 1977-09-30 1979-04-11 Philips Nv Programmable read-only memory cell
JPS54105988A (en) * 1978-02-07 1979-08-20 Seiko Epson Corp Semiconductor memory device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA902796A (en) * 1972-06-13 J. Boleky Edward Fabrication of semiconductor devices
US3533088A (en) * 1967-10-31 1970-10-06 Rca Corp Control circuit for memory
US3584183A (en) * 1968-10-03 1971-06-08 North American Rockwell Laser encoding of diode arrays
US3699395A (en) * 1970-01-02 1972-10-17 Rca Corp Semiconductor devices including fusible elements
US3792319A (en) * 1972-01-19 1974-02-12 Intel Corp Poly-crystalline silicon fusible links for programmable read-only memories
US4017769A (en) * 1972-02-17 1977-04-12 Siemens Aktiengesellschaft Integrated circuits and method of producing the same
US4045310A (en) * 1976-05-03 1977-08-30 Teletype Corporation Starting product for the production of a read-only memory and a method of producing it and the read-only memory
GB2005078A (en) * 1977-09-30 1979-04-11 Philips Nv Programmable read-only memory cell
JPS54105988A (en) * 1978-02-07 1979-08-20 Seiko Epson Corp Semiconductor memory device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Kokkonen et al., "Redundancy Techniques for Fast Static RAMs", 1981 IEEE-Int'l Solid State Circuits Conf. Dig. of Tech. Papers, 80-81, (Feb. 18, 1981).
Kokkonen et al., Redundancy Techniques for Fast Static RAMs , 1981 IEEE Int l Solid State Circuits Conf. Dig. of Tech. Papers, 80 81, (Feb. 18, 1981). *

Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155058A (en) * 1986-11-07 1992-10-13 Canon Kabushiki Kaisha Method of making semiconductor memory device
US4872140A (en) * 1987-05-19 1989-10-03 Gazelle Microcircuits, Inc. Laser programmable memory array
GB2206730A (en) * 1987-05-19 1989-01-11 Gazelle Microcircuits Inc Semiconductor circuit device parameter optimization
US5428237A (en) * 1991-04-26 1995-06-27 Canon Kabushiki Kaisha Semiconductor device having an insulated gate transistor
US5420456A (en) * 1992-04-02 1995-05-30 International Business Machines Corporation ZAG fuse for reduced blow-current application
US7547916B2 (en) 1992-12-09 2009-06-16 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7105898B2 (en) 1992-12-09 2006-09-12 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US20050145847A1 (en) * 1992-12-09 2005-07-07 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US6031290A (en) * 1992-12-09 2000-02-29 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US20090236607A1 (en) * 1992-12-09 2009-09-24 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US6166414A (en) * 1992-12-09 2000-12-26 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US5804878A (en) * 1992-12-09 1998-09-08 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US20040051102A1 (en) * 1992-12-09 2004-03-18 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7045399B2 (en) 1992-12-09 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7897972B2 (en) 1992-12-09 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US20040023445A1 (en) * 1992-12-09 2004-02-05 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US20070012923A1 (en) * 1992-12-09 2007-01-18 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US6448612B1 (en) 1992-12-09 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor
US8294152B2 (en) 1992-12-09 2012-10-23 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit including pixel electrode comprising conductive film
US6608353B2 (en) 1992-12-09 2003-08-19 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having pixel electrode connected to a laminate structure
US7061016B2 (en) 1992-12-09 2006-06-13 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US5389814A (en) * 1993-02-26 1995-02-14 International Business Machines Corporation Electrically blowable fuse structure for organic insulators
US5661323A (en) * 1995-06-30 1997-08-26 Samsung Electrics Co., Ltd. Integrated circuit fuse programming and reading circuits
US6300170B1 (en) 1998-01-29 2001-10-09 Micron Technology, Inc. Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
US6249037B1 (en) 1998-01-29 2001-06-19 Micron Technology, Inc. Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
US6238955B1 (en) * 1998-01-29 2001-05-29 Micron Technology, Inc. Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
US6265299B1 (en) 1998-01-29 2001-07-24 Micron Technology, Inc. Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
US6680519B2 (en) 1998-01-29 2004-01-20 Micron Technology, Inc. Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
US6064095A (en) * 1998-03-10 2000-05-16 United Microelectronics Corp. Layout design of electrostatic discharge protection device
WO2001073845A1 (en) * 2000-03-28 2001-10-04 Koninklijke Philips Electronics N.V. Integrated circuit with programmable memory element
US6323535B1 (en) * 2000-06-16 2001-11-27 Infineon Technologies North America Corp. Electrical fuses employing reverse biasing to enhance programming
WO2002043152A3 (en) * 2000-11-27 2002-09-19 Koninkl Philips Electronics Nv Poly fuse rom
CN100502007C (en) 2001-12-18 2009-06-17 松下电器产业株式会社 Non-volatile memory
US20060012458A1 (en) * 2003-07-16 2006-01-19 Leigh Stan E Fuse structure
US6960978B2 (en) 2003-07-16 2005-11-01 Hewlett-Packard Development Company, L.P. Fuse structure
US7170387B2 (en) 2003-07-16 2007-01-30 Hewlett-Packard Development Company, L.P. Fuse structure
US20050285223A1 (en) * 2003-07-16 2005-12-29 Leigh Stan E Fuse structure
US7209027B2 (en) 2003-07-16 2007-04-24 Hewlett-Packard Development Company, L.P. Fuse structure
WO2005008676A2 (en) * 2003-07-16 2005-01-27 Hewlett-Packard Development Company, L.P. A fuse structure
CN100530436C (en) 2003-07-16 2009-08-19 惠普开发有限公司 Fuse structure
WO2005008676A3 (en) * 2003-07-16 2005-04-21 Hewlett Packard Development Co A fuse structure
US7242239B2 (en) * 2005-06-07 2007-07-10 International Business Machines Corporation Programming and determining state of electrical fuse using field effect transistor having multiple conduction states
US20060273841A1 (en) * 2005-06-07 2006-12-07 International Business Machines Corporation Programming and determining state of electrical fuse using field effect transistor having multiple conduction states
US20070026579A1 (en) * 2005-07-29 2007-02-01 International Business Machines Corporation Doped single crystal silicon silicided efuse
US7382036B2 (en) 2005-07-29 2008-06-03 International Business Machines Corporation Doped single crystal silicon silicided eFuse
US7572724B2 (en) 2005-07-29 2009-08-11 International Business Machines Corporation Doped single crystal silicon silicided eFuse
US7656005B2 (en) 2006-03-09 2010-02-02 International Business Machines Corporation Electrically programmable π-shaped fuse structures and methods of fabrication thereof
US7531388B2 (en) 2006-03-09 2009-05-12 International Business Machines Corporation Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof
US7784009B2 (en) 2006-03-09 2010-08-24 International Business Machines Corporation Electrically programmable π-shaped fuse structures and design process therefore
US20080014737A1 (en) * 2006-03-09 2008-01-17 International Business Machine Corporation Electrically programmable pi-shaped fuse structures and methods of fabrication thereof
US20070247273A1 (en) * 2006-03-09 2007-10-25 International Business Machine Corporation Electrically programmable pi-shaped fuse structures and methods of fabrication thereof
US20080258857A1 (en) * 2006-03-09 2008-10-23 International Business Machines Corporation Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
US20070210411A1 (en) * 2006-03-09 2007-09-13 International Business Machines Corporation Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
US20080052659A1 (en) * 2006-03-09 2008-02-28 International Business Machines Corporation Electrically Programmable pi-Shaped Fuse Structures and Design Process Therefore
US7645645B2 (en) * 2006-03-09 2010-01-12 International Business Machines Corporation Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
US20080050903A1 (en) * 2006-03-09 2008-02-28 International Business Machines Corporation Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof
US7545253B2 (en) 2006-03-09 2009-06-09 International Business Machines Corporation Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
US20090039464A1 (en) * 2007-07-10 2009-02-12 Elpida Memory, Inc. Semiconductor device
US7821100B2 (en) * 2007-09-21 2010-10-26 Panasonic Corporation Semiconductor device and method for manufacturing the same
US20090078988A1 (en) * 2007-09-21 2009-03-26 Higuchi Yuichiro Semiconductor device and method for manufacturing the same
US9331211B2 (en) * 2009-08-28 2016-05-03 X-Fab Semiconductor Foundries Ag PN junctions and methods
US20120241717A1 (en) * 2009-09-04 2012-09-27 University Of Warwick Organic Photosensitive Optoelectronic Devices
US9059172B2 (en) 2013-10-25 2015-06-16 Nuvoton Technology Corporation Fuse circuit

Also Published As

Publication number Publication date Type
JPS57143858A (en) 1982-09-06 application
JP1215487C (en) grant
JPS5846174B2 (en) 1983-10-14 grant

Similar Documents

Publication Publication Date Title
US6713839B2 (en) Antifuse structure with low resistance
US6175138B1 (en) Semiconductor memory device and method of manufacturing the same
US5444012A (en) Method for manufacturing semiconductor integrated circuit device having a fuse element
US4507759A (en) Static memory
US5359226A (en) Static memory with self aligned contacts and split word lines
US5663589A (en) Current regulating semiconductor integrated circuit device and fabrication method of the same
US5420456A (en) ZAG fuse for reduced blow-current application
US5086331A (en) Integrated circuit comprising a programmable cell
US6693481B1 (en) Fuse circuit utilizing high voltage transistors
US5389558A (en) Method of making a semiconductor memory circuit device
US5552338A (en) Method of using latchup current to blow a fuse in an integrated circuit
US4569120A (en) Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation
US4554729A (en) Method of making semiconductor memory device
US4240092A (en) Random access memory cell with different capacitor and transistor oxide thickness
US4796074A (en) Method of fabricating a high density masked programmable read-only memory
US6741492B2 (en) Semiconductor memory device
US5303199A (en) Redundant memory device having a memory cell and electrically breakable circuit having the same dielectric film
US5920097A (en) Compact, dual-transistor integrated circuit
US4413272A (en) Semiconductor devices having fuses
US4569121A (en) Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer
US5536968A (en) Polysilicon fuse array structure for integrated circuits
US5914524A (en) Semiconductor device
US4590589A (en) Electrically programmable read only memory
US4499557A (en) Programmable cell for use in programmable electronic arrays
US4654689A (en) Structure of power supply wirings in semiconductor integrated circuit

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12