US4471419A - Circuitry and method of operation for an intermediate-like converter - Google Patents

Circuitry and method of operation for an intermediate-like converter Download PDF

Info

Publication number
US4471419A
US4471419A US06/429,867 US42986782A US4471419A US 4471419 A US4471419 A US 4471419A US 42986782 A US42986782 A US 42986782A US 4471419 A US4471419 A US 4471419A
Authority
US
United States
Prior art keywords
link
inverter
output
converter
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US06/429,867
Other languages
English (en)
Inventor
Hans-Peter Schneider
Hans-Hermann Zander
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Assigned to SIEMENS AKTIENGESELLSCHAFT, reassignment SIEMENS AKTIENGESELLSCHAFT, ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: SCHNEIDER, HANS-PETER, ZANDER, HANS-HERMANN
Application granted granted Critical
Publication of US4471419A publication Critical patent/US4471419A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/505—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/515—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/525—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency
    • H02M7/527—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency by pulse width modulation

Definitions

  • This invention relates generally to systems for operating intermediate-link frequency converters, and more particularly, to a system wherein energy is conducted in two directions via two antiparallel-connected controlled converters which are coupled to an intermediate-link converter by an inverter in a three-phase bridge circuit.
  • a known intermediate-link converter which utilizes an intermediate DC link is described in the text Thyristoren, by Heumann and Stumpe, 3rd Edition, 1974, page 198. It is often desirable to operate a frequency converter in both energy directions such that a load is supplied electrical energy from a supply voltage source, and the load may function as a generator to feedback electrical energy to the source. In this manner, electrical motors can be braked almost without loss by feeding back the energy to the supply voltage source.
  • Such energy-recovering circuits have been provided heretofore only for converters having a DC intermediate link. In such known circuits, the direction of the current in the intermediate link is preserved, and only the voltage in the intermediate link is reversed.
  • an object of this invention to provide a system for operating an intermediate-link converter wherein the antiparallel-connected rectifiers on the input side are switched over as soon as the conditions for recovery are present.
  • this invention provides a system of the type wherein an intermediate link bears an impressed voltage, and 30° after each change of the addressing combination of the switches of the inverter, the polarity of the intermediate link current is interrogated.
  • the voltage at the intermediate link is compared against a reference voltage value.
  • the rectifier of the intermediate-link converter which is connected in the feedback direction is switched on as long as the interrogated polarity of the intermediate-link current is negative, and the intermediate-link voltage is above the desired value by a fixed, predetermined amount. If these conditions are not met, the rectifier which is arranged in the feed-in direction of the intermediate-link converter is switched on.
  • a measured value for the intermediate-link current is advantageously supplied to an operational amplifier which provides at its output a desired polarity signal.
  • the measured value is conducted to the operational amplifier via a polarity interrogating stage which contains an electronic measurement value switch and a smoothing stage.
  • the electronic measurement value switch is driven by a control unit of the inverter, and the switch of the inverter is closed for a short time 30° after each change of the addressing combination. In this manner, it is ascertained whether electrical energy flows from the intermediate link into the load, or from the load into the intermediate link.
  • the output currents of the three phases of the inverters are each conducted to respective switches and, via inverters, to three further switches of a multiplexer which forms an overall measurement value for the intermediate-link current.
  • the other terminals of the switches are connected to a common output at which the desired measurement value for the intermediate-link current is provided.
  • the switches are addressed dependent upon the addressing combination of the switches in the inverter.
  • the intermediate-link current can be determined from the output currents of the inverter. This provides the significant advantage that the DC current in the intermediate link need not be measured separately. Instead, the current transformers which are customarily provided in the output circuit of the inverter can be utilized for forming a measurement value for the intermediate-link currents.
  • the rectified and filtered output voltage of the intermediate-link converter can be conducted to respective inputs of a comparator stage which delivers at its output a signal for the voltage increase as soon as the output voltage of the intermediate-link converter exceeds the desired value by a fixed amount.
  • the signal for the voltage increase can also be formed without direct measurement of the intermediate-link voltage.
  • the intermediate-link voltage is formed directly from the output voltage of the intermediate-link converter which customarily is measured anyway.
  • the antiparallel rectifiers are advantageously switched-over by feeding the polarity signal for the voltage increase to both inputs of an AND gate, the output of which is connected to a double throw switching device for the two rectifiers.
  • FIG. 1 is a block and schematic representation of an intermediate-link frequency converter which is constructed and operated in accordance with the principles of the present invention
  • FIGS. 2 and 3 are waveform timing diagrams which are useful in explaining the operation of the invention.
  • FIG. 4 is a block and schematic representation of an interrogation stage
  • FIG. 5 is a control signal diagram which is useful in explaining the operation of the embodiment of FIG. 1;
  • FIG. 6 is a block and schematic representation of an evaluation circuit.
  • FIG. 1 is a block and schematic diagram of an intermediate-link frequency converter which is operated in accordance with the principles of the invention.
  • Two antiparallel-connected controlled rectifiers 1a and 1b illustratively in a three-phase bridge circuit, are connected to a supply network having a voltage V N .
  • Rectifiers 1a and 1b are coupled to an inverter 2.
  • inverter 2 can be operated as a rectifier.
  • the designation "inverter” is retained in this description to preserve clarity and uniformity.
  • a capacitor 3 having a relatively high capacity is shunted across the output terminal of rectifiers 1a and 1b, as shown, so that an intermediate-link voltage V d is impressed thereacross.
  • a motor M is connected as a load to the three-phase AC output of inverter 2.
  • Antiparallel-connected converters 1a and 1b, as well as inverter 2 are addressed by control units 6 and 7, respectively.
  • the control units are of a known type and are described, for example, in the text Industrie-Elektronik by Ernst and Stroehle, 1973, pages 52 to 56.
  • Control unit 7 addresses inverters 1a and 1b via a double-throw switching device 8 which selects the particular one of the inverters to be addressed.
  • the line voltage V N is conducted to control unit 7 as the control variable.
  • a reference voltage V soll for inverter 2 is produced by a reference voltage generator 9, and is conducted to control unit 6. Moreover, three current transformers 10, 11, and 12 are provided with their inputs connected to control unit 6 so as to provide control unit 6 with measurement values for the output currents I L1 , I L2 , and I L3 .
  • converter 1a operates as a rectifier and converts the input AC voltage V N into a DC voltage V d in the intermediate link.
  • the DC voltage V d is again converted by the inverter 2 into a three-phase AC voltage having a variable frequency for operating the motor M.
  • the individual phase voltages of the three-phase voltage are designated V 1 , V 2 and V 3 .
  • converter 1a is therefore switched from its operation as a rectifier to converter 1b operating as an inverter only if the intermediate-link voltage V d has increased and the active component of the intermediate-link current I d has reversed its polarity.
  • the increase in the intermediate-link voltage V d is determined by comparing it with the desired value V soll for the output voltage.
  • intermediate-link voltage V d is determined indirectly from output voltages V 1 , V 2 , and V 3 of the intermediate-link converter. These output voltages are, in any event, determined for controlling the converter with voltage transformers 13, 14, and 15. These voltages agree with the intermediate-link voltage V d if switches S1 to S6 of inverter 2 assigned to the respective phase are closed, and if the voltage drop across these switches is neglected.
  • the output voltages of inverter 2 are rectified by rectifier 16 and smoothed, so that a value which corresponds to intermediate-link voltage V d in the tolerance range of interest here is present at the output of rectifier 16.
  • Comparator 4 is formed of a subtraction stage 4a and a limiting stage 4b connected thereto.
  • Subtraction stage 4a receives at an adding input thereof the intermediate-link voltage V d , and at a subtraction input thereof, the desired voltage V soll . If the intermediate-link voltage V d exceeds the desired voltage V soll by an amount which is predetermined by the limit indicator 4b, the latter delivers a signal which is conducted to a first input of an AND gate 17. Thus, the first condition for switching from converter 1a to converter 1b is determined.
  • FIG. 2 is a waveform timing diagram showing smoothened output voltages V 1 , V 2 , and V 3 , as well as intermediate-link current I d for the case of full drive of inverter 2.
  • the two electronic switches belonging to one bridge arm are switched on for a half-period, displaced in time by a half-period each.
  • the "arm" phases of the two adjacent bridge arms are displaced relative to each other always by T/3.
  • voltage V 1 for example, is equal to the intermediate-link voltage V d as long as switches S1 and S5 are simultaneously closed.
  • the voltage V 1 is zero as long as switches S1 and S2 are closed simultaneously, and the voltage is equal to the negative intermediate-link voltage V d as long as switches S2 and S4 are closed simultaneously.
  • the waveforms of voltages V 2 and V 3 are obtained analogously.
  • the intermediate-link current is a pure AC current since no active power is taken up or given off by the intermediate-link capacitor 3.
  • Current I di therefore has a sawtooth waveform with a period of T/6.
  • the derivation of this current waveform from the positions of switches S1 to S6 is described in detail in the book Edgefuehrte Thyristor-Stronrichter, (free-running thyristor converters), by Manfred Meyer, 3rd Edition, pages 197 to 199. Accordingly, such a derivation will not be explained in detail.
  • intermediate-link current I d has a positive DC component such that the curve of the waveform is shifted upward.
  • the intermediate-link current produced in this manner which occurs in motor operation of the motor M, is designated in FIG. 2 as I dm .
  • a negative DC component is added to the inductive intermediate link current I di , and the current waveform designated as I dg is produced.
  • the intermediate-link current I d is zero at this point in time for a purely inductive load.
  • this link current is positive if active power is delivered, such as by motor operation, and negative, if active power is consumed, such as by generator operation.
  • a safe criterion for the direction of the active current is available. Since the addressing combination of the switches S1 to S6 changes with the period T/6, the polarity is interrogated with this period, or six times the frequency of the output voltage of the inverter.
  • FIG. 3 shows the "on" times of switches S1 to S6, as well as the waveform of the phase voltages V 1 to V 3 , and the intermediate-link current I d .
  • These waveforms are shown for the case wherein the switches S1 to S3 are addressed by 120° blocks, i.e., with a control angle of ⁇ /3.
  • a staircase voltage waveform is obtained, wherein phase voltages V 1 to V 3 change between the full intermediate-link voltage V d , one-half the intermediate-link voltage V d , and the corresponding negative values.
  • the derivation of the phase voltages V 1 to V 3 from the switching states of the switches S1 to S3 is described in the above-mentioned text by Manfred Meyer, at pages 200 to 201. Accordingly, such a derivation will not be explained here in detail.
  • the intermediate-link current I d has a sawtooth waveform for purely inductive load.
  • the sawtooth curve is shifted by a DC component in the positive direction if the motor M takes on active load, and in the negative direction if it delivers active power.
  • the intermediate-link current I d goes through zero, for purely inductive load, 30° after each change of the switch combination of switches S1 to S6, the polarity is interrogated at a point in time t.sub. ⁇ which is always 30° after each change of the addressing combination, or with reference to the voltage waveform, 30° after each zero crossing of a phase voltage V 1 to V 3 .
  • the polarity interrogation times t.sub. ⁇ can be derived in a simple manner from inverter control unit 6.
  • the inverter control unit is constructed from a frequency generator followed by a ring counter. It is only necessary to provide additional counters, the outputs of which are programmed for the times t.sub. ⁇ .
  • the polarity is determined in the embodiment of FIG. 1 by the provision that a measuring resistor 18 which carries the intermediate-link current I d is arranged in the intermediate link. Resistor 18 is followed by a differential amplifier 18a having an output which produces a measured value for the intermediate-link current I d . This measured value is conducted to a polarity interrogation stage 5 which is controlled by inverter control unit 6. The polarity signal obtained by a polarity interrogation stage 5 is conducted to a second input of an AND gate 17, which, as already described, receives the voltage increase signal at its first input.
  • FIG. 4 is a block and schematic representation of an embodiment of a polarity interrogation stage.
  • the measured value of intermediate-link current I d is conducted via a measured value switch 5a to a smoothing stage consisting of a series resistor 5c and a shunt capacitor 5d.
  • Measured value switch 5a is switched-on by a pulse generator 5b which, as described, is triggered by the inverter control unit 6 30° after each change of the addressing combination of switches S1 to S6 of inverter 2.
  • the value of current I d is always interrogated at the time t.sub. ⁇ , where a continuous signal is obtained from the individual pulses by the smoothing stage 5c, 5d.
  • This continuous signal is inverted by inverter 5e which is followed by a limit indicator 5f which produces an output signal when the smoothed interrogation signal exceeds a predetermined negative value.
  • Limit indicator 5f provides at its output the desired polarity signal which has the value "1" if the motor M feeds back to the intermediate link. As described, an AND gate 17 is addressed by this polarity signal.
  • the determination of the current in the intermediate link is necessary for the interrogation of the polarity. Since one of the output currents I L1 to I L3 is always identical with the intermediate-link current I d , it also possible to determine the intermediate-link current I d from the output currents I L1 to I L3 by a suitable choice of the output currents. These output currents are usually measured anyhow by current transformers in the output line.
  • FIG. 5 is a control diagram for switches S1 to S6, according to FIG. 1. Since the two switches of switches S1 to S6 which are connected to a bridge arm are always driven inversely to each other, each switch combination of the six switches S1 to S6 can be completely characterized by the switch combinations, for example, illustratively of the switches S1 to S3. Each switch combination can therefore be characterized by a digital signal wherein, for example, the switching state of switch S1 represents the most significant digit, the switching state of switch S2 represents the second highest digit, and the switching state of switch S3 represents the least significant digit.
  • the binary numbers corresponding to the respective switching states of switches S1 to S6 are indicated in decimal notation.
  • the intermediate-link current I d can be determined from the output currents I L1 to I L3 in accordance with the following scheme: if switches S1 and S3 are switched on, i.e., for the addressing combination designated with 5, the intermediate-link current is equal to the negative output current I L2 , since the intermediate-link current I d is distributed over the switches S1 and S3, flows through motor M and flows back again into the intermediate link via switch S5 as current -I L2 . If only the switch S1 is switched on, i.e., the addressing combination 4 is present, the intermediate-link current I d can only flow through the switch S1 and is therefore identical with the output current I L1 , etc.
  • the intermediate-link current I d can therefore be determined from the output currents I L1 to I L3 or from their inverted values by selecting them via switches which are driven dependent upon the addressing combinations of the switches S1 to S3.
  • FIG. 6 shows an evaluation circuit constructed in accordance with the principles of the invention for determining the intermediate-link current I d .
  • the output currents I L1 , I L2 , and I L3 are conducted to the inputs of a multiplexer 19, both directly and via inverting stages 20, 21, and 22.
  • multiplexer 19 receives the output currents in inverted and noninverted forms.
  • the addressing inputs of multiplexer 19 are connected to the addressing lines of switches S1 to S3.
  • Multiplexer 19 contains six switches, 19b to 19g, via which the inputs are connected to a common output. Furthermore, a decoder 19a is provided which addresses the switches 19b to 19g with the binary number given by the addressing combination of switches S1 to S3. Decoder 19 has six outputs which are each assigned a respective one of binary numbers 1 to 6, according to FIG. 5. The output assigned to binary number 1 is connected to switch 19g, the output assigned to binary number 2 is connected to switch 19e, the output assigned to binary number 3 is connected to switch 19b, the output assigned to binary number 4 is connected to switch 19c, the output assigned to binary number 5 is connected to switch 19b, and the output assigned to binary number 6 is connected to switch 19f.
  • switch 19d for example, is addressed according to the already explained scheme, if switches S1 and S3 are closed, and therefore the inverted output current I L2 is used as the intermediate-link current Id. If only switch S1 is closed, switch 19c is closed and the output current I L1 is used as the intermediate-link current I d , etc.
  • the measured value for the intermediate-link current I d which is present at the output of multiplexer 19 is conducted to the polarity interrogator 5, according to FIG. 1.
  • the circuit of FIG. 6, therefore, allows measuring resistor 18 and differential amplifier 18a, according to FIG. 1, to be replaced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Stopping Of Electric Motors (AREA)
  • Ac-Ac Conversion (AREA)
  • Control Of Ac Motors In General (AREA)
  • Communication Control (AREA)
  • Control Of Multiple Motors (AREA)
US06/429,867 1981-10-20 1982-09-30 Circuitry and method of operation for an intermediate-like converter Expired - Fee Related US4471419A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3141621 1981-10-20
DE19813141621 DE3141621A1 (de) 1981-10-20 1981-10-20 Verfahren zum betrieb eines zwischenkreisumrichters und schaltungsanordnung zur durchfuehrung des verfahrens

Publications (1)

Publication Number Publication Date
US4471419A true US4471419A (en) 1984-09-11

Family

ID=6144489

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/429,867 Expired - Fee Related US4471419A (en) 1981-10-20 1982-09-30 Circuitry and method of operation for an intermediate-like converter

Country Status (7)

Country Link
US (1) US4471419A (enrdf_load_stackoverflow)
EP (1) EP0078923B1 (enrdf_load_stackoverflow)
JP (1) JPS5879475A (enrdf_load_stackoverflow)
AT (1) ATE17809T1 (enrdf_load_stackoverflow)
DE (2) DE3141621A1 (enrdf_load_stackoverflow)
DK (1) DK464782A (enrdf_load_stackoverflow)
IN (1) IN158420B (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642546A (en) * 1983-11-21 1987-02-10 Siemens Aktiengesellschaft Method and apparatus for operating a load supplied via an intermediate-link converter, especially an asynchronous machine, in the event of a network disturbance
US4713595A (en) * 1985-07-19 1987-12-15 Mitsubishi Denki Kabushiki Kaisha Control apparatus for elevator
US10361637B2 (en) * 2015-03-20 2019-07-23 Hubbell Incorporated Universal input electronic transformer

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207882A (ja) * 1982-05-26 1983-12-03 Fanuc Ltd 交流モ−タの回生エネルギ−処理装置
US4688163A (en) * 1986-07-01 1987-08-18 Siemens Aktiengesellschaft Method for controlling the phase angle of the output current or the output voltage of a frequency converter and apparatus for carrying out the method
DE4322379C1 (de) * 1993-06-29 1994-12-22 Licentia Gmbh Schaltungsanordnung zum Schutz der Halbleiterschalter beim Kippen einer Energie in ein Netz zurückspeisenden Netzstromrichterbrücke in einem Gleichspannungszwischenkreis-Umrichter
DE19546000A1 (de) * 1995-12-09 1997-06-12 Gegelec Aeg Anlagen Und Antriebssysteme Gmbh 4-Quadrant-Einspeisestromrichter für Pulswechselrichter
DE102006015031A1 (de) 2006-03-31 2007-10-11 Siemens Ag Verfahren zur Verringerung des Blindleistungsbedarfs eines grundfrequent getakteten netzseitigen Stromrichters im Leerlauf sowie bei geringer motorischer Belastung

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158163A (en) * 1976-10-25 1979-06-12 Danfoss A/S Inverter circuit
US4270078A (en) * 1979-04-24 1981-05-26 General Electric Company Method and apparatus for a variable frequency inverter system having commutation fault detection and correction capabilities
US4274042A (en) * 1979-04-24 1981-06-16 General Electric Company AC Motor drive system having clamped command error signal
US4328454A (en) * 1979-01-10 1982-05-04 Hitachi, Ltd. Apparatus for controlling ac motor
US4366427A (en) * 1980-04-22 1982-12-28 General Electric Company Protective method and apparatus for a controlled current inverter and motor control system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE658711A (enrdf_load_stackoverflow) * 1964-02-03 1965-05-17
DE1538153A1 (de) * 1966-03-24 1969-10-23 Siemens Ag Anordnung zur Regelung des Kreisstromes von Stromrichtern in Umkehrschaltung
DE1588783B2 (de) * 1967-09-30 1973-02-08 Siemens AG, 1000 Berlin u 8000 München Einrichtung zur steuerung eines umkehrstromrichters

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158163A (en) * 1976-10-25 1979-06-12 Danfoss A/S Inverter circuit
US4328454A (en) * 1979-01-10 1982-05-04 Hitachi, Ltd. Apparatus for controlling ac motor
US4270078A (en) * 1979-04-24 1981-05-26 General Electric Company Method and apparatus for a variable frequency inverter system having commutation fault detection and correction capabilities
US4274042A (en) * 1979-04-24 1981-06-16 General Electric Company AC Motor drive system having clamped command error signal
US4366427A (en) * 1980-04-22 1982-12-28 General Electric Company Protective method and apparatus for a controlled current inverter and motor control system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Thyristoren," by Heumann and Stumpe, 3rd Edition, 1974, p. 198.
Thyristoren, by Heumann and Stumpe, 3rd Edition, 1974, p. 198. *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642546A (en) * 1983-11-21 1987-02-10 Siemens Aktiengesellschaft Method and apparatus for operating a load supplied via an intermediate-link converter, especially an asynchronous machine, in the event of a network disturbance
US4713595A (en) * 1985-07-19 1987-12-15 Mitsubishi Denki Kabushiki Kaisha Control apparatus for elevator
US10361637B2 (en) * 2015-03-20 2019-07-23 Hubbell Incorporated Universal input electronic transformer
US11557977B2 (en) 2015-03-20 2023-01-17 Hubbell Lighting, Inc. Universal input electronic transformer

Also Published As

Publication number Publication date
IN158420B (enrdf_load_stackoverflow) 1986-11-15
EP0078923B1 (de) 1986-01-29
ATE17809T1 (de) 1986-02-15
DE3268857D1 (en) 1986-03-13
DE3141621A1 (de) 1983-05-05
DK464782A (da) 1983-04-21
JPS5879475A (ja) 1983-05-13
EP0078923A1 (de) 1983-05-18

Similar Documents

Publication Publication Date Title
US4672520A (en) Current-source power converting apparatus with self-extinction devices
US4399499A (en) Bi-lateral four quadrant power converter
EP0152796B1 (en) Control circuit for power converter apparatus
US3694718A (en) Methods of inverter voltage control by superimposed chopping
US4354223A (en) Step-up/step down chopper
US4180853A (en) Two-stage commutation circuit for an inverter
US4128793A (en) Power circuit for variable frequency, variable magnitude power conditioning system
US4471419A (en) Circuitry and method of operation for an intermediate-like converter
CN111313796B (zh) 可切换驱动模式的驱动电路、方法、变频器及设备
JPH04121065A (ja) 電力変換方法、電力変換装置およびその電力変換装置を用いた圧延システム
US3641566A (en) Frequency polyphase power supply
Khan et al. A comparative study of multilevel inverter typologies with reduced switches
US4240135A (en) Regulated cycloconverter circuit
US3539900A (en) Rectifier lockout circuit
US4247887A (en) AC--AC Converter device
SU1501234A1 (ru) Устройство дл цифрового управлени вентильным коммутатором
US5006776A (en) Gate-controlled electric drive
US4688163A (en) Method for controlling the phase angle of the output current or the output voltage of a frequency converter and apparatus for carrying out the method
US4358820A (en) Inverter with individual commutation circuit
SU1069150A1 (ru) Преобразователь кода в напр жение
US3492560A (en) Three-phase full wave rectifier for a three-phase four-wire alternating current supply
US4608626A (en) Electrical inverter with minority pole current limiting
SU584415A1 (ru) Двухтактный инвертор
SU543116A1 (ru) Устройство управлени реверсивным преобразователем
SU1422343A1 (ru) Преобразователь посто нного напр жени в трехфазное квазисинусоидальное напр жение

Legal Events

Date Code Title Description
AS Assignment

Owner name: SIEMENS AKTIENGESELLSCHAFT, MUNCHEN, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:SCHNEIDER, HANS-PETER;ZANDER, HANS-HERMANN;REEL/FRAME:004091/0790

Effective date: 19820927

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Lapsed due to failure to pay maintenance fee

Effective date: 19920913

FP Lapsed due to failure to pay maintenance fee

Effective date: 19920913

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362