US4468260A - Method for diffusing dopant atoms - Google Patents

Method for diffusing dopant atoms Download PDF

Info

Publication number
US4468260A
US4468260A US06/480,082 US48008283A US4468260A US 4468260 A US4468260 A US 4468260A US 48008283 A US48008283 A US 48008283A US 4468260 A US4468260 A US 4468260A
Authority
US
United States
Prior art keywords
silicon wafer
dopant atoms
light sources
halogen lamps
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US06/480,082
Inventor
Tatsumi Hiramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ushio Denki KK
Original Assignee
Ushio Denki KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ushio Denki KK filed Critical Ushio Denki KK
Assigned to USHIO DENKI KABUSHIKI KAISHA reassignment USHIO DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: HIRAMOTO, TATSUMI
Application granted granted Critical
Publication of US4468260A publication Critical patent/US4468260A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H01L21/2686—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation using incoherent radiation

Definitions

  • This invention relates to a method for diffusing dopant atoms such as aluminum, gallium, phosphorus or the like thermally into the interior of a semiconductor wafer of silicon.
  • the thermal diffusion technique is currently used in the fabrication of integrated circuits, large-scale integrated circuits and the like so as to form layers doped with dopant atoms.
  • the thermal diffusion technique permits to form a junction of a doped layer in a silicon wafer. It also enables to form such a junction at a greater depth of the wafer.
  • the above-described thermal diffusion method making use of a resistance furnace is superior in that a number of wafers may be subjected to a diffusion treatment at once and, because wafers are heated for a long period of time making use of the thermal conduction by means of the surrounding gas, temperature variations may be kept relatively small at various points of each wafer.
  • the above conventional method is however accompanied by such drawbacks that the wafers often develop crystal defects because they are kept for a long time period at a high temperature and wafers may develop other physical defects such as warping if they are charged or discharged at a higher speed into or from a furnace with a view toward making the treatment time shorter.
  • the diffusing temperature is said to be 1200° C. or so at most, because the heat treatment of silicon wafers is generally conducted while holding them in a container formed of a high-purity silicon glass tube and any temperatures higher than the melting point of silicon must thus be avoided.
  • Use of phosphorus as a dopant still requires a considerably long time period, i.e., 4 hours for its diffusion even if silicon wafers are heated at a treatment temperature of 1200° C.
  • the problem of developing physical defects such as warping remain unsolved even if the diffusing treatment is carried out at such a high temperature.
  • An object of this invention is accordingly to provide a novel diffusion method of dopant atoms which method does not induce warping and other physical defects of the silicon wafers and correspondingly enjoys high productivity.
  • Another object of this invention is to provide a diffusion method of dopant atoms which method requires a shorter time period but brings about a greater diffusing depth of the dopant atoms.
  • a method for diffusing dopant atoms into a silicon wafer comprises heating the entirety of said silicon wafer with said dopant atoms to a predetermined diffusing temperature in a short period of time by applying light thereonto under such conditions that the temperature difference between a central part and a peripheral part of the silicon wafer is maintained not more than 65° C. throughout the treatment, thereby causing said dopant atoms to undergo thermal diffusion into the interior of said silicon wafer.
  • the diffusion method of dopant atoms according to the present invention permits, as will be apparent from Examples which will be described later in this specification, to carry out diffusion of the dopant into silicon wafers with high productivity without inducing any physical defects such as warping and slip lines.
  • it requires a very short time period for effecting diffusion to a desired extent and it enables to make the depth of diffusion greater.
  • FIG. 1 is a schematic cross-sectional view showing an essential part of a light-heating furnace which may be used suitably in the practice of the method according to this invention.
  • FIG. 1 One embodiment of this invention will hereinafter be described with reference to the accompanying sole drawing, i.e., FIG. 1.
  • numerals 1a,1b indicate respectively upper and lower reflectors arranged in up-and-down and face-to-face relationship with an irradiation space 10 interposed therebetween.
  • the reflectors 1a,1b are provided with flow passages 2a and 2b for cooling water respectively.
  • a plurality of gutter-like grooves 3a,3b (12 grooves in the illustrated embodiment) are formed close and parallel to one another.
  • Tubular halogen lamps 4a,4b are provided in such a state that they are received in their corresponding grooves 3a,3b.
  • the halogen lamps 4a which correspond to the reflector 1a, are arranged in such a way that their filaments are positioned in a common plane and make up an upper plane light source together with their matching reflector 1a.
  • the halogen lamps 4b which correspond to the reflector 1b, lie in a common plane which is parallel to the plane in which the filaments of the above-described upper plane light source are positioned.
  • the halogen lamps 4b make up a lower plane light source together with the reflector 1b.
  • each of the halogen lamps 4a,4b is a tubular lamp having a filament which is equipped with alternating luminous parts and nonluminous parts and sealed in a sealed envelope, that are used as an exposure lamp in an electronic copying machine, for example.
  • the rated power consumption of the lamp is 2 KW.
  • Each of the upper and lower plane light sources is constructed of 12 halogen lamps 4a or 4b disposed with their longitudinal tubular axes parallel to one another. It has an area of 20 cm ⁇ 25 cm or so.
  • diffusion of dopant atoms into a silicon wafer is carried out as follows, using, for example, a light-heating furnace having such a structure as mentioned above.
  • a silicon wafer 6 to be subjected to a diffusion treatment with dopant atoms which has in advance been introduced into the silicon wafer 6 in accordance with, for instance, the ion implantation process, is supported horizontally on a wafer holder 7 disposed in a transparent container 5.
  • the transparent container 5 is inserted into the irradiation space 10 of the light-heating furnace in such a way that the upper and lower surfaces of the silicon wafer 6 confront parallelly with central regions of their corresponding upper and lower plane light sources.
  • Numeral 8 indicates a substantially annular subsidiary heater which extends along the outer circumference of the silicon wafer 6 and may be provided as needed.
  • the subsidiary heater 8 is supported by support legs 9 in the transparent container 5.
  • all the halogen lamps 4a,4b of the upper and lower plane light sources are turned on at once so that light and heat, which are emitted from the halogen lamps 4a,4b, are applied onto the upper and lower surfaces of the silicon wafer 6, whereby to heat the silicon wafer 6 under such conditions that the temperature difference between a central part 6a of the silicon wafer 6 and its peripheral part 6b (an area within several millimeters from the peripheral edge 6c) does not exceed 65° C.
  • the dopant atoms which have in advance been introduced in the silicon wafer 6 is caused to undergo thermal diffusion.
  • the surface temperature of the silicon wafer 6 can be raised to a temperature as high as 1250° C. or higher within a short period of 10 seconds. It is preferred to make the transparent container 5 and wafer holder 7 with silica glass, because the transparent container 5 and wafer holder 7 are prevented from getting hotter and the silicon wafer 6 may be heated at a faster speed, thereby making it possible to raise the temperature of the silicon wafer 6 to a high temperature of at most 1400° C. in a short period of time.
  • the silicon wafer 6 can be heated to high temperatures to cause dopant atoms to undergo diffusion thereinto without inducing any physical defects, i.e., warping or slip lines to occur.
  • the above effect of the present invention has been confirmed through experiments.
  • the following means are effective to achieve the above-described heating by radiated light while fulfilling the requirement that the temperature difference between the central part 6a of the silicon wafer 6 and its peripheral part 6b be maintained within 65° C.:
  • each of the plane light sources has an area of 20 cm ⁇ 25 cm as mentioned above and the distance between the common plane on which the filament of each of the halogen lamps 4a,4b lies and its corresponding surface of the silicon wafer 6 is for instance 4 cm, the above heating method is effective for silicon wafers having a diameter of 5 inches or smaller.
  • the provision of the subsidiary heater 8 not only reduces the radiation of heat from the peripheral part 6b of the silicon wafer 6 but also, on the contrary, applies heat to the peripheral part 6b to compensate any temperature drop at the peripheral part 6b.
  • the subsidiary heater 8 may be employed, for example, an annular halogen lamp, an annular metallic member having a high melting point which radiates heat on receiving the light or the like.
  • the above means (3) can bring about the same effects as the means (2).
  • Ion implantation into a silicon wafer was effected in the same manner as in Example 1 except that gallium ions, which had been accelerated with an energy of 350 KeV, were implanted to a concentration of 3 ⁇ 10 15 ions/cm 2 .
  • the wafer was heated to 1350° C. at its central part and 1345° C. at its peripheral part.
  • gallium atoms were caused to undergo diffusion and the depth of the junction was increased to 5 ⁇ m. No development of physical defects such as slip lines was observed.
  • a film of phosphorus trioxide having a thickness of 0.4 ⁇ m was formed on a silicon wafer of the same type as that used in Example 1.
  • the silicon wafer was exposed to light in the same manner as in Example 1, the wafer was heated to 1350° C. at its central part and 1330° C. at its peripheral part.
  • phosphorus atoms had undergone solid-phase diffusion, thereby providing a wafer having a junction formed at a depth of 5 ⁇ m with a phosphorus-doped layer. Similar results were brought about when a silicon wafer applied with a film of phosphorus glass in place of the film of phosphorus trioxide.
  • the present invention has made it possible to complete each diffusion treatment in a relatively short period of time because a silicon wafer is heated by applying light thereonto so as to diffuse dopant atoms into the interior of the silicon wafer. Since the heating of a silicon wafer is carried out in the present invention under such conditions that the temperature difference between the central part of the silicon wafer and its peripheral part does not exceed 65° C., the silicon wafer does not develop such physical defects as warping or slip lines. Accordingly, the method of the present invention can diffuse dopant atoms to a significantly greater junction depth in a shorter period of time and can fabricate doped silicon wafers with higher productivity, compared with the conventional heating method which makes use of a resistance furnace.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Dopant atoms are diffused into a silicon wafer by heating the entirety of the silicon wafer with the dopant atoms to a predetermined diffusing temperature in a short period of time, and more specifically, by applying light onto the silicon wafer under such conditions that the temperature difference between a central part of the silicon wafer and its peripheral part is maintained within 65° C. The above diffusion method permits to carry out diffusion of the dopant atoms into silicon wafers with high productivity but without inducing physical defects such as warping or slip lines. It requires a very short time period for effecting diffusion to a desired extent and it enables to make the depth of diffusion greater.

Description

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method for diffusing dopant atoms such as aluminum, gallium, phosphorus or the like thermally into the interior of a semiconductor wafer of silicon.
(2) Description of the Prior Art
The thermal diffusion technique is currently used in the fabrication of integrated circuits, large-scale integrated circuits and the like so as to form layers doped with dopant atoms. The thermal diffusion technique permits to form a junction of a doped layer in a silicon wafer. It also enables to form such a junction at a greater depth of the wafer.
As a method for causing dopant atoms to undergo thermal diffusion into the interior of a silicon wafer, it has heretofore been carried out to heat the silicon wafer with the dopant atoms in a resistive furnace. It is however necessary, according to the above conventional method, to carry out the heating of the silicon wafer at a temperature of about 1100° C. and for a time period as long as about 10 hours in order to achieve a desired level of diffusion, although the diffusing temperature and time may vary to certain extents depending on the sort of dopant atoms to be diffused. Moreover, it is also required to conduct the temperature-raising step of the silicon wafer from room temperature to a diffusing temperature where the dopant atoms are caused to undergo diffusion, and the temperature-lowering step of the same silicon wafer from the diffusing temperature to room temperature respectively before and after the diffusion treatment slowly, each, over a time period of 1 hour or longer, thereby making the overall diffusion treatment very time-consuming.
The above-described thermal diffusion method making use of a resistance furnace is superior in that a number of wafers may be subjected to a diffusion treatment at once and, because wafers are heated for a long period of time making use of the thermal conduction by means of the surrounding gas, temperature variations may be kept relatively small at various points of each wafer. The above conventional method is however accompanied by such drawbacks that the wafers often develop crystal defects because they are kept for a long time period at a high temperature and wafers may develop other physical defects such as warping if they are charged or discharged at a higher speed into or from a furnace with a view toward making the treatment time shorter.
With the foregoing in view, it may be contemplated to effect the diffusion at a higher temperature so as to shorten the treatment time. However, the diffusing temperature is said to be 1200° C. or so at most, because the heat treatment of silicon wafers is generally conducted while holding them in a container formed of a high-purity silicon glass tube and any temperatures higher than the melting point of silicon must thus be avoided. Use of phosphorus as a dopant still requires a considerably long time period, i.e., 4 hours for its diffusion even if silicon wafers are heated at a treatment temperature of 1200° C. Furthermore, the problem of developing physical defects such as warping remain unsolved even if the diffusing treatment is carried out at such a high temperature.
When increasing the depth of diffusion, for example, to 10 μm or so from the surface of a wafer by the above-described thermal diffusion method making use of a resistance furnace, it is necessary to make the diffusing temperature still higher and the treatment time still longer. The above-mentioned drawbacks become serious problems if the diffusing temperature and time are increased. Therefore, the conventional diffusion method, which uses a resistance furnace, cannot be considered as a meritorious method in view of its productivity and production yield.
SUMMARY OF THE INVENTION
The present invention has been completed taking the foregoing into consideration. An object of this invention is accordingly to provide a novel diffusion method of dopant atoms which method does not induce warping and other physical defects of the silicon wafers and correspondingly enjoys high productivity.
Another object of this invention is to provide a diffusion method of dopant atoms which method requires a shorter time period but brings about a greater diffusing depth of the dopant atoms.
In one aspect of this invention, there is thus provided a method for diffusing dopant atoms into a silicon wafer, which method comprises heating the entirety of said silicon wafer with said dopant atoms to a predetermined diffusing temperature in a short period of time by applying light thereonto under such conditions that the temperature difference between a central part and a peripheral part of the silicon wafer is maintained not more than 65° C. throughout the treatment, thereby causing said dopant atoms to undergo thermal diffusion into the interior of said silicon wafer.
The diffusion method of dopant atoms according to the present invention permits, as will be apparent from Examples which will be described later in this specification, to carry out diffusion of the dopant into silicon wafers with high productivity without inducing any physical defects such as warping and slip lines. In addition, it requires a very short time period for effecting diffusion to a desired extent and it enables to make the depth of diffusion greater.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a schematic cross-sectional view showing an essential part of a light-heating furnace which may be used suitably in the practice of the method according to this invention.
DETAILED DESCRIPTION OF THE INVENTION AND PREFERRED EMBODIMENT
One embodiment of this invention will hereinafter be described with reference to the accompanying sole drawing, i.e., FIG. 1.
In FIG. 1, numerals 1a,1b indicate respectively upper and lower reflectors arranged in up-and-down and face-to-face relationship with an irradiation space 10 interposed therebetween. The reflectors 1a,1b are provided with flow passages 2a and 2b for cooling water respectively. In the inner surface of each of the reflectors 1a,1b, a plurality of gutter- like grooves 3a,3b (12 grooves in the illustrated embodiment) are formed close and parallel to one another. Tubular halogen lamps 4a,4b are provided in such a state that they are received in their corresponding grooves 3a,3b. The halogen lamps 4a, which correspond to the reflector 1a, are arranged in such a way that their filaments are positioned in a common plane and make up an upper plane light source together with their matching reflector 1a. On the other hand, the halogen lamps 4b, which correspond to the reflector 1b, lie in a common plane which is parallel to the plane in which the filaments of the above-described upper plane light source are positioned. The halogen lamps 4b make up a lower plane light source together with the reflector 1b.
Describing the above light-heating furnace more specifically, each of the halogen lamps 4a,4b is a tubular lamp having a filament which is equipped with alternating luminous parts and nonluminous parts and sealed in a sealed envelope, that are used as an exposure lamp in an electronic copying machine, for example. In an example, the rated power consumption of the lamp is 2 KW. Each of the upper and lower plane light sources is constructed of 12 halogen lamps 4a or 4b disposed with their longitudinal tubular axes parallel to one another. It has an area of 20 cm×25 cm or so.
In the present invention, diffusion of dopant atoms into a silicon wafer is carried out as follows, using, for example, a light-heating furnace having such a structure as mentioned above. Namely, a silicon wafer 6 to be subjected to a diffusion treatment with dopant atoms, which has in advance been introduced into the silicon wafer 6 in accordance with, for instance, the ion implantation process, is supported horizontally on a wafer holder 7 disposed in a transparent container 5. Then, the transparent container 5 is inserted into the irradiation space 10 of the light-heating furnace in such a way that the upper and lower surfaces of the silicon wafer 6 confront parallelly with central regions of their corresponding upper and lower plane light sources. Numeral 8 indicates a substantially annular subsidiary heater which extends along the outer circumference of the silicon wafer 6 and may be provided as needed. The subsidiary heater 8 is supported by support legs 9 in the transparent container 5.
While holding the silicon wafer in the above-mentioned state, all the halogen lamps 4a,4b of the upper and lower plane light sources are turned on at once so that light and heat, which are emitted from the halogen lamps 4a,4b, are applied onto the upper and lower surfaces of the silicon wafer 6, whereby to heat the silicon wafer 6 under such conditions that the temperature difference between a central part 6a of the silicon wafer 6 and its peripheral part 6b (an area within several millimeters from the peripheral edge 6c) does not exceed 65° C. By the above heat treatment, the dopant atoms which have in advance been introduced in the silicon wafer 6 is caused to undergo thermal diffusion.
When heating the silicon wafer 6 in a light-heating furnace as mentioned above, the surface temperature of the silicon wafer 6 can be raised to a temperature as high as 1250° C. or higher within a short period of 10 seconds. It is preferred to make the transparent container 5 and wafer holder 7 with silica glass, because the transparent container 5 and wafer holder 7 are prevented from getting hotter and the silicon wafer 6 may be heated at a faster speed, thereby making it possible to raise the temperature of the silicon wafer 6 to a high temperature of at most 1400° C. in a short period of time.
However, if the silicon wafer 6 is heated rapidly to such a high temperature under ordinary conditions, a greater temperature difference occurs between the central part 6a and the peripheral part 6b of the silicon wafer 6 due to a difference in temperature distribution or temperature-raising speed. Besides, a greater difference may also occur in reachable highest temperature between the central part 6a and the peripheral part 6b of the silicon wafer 6 for the same reasons. Such differences will result in development of not only warping but also a physical defect which is generally called "slip lines". The above temperature difference occurs in the silicon wafer 6 because more heat quantity is radiated outwardly from the peripheral part 6b of the silicon wafer 6 than the central part 6a and the peripheral part 6b is thus heated at a slower temperature-raising speed or to a lower temperature.
Since the above-mentioned heating of the silicon wafer 6 by means of radiated light is effected in the present invention under such conditions that the temperature difference between the central part 6a of the wafer 6 and its peripheral part 6b does not exceed 65° C., the silicon wafer 6 can be heated to high temperatures to cause dopant atoms to undergo diffusion thereinto without inducing any physical defects, i.e., warping or slip lines to occur. The above effect of the present invention has been confirmed through experiments.
The following means are effective to achieve the above-described heating by radiated light while fulfilling the requirement that the temperature difference between the central part 6a of the silicon wafer 6 and its peripheral part 6b be maintained within 65° C.:
(1) To place a silicon wafer having a relatively small diameter compared with the areas of the plane light sources in face-to-face relationship with central regions of the plane light sources.
Supposing that each of the plane light sources has an area of 20 cm×25 cm as mentioned above and the distance between the common plane on which the filament of each of the halogen lamps 4a,4b lies and its corresponding surface of the silicon wafer 6 is for instance 4 cm, the above heating method is effective for silicon wafers having a diameter of 5 inches or smaller.
(2) To provide the subsidiary heater 8 so as to surround the outer circumference of the silicon wafer 6 or allow it to extend along the outer circumference of the silicon wafer 6, whereby additionally heating the peripheral part 6b of the silicon wafer 6.
The provision of the subsidiary heater 8 not only reduces the radiation of heat from the peripheral part 6b of the silicon wafer 6 but also, on the contrary, applies heat to the peripheral part 6b to compensate any temperature drop at the peripheral part 6b. As the subsidiary heater 8, may be employed, for example, an annular halogen lamp, an annular metallic member having a high melting point which radiates heat on receiving the light or the like.
(3) To displace halogen lamps positioned at the peripheral parts of the upper and lower plane light sources inwardly in the vertical direction of the light-heating space 10, in other words, closer to the silicon wafer 6 or to supply a greater power to halogen lamps positioned at the peripheral parts of the upper and lower plane light sources than the remaining halogen lamps.
The above means (3) can bring about the same effects as the means (2).
Having generally described the invention, a more complete understanding can be obtained by reference to certain specific examples, which are provided herein for purposes of illustration only and are not intended to be limiting unless otherwise specified.
EXAMPLE 1
A silicon nitride (Si3 N4) film of 0.2 μm thick was formed on a surface of a wafer made of an Si single crystal and having a diameter of 10 cm and a thickness of 0.45 mm and aluminum ions, which had been accelerated with an energy of 320 KeV, were implanted to a concentration of 8×1015 ions/cm2 through the film, thereby obtaining a wafer in which a junction was formed at a depth of 3 μm with an aluminum-doped layer. When the thus-obtained silicon wafer was heated by applying light thereonto in a light-heating furnace of the same construction as shown in FIG. 1, the temperatures of the central part and peripheral part of the silicon wafer 6 were raised respectively to 1350° C. and 1335° C. Upon continuing the application of light for 3 minutes under the above conditions, aluminum atoms implanted were caused to undergo diffusion and the depth of the junction was increased to 5 μm. No development of physical defects such as slip lines was observed.
EXAMPLE 2
Ion implantation into a silicon wafer was effected in the same manner as in Example 1 except that gallium ions, which had been accelerated with an energy of 350 KeV, were implanted to a concentration of 3×1015 ions/cm2. When light was applied onto the thus-obtained wafer in the same manner as in Example 1, the wafer was heated to 1350° C. at its central part and 1345° C. at its peripheral part. Upon continuing the application of light for 20 minutes under the same conditions, gallium atoms were caused to undergo diffusion and the depth of the junction was increased to 5 μm. No development of physical defects such as slip lines was observed.
EXAMPLE 3
A film of phosphorus trioxide having a thickness of 0.4 μm was formed on a silicon wafer of the same type as that used in Example 1. When the silicon wafer was exposed to light in the same manner as in Example 1, the wafer was heated to 1350° C. at its central part and 1330° C. at its peripheral part. After continuing the application of light under the same conditions for 45 minutes, phosphorus atoms had undergone solid-phase diffusion, thereby providing a wafer having a junction formed at a depth of 5 μm with a phosphorus-doped layer. Similar results were brought about when a silicon wafer applied with a film of phosphorus glass in place of the film of phosphorus trioxide.
As understood from the above description, the present invention has made it possible to complete each diffusion treatment in a relatively short period of time because a silicon wafer is heated by applying light thereonto so as to diffuse dopant atoms into the interior of the silicon wafer. Since the heating of a silicon wafer is carried out in the present invention under such conditions that the temperature difference between the central part of the silicon wafer and its peripheral part does not exceed 65° C., the silicon wafer does not develop such physical defects as warping or slip lines. Accordingly, the method of the present invention can diffuse dopant atoms to a significantly greater junction depth in a shorter period of time and can fabricate doped silicon wafers with higher productivity, compared with the conventional heating method which makes use of a resistance furnace.
Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the invention as set forth herein.

Claims (10)

What is claimed is:
1. A method for diffusing dopant atoms into a silicon wafer, which method comprises heating the entirety of said silicon wafer with said dopant atoms to a predetermined diffusing temperature in a short period of time by applying light thereonto under such conditions that the temperature difference between a central part of said silicon wafer and a peripheral part thereof is maintained within 65° C., thereby causing said dopant to undergo thermal diffusion into the interior of said silicon wafer.
2. A method as claimed in claim 1, wherein the light is applied from an upper and lower plane light sources disposed respectively above and below said silicon wafer and each of said plane light sources is constructed of a reflector and a number of halogen lamps arranged close to one another between said reflector and the silicon wafer.
3. A method as claimed in claim 2, wherein said plane light sources have areas wider than said silicon wafer and the application of the light is carried out while holding said silicon wafer in face-to-face relationship with central regions of said plane light sources.
4. A method as claimed in claim 2, wherein halogen lamps arranged along the peripheries of their corresponding plane light sources are closer to the level at which said silicon wafer is held, compared with the remaining halogen lamps.
5. A method as claimed in claim 2, wherein halogen lamps arranged along the peripheries of their corresponding plane light sources are operated with a power consumption greater than the remaining halogen lamps.
6. A method as claimed in claim 1, wherein the light is applied to said silicon wafer which is held within a transparent container.
7. A method as claimed in claim 1, wherein the application of the light is carried out while additionally heating the peripheral part of said silicon wafer by means of a subsidiary heater arranged along the peripheral part of said silicon wafer.
8. A method as claimed in claim 1, wherein said dopant atoms have in advance been introduced in said silicon wafer by the ion implantation process.
9. A method as claimed in claim 8, wherein the dopant atoms are aluminum or gallium.
10. A method as claimed in claim 1, wherein a material containing said dopant atoms have in advance been applied on said silicon wafer.
US06/480,082 1982-06-22 1983-03-29 Method for diffusing dopant atoms Expired - Fee Related US4468260A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57-106189 1982-06-22
JP57106189A JPS58223320A (en) 1982-06-22 1982-06-22 Diffusing method for impurity

Publications (1)

Publication Number Publication Date
US4468260A true US4468260A (en) 1984-08-28

Family

ID=14427242

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/480,082 Expired - Fee Related US4468260A (en) 1982-06-22 1983-03-29 Method for diffusing dopant atoms

Country Status (2)

Country Link
US (1) US4468260A (en)
JP (1) JPS58223320A (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4560420A (en) * 1984-06-13 1985-12-24 At&T Technologies, Inc. Method for reducing temperature variations across a semiconductor wafer during heating
FR2596201A1 (en) * 1986-03-24 1987-09-25 Westinghouse Electric Corp METHOD FOR MANUFACTURING SEMICONDUCTOR JUNCTIONS AND PRODUCTS THUS OBTAINED
US4916090A (en) * 1988-03-23 1990-04-10 Nippon Precision Circuits Ltd. Amorphous silicon thin film transistor and method of manufacturing the same
US4958061A (en) * 1988-06-27 1990-09-18 Tokyo Electron Limited Method and apparatus for heat-treating a substrate
US4965515A (en) * 1986-10-15 1990-10-23 Tokyo Electron Limited Apparatus and method of testing a semiconductor wafer
US5044943A (en) * 1990-08-16 1991-09-03 Applied Materials, Inc. Spoked susceptor support for enhanced thermal uniformity of susceptor in semiconductor wafer processing apparatus
US5086270A (en) * 1988-07-08 1992-02-04 Tokyo Electron Limited Probe apparatus
WO1993003310A1 (en) * 1991-07-30 1993-02-18 Quadlux, Inc. Cooking apparatus using electron and molecular excitation mode
US5517005A (en) * 1988-05-19 1996-05-14 Quadlux, Inc. Visible light and infra-red cooking apparatus
US5710407A (en) * 1993-01-21 1998-01-20 Moore Epitaxial, Inc. Rapid thermal processing apparatus for processing semiconductor wafers
US5902407A (en) * 1987-03-31 1999-05-11 Deboer; Wiebe B. Rotatable substrate supporting mechanism with temperature sensing device for use in chemical vapor deposition equipment
US5958271A (en) * 1997-09-23 1999-09-28 Quadlux, Inc. Lightwave oven and method of cooking therewith with cookware reflectivity compensation
US5990454A (en) * 1997-09-23 1999-11-23 Quadlux, Inc. Lightwave oven and method of cooking therewith having multiple cook modes and sequential lamp operation
US6013900A (en) * 1997-09-23 2000-01-11 Quadlux, Inc. High efficiency lightwave oven
US6034356A (en) * 1996-11-26 2000-03-07 Texas Instruments Incorporated RTP lamp design for oxidation and annealing
WO2001006031A1 (en) * 1999-07-14 2001-01-25 Seh America, Inc. Susceptorless semiconductor wafer support and reactor system for epitaxial layer growth
US6316747B1 (en) * 1998-03-02 2001-11-13 Steag Rtp Systems Gmbh Apparatus for the thermal treatment of substrates
US6375749B1 (en) 1999-07-14 2002-04-23 Seh America, Inc. Susceptorless semiconductor wafer support and reactor system for epitaxial layer growth
US6395085B2 (en) 1999-07-14 2002-05-28 Seh America, Inc. Purity silicon wafer for use in advanced semiconductor devices
US20020062792A1 (en) * 1999-07-14 2002-05-30 Seh America, Inc. Wafer support device and reactor system for epitaxial layer growth
US6454852B2 (en) 1999-07-14 2002-09-24 Seh America, Inc. High efficiency silicon wafer optimized for advanced semiconductor devices
US6632277B2 (en) 1999-07-14 2003-10-14 Seh America, Inc. Optimized silicon wafer gettering for advanced semiconductor devices
WO2004072323A2 (en) * 2003-02-07 2004-08-26 Solaicx High reflectivity atmospheric pressure furnace for preventing contamination of a work piece
US20070293026A1 (en) * 2006-06-16 2007-12-20 Hynix Semiconductor Inc. Method of manufacturing semiconductor device
US20100267307A1 (en) * 2009-04-16 2010-10-21 Samsung Mobile Display Co., Ltd. Sealing apparatus and method of manufacturing flat display device using the same
CN115565852A (en) * 2022-12-06 2023-01-03 西安奕斯伟材料科技有限公司 Method and apparatus for back sealing silicon wafer

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503087A (en) * 1983-08-29 1985-03-05 Varian Associates, Inc. Process for high temperature drive-in diffusion of dopants into semiconductor wafers
JPH0719759B2 (en) * 1984-09-13 1995-03-06 セイコーエプソン株式会社 Method for manufacturing semiconductor device
JPS6139516A (en) * 1984-07-30 1986-02-25 Seiko Epson Corp Manufacture of semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3589949A (en) * 1968-08-22 1971-06-29 Atomic Energy Authority Uk Semiconductors and methods of doping semiconductors
US3627590A (en) * 1968-12-02 1971-12-14 Western Electric Co Method for heat treatment of workpieces
US4001047A (en) * 1975-05-19 1977-01-04 General Electric Company Temperature gradient zone melting utilizing infrared radiation
US4012236A (en) * 1975-12-31 1977-03-15 General Electric Company Uniform thermal migration utilizing noncentro-symmetric and secondary sample rotation
US4016006A (en) * 1974-10-30 1977-04-05 Hitachi, Ltd. Method of heat treatment of wafers
US4170490A (en) * 1978-12-07 1979-10-09 General Electric Company Process for thermal gradient zone melting utilizing a beveled wafer edge
US4370174A (en) * 1981-08-31 1983-01-25 Braithwaite Jr Charles H Method for removing adhesive residues with an emulsion cleaner
US4415372A (en) * 1980-10-24 1983-11-15 Tokyo Shibaura Denki Kabushiki Kaisha Method of making transistors by ion implantations, electron beam irradiation and thermal annealing

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS445160Y1 (en) * 1966-03-07 1969-02-25
SE7710800L (en) * 1976-10-05 1978-04-06 Western Electric Co PROCEDURE FOR THE SUBSTITUTION OF AN EPITAXIAL LAYER ON A SUBSTRATE

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3589949A (en) * 1968-08-22 1971-06-29 Atomic Energy Authority Uk Semiconductors and methods of doping semiconductors
US3627590A (en) * 1968-12-02 1971-12-14 Western Electric Co Method for heat treatment of workpieces
US4016006A (en) * 1974-10-30 1977-04-05 Hitachi, Ltd. Method of heat treatment of wafers
US4001047A (en) * 1975-05-19 1977-01-04 General Electric Company Temperature gradient zone melting utilizing infrared radiation
US4012236A (en) * 1975-12-31 1977-03-15 General Electric Company Uniform thermal migration utilizing noncentro-symmetric and secondary sample rotation
US4170490A (en) * 1978-12-07 1979-10-09 General Electric Company Process for thermal gradient zone melting utilizing a beveled wafer edge
US4415372A (en) * 1980-10-24 1983-11-15 Tokyo Shibaura Denki Kabushiki Kaisha Method of making transistors by ion implantations, electron beam irradiation and thermal annealing
US4370174A (en) * 1981-08-31 1983-01-25 Braithwaite Jr Charles H Method for removing adhesive residues with an emulsion cleaner

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4560420A (en) * 1984-06-13 1985-12-24 At&T Technologies, Inc. Method for reducing temperature variations across a semiconductor wafer during heating
FR2596201A1 (en) * 1986-03-24 1987-09-25 Westinghouse Electric Corp METHOD FOR MANUFACTURING SEMICONDUCTOR JUNCTIONS AND PRODUCTS THUS OBTAINED
GB2188481A (en) * 1986-03-24 1987-09-30 Westinghouse Electric Corp Method of forming semiconductor junctions
GB2188481B (en) * 1986-03-24 1989-12-20 Westinghouse Electric Corp Method of forming semiconductor junctions
US4965515A (en) * 1986-10-15 1990-10-23 Tokyo Electron Limited Apparatus and method of testing a semiconductor wafer
US5902407A (en) * 1987-03-31 1999-05-11 Deboer; Wiebe B. Rotatable substrate supporting mechanism with temperature sensing device for use in chemical vapor deposition equipment
US4916090A (en) * 1988-03-23 1990-04-10 Nippon Precision Circuits Ltd. Amorphous silicon thin film transistor and method of manufacturing the same
USRE36724E (en) * 1988-05-19 2000-06-06 Quadlux, Inc. Visible light and infra-red cooking apparatus
US5517005A (en) * 1988-05-19 1996-05-14 Quadlux, Inc. Visible light and infra-red cooking apparatus
US4958061A (en) * 1988-06-27 1990-09-18 Tokyo Electron Limited Method and apparatus for heat-treating a substrate
US5086270A (en) * 1988-07-08 1992-02-04 Tokyo Electron Limited Probe apparatus
US5044943A (en) * 1990-08-16 1991-09-03 Applied Materials, Inc. Spoked susceptor support for enhanced thermal uniformity of susceptor in semiconductor wafer processing apparatus
WO1993003310A1 (en) * 1991-07-30 1993-02-18 Quadlux, Inc. Cooking apparatus using electron and molecular excitation mode
US6151447A (en) * 1993-01-21 2000-11-21 Moore Technologies Rapid thermal processing apparatus for processing semiconductor wafers
US5710407A (en) * 1993-01-21 1998-01-20 Moore Epitaxial, Inc. Rapid thermal processing apparatus for processing semiconductor wafers
US6310327B1 (en) 1993-01-21 2001-10-30 Moore Epitaxial Inc. Rapid thermal processing apparatus for processing semiconductor wafers
US6034356A (en) * 1996-11-26 2000-03-07 Texas Instruments Incorporated RTP lamp design for oxidation and annealing
US6013900A (en) * 1997-09-23 2000-01-11 Quadlux, Inc. High efficiency lightwave oven
US5958271A (en) * 1997-09-23 1999-09-28 Quadlux, Inc. Lightwave oven and method of cooking therewith with cookware reflectivity compensation
US5990454A (en) * 1997-09-23 1999-11-23 Quadlux, Inc. Lightwave oven and method of cooking therewith having multiple cook modes and sequential lamp operation
US6316747B1 (en) * 1998-03-02 2001-11-13 Steag Rtp Systems Gmbh Apparatus for the thermal treatment of substrates
US20020062792A1 (en) * 1999-07-14 2002-05-30 Seh America, Inc. Wafer support device and reactor system for epitaxial layer growth
US6375749B1 (en) 1999-07-14 2002-04-23 Seh America, Inc. Susceptorless semiconductor wafer support and reactor system for epitaxial layer growth
US6395085B2 (en) 1999-07-14 2002-05-28 Seh America, Inc. Purity silicon wafer for use in advanced semiconductor devices
WO2001006031A1 (en) * 1999-07-14 2001-01-25 Seh America, Inc. Susceptorless semiconductor wafer support and reactor system for epitaxial layer growth
US6454852B2 (en) 1999-07-14 2002-09-24 Seh America, Inc. High efficiency silicon wafer optimized for advanced semiconductor devices
US6632277B2 (en) 1999-07-14 2003-10-14 Seh America, Inc. Optimized silicon wafer gettering for advanced semiconductor devices
WO2004072323A3 (en) * 2003-02-07 2004-12-09 Solaicx High reflectivity atmospheric pressure furnace for preventing contamination of a work piece
WO2004072323A2 (en) * 2003-02-07 2004-08-26 Solaicx High reflectivity atmospheric pressure furnace for preventing contamination of a work piece
US20070293026A1 (en) * 2006-06-16 2007-12-20 Hynix Semiconductor Inc. Method of manufacturing semiconductor device
US20100267307A1 (en) * 2009-04-16 2010-10-21 Samsung Mobile Display Co., Ltd. Sealing apparatus and method of manufacturing flat display device using the same
US8500506B2 (en) * 2009-04-16 2013-08-06 Samsung Display Co., Ltd. Sealing apparatus and method of manufacturing flat display device using the same
TWI408630B (en) * 2009-04-16 2013-09-11 Samsung Display Co Ltd Sealing apparatus and method of manufacturing flat display device using the same
US8864543B2 (en) 2009-04-16 2014-10-21 Samsung Display Co., Ltd. Sealing apparatus and method of manufacturing flat display device using the same
CN115565852A (en) * 2022-12-06 2023-01-03 西安奕斯伟材料科技有限公司 Method and apparatus for back sealing silicon wafer
CN115565852B (en) * 2022-12-06 2024-05-28 西安奕斯伟材料科技股份有限公司 Method and apparatus for back-sealing silicon wafers

Also Published As

Publication number Publication date
JPS58223320A (en) 1983-12-24

Similar Documents

Publication Publication Date Title
US4468260A (en) Method for diffusing dopant atoms
US4581520A (en) Heat treatment machine for semiconductors
US4535228A (en) Heater assembly and a heat-treatment method of semiconductor wafer using the same
US4493977A (en) Method for heating semiconductor wafers by a light-radiant heating furnace
JP3484651B2 (en) Heating device and heating method
US4571486A (en) Heating method of semiconductor wafer
US4504323A (en) Method for annealing semiconductors with a planar source composed of flash discharge lamps
US4469529A (en) Method for heating semiconductor wafer by means of application of radiated light with supplemental circumferential heating
US4535227A (en) Method for heating semiconductor wafer by means of application of radiated light
US6122440A (en) Optical heating device for rapid thermal processing (RTP) system
JPH0715894B2 (en) Semiconductor heat treatment furnace
US4659422A (en) Process for producing monocrystalline layer on insulator
CN107342253A (en) Support cylinder for thermal processing chamber
US4468259A (en) Uniform wafer heating by controlling light source and circumferential heating of wafer
US4543472A (en) Plane light source unit and radiant heating furnace including same
US4504730A (en) Method for heating semiconductor wafer by means of application of radiated light
US7038173B2 (en) Thermal processing apparatus and thermal processing method
JPS60161616A (en) Infrared heating unit for semiconductor wafer
JPS6244848B2 (en)
JPH0377657B2 (en)
JPS59178718A (en) Semiconductor substrate processing apparatus
JPS60137027A (en) Optical irradiation heating method
US4540911A (en) Halogen lamp unit
JPS63257221A (en) Lamp annealing apparatus
JPH025295B2 (en)

Legal Events

Date Code Title Description
AS Assignment

Owner name: USHIO DENKI KABUSHIKI KAISHA, TOKYO, JAPAN,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:HIRAMOTO, TATSUMI;REEL/FRAME:004117/0521

Effective date: 19830307

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Lapsed due to failure to pay maintenance fee

Effective date: 19960828

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362