US3918038A - Alpha numeric raster display system - Google Patents

Abstract

An information storage and display system for time sequential information using a cathode ray tube raster brightup display and a memory system, wherein the high speed or line scan of the raster is transverse to the time sequence of the displayed information, and the information is stored in a memory in sequence according to its order on the scan rather than its original time sequence.

Description

Umted States Patent 1191 1111 3,918,038

Stonelake Nov. 4, 1975 ALPHA NUMERIC RASTER DISPLAY 3,422,420 l/1969 Clark 340/324 AD SYSTEM 3,423,749 l/1969 Newcomb 340/324 AD 3,510,866 5/1970 Kronick et al. 340/324 AD Inventori Dennis Stonelake, Burlington, 3,585,440 6/1971 Lee et a1. 340 324 AD Canada 3,611,348 10/1971 Rogers 340/324 AD Assignee: Westinghouse Canada Limited, 3,737,890 6/1973 Salava 340/324 AD Hamilton, Canada 2 Filed; Nov. 9, 1973 Primary Examiner-Marshall M. Curtis [21] Appl. No.: 414,295

Related US. Application Data [57] ABSTRACT [63] Continuation of Ser. No. 255,227, May 19, 1972,

abandoned, An information storage and display system for time sequential information using a cathode ray tube raster [30] Forelgn Apphcatlon Prlorlty Data brightup display and a memory system, wherein the May 26, 1971 Canada 113895 h gh speed or n scan of he r ter is transverse to the time sequence of the displayed information, and [52] US. Cl. 340/324 AD; 235/198 he information is stored in a memory in sequence ac- [51] Int. C1. G06F 3/ 14 cording to its order on the scan rather than its original [58] Field of Search 340/324 AD; 235/198 time sequence.

[56] References Cited 3 Claims, 5 Drawing Figures UNITED STATES PATENTS 3,396,377 8/1968 Strout 340/324 AD VIDEO GENERATOR,

DISPLAY.

NTERLACE UNE SCAN GENERATOR LINE SHIFT RECRCULATION CONTROL FIELD SYNCH.

BIT STORE A BIT STORE BIT STORE C BIT STORE M BIT STORE N,

BIT STORE O 3 BIT STORE 3 BIT STORE COUJMN SELECTOR,

3 BIT FUNCTION GENERATOR US. Patent Nov. 4, 1975 Sheet 1 of3 3,918,038

\ Mm: ..mmHMIIHWINM "11;; L m {h u FIG. 2.

U.S. Patent Nov. 4, 1975 Sheet2 Of3 3,918,038

INPUT CONTROL LE 40 12 I REURC- BIT STORE A,

CODER ULATION CONTROL 15\ L an STORE M, 19- 4c BIT STORE N. FIG. 3. 49

BIT sTORE O. l l l RECIRCULATION COLUMN l CONTROL 4O SELECTOR.\ J} i i 29 1 381T STORE, l VIDEO I GENE ATOR. I 2

. v cHARAcTER I 4O COLUMN l GENERATOR. SELECTOR. i J 3B|T STORE. 1 I so I l I l 33 32 I I 27 W I l C 1 set wwi I COUNTER. l 41 3B|T STORE. 1 1 36 31 x z I Y 28 FIELD SCAN DISPLAY GENERATOR. 25

w FUNCTION 4 34 I GENERATOR.

FIELD INTERLACE SYNCH. i GENERATOR u 35 uNE SCAN 37 GENERATOR LINE SYNCH. SHIFT ALPHA NUMERIC RASTER DISPLAY SYSTEM This is a continuation of application Ser. No. 255,227, filed May 19, 1972 now abandoned.

RELATED CASES This application is related to application Ser. No. 157,486, filed June 28, 1971, now abandoned.

BACKGROUND OF THE INVENTION There are various ways of producing alpha-numeric and analog displays on cathode ray tubes. Oscilloscopes, of course, are one example of general application, and television displays are another typical type of a display. This present invention has a closer relation ship to the latter type of display which may be generally described as a raster bright-up display. That is, a display wherein the cathode ray tube is deflected at a high rate of speed in one direction and at a lower rate of speed in the other direction, thus producing a raster on the face of the tube. The beam is then modulated in intensity in such a way as to cause the raster to brighten up in specified locations, producing the desired display. In the system described in the above-identified application, such a raster was used to produce an analog display of some variable quantity. In a similar manner, alpha-numerics may be displayed by causing suitable modulation of the beam in the raster.

If it is desired to display a substantial quantity of alpha-numeric information on the face of the tube, information will normally be arranged in the form of a printed page; that is, with lines of information running transversely and arranged in a vertical order. When information is so arranged, and if the characters used are of a standardized nature, their order may be consistent not only in lines but also in columns. That is, the first letter of each line can be arranged to fall in a column and the second letters will also then automatically fall in a column. In systems of the type under consideration, it is usual for the alpha-numeric characters to be of standardized dimension, and hence it will be normal for a display to be not only regular in line formation but also regular in columnar formation. Given the standard television screen parameters, there will be more elements in a transverse line than in a column. A typical relationship would indicate, for example, 80 characters on a line with twenty lines arranged one below each other in the whole display. Such a proportion would be convenient to read and have an optimum ratio. It will be seen however that if there are eighty characters in the line and if the raster is arranged in the normal T.V. arrangement, a horizontal high speed line will scan eighty characters. Assuming each character is equivalent to a six-bit code, this will be equal to at least 480 bits per sweep. If, on the other hand, one were to scan in the opposite direction; that is, in a columnar direction, each high speed scan, which would then be vertical, would contain information relative to 20 characters or only a 120 bits.

At the same time, if the information is to be displayed in a time sequence corresponding to the columnar arrangement, certain advantages will accrue if it is also stored in a memory in the same sequence; that is, if the memory contains information in the column sequential order. One particular advantage of column sequential order of the information in the memory is that the memory may be updated to produce a roll-up; that is, dropping off the first line of information from the top of the screen, and adding new lines of information at the bottom, in a very convenient manner, simply by delaying the information in the storage in such a way that the new information may be entered at the proper location and the old information is rejected.

In accordance with this invention, there is provided an alpha-numeric display of the raster bright-up type wherein the high speed scan is in the vertical or minor dimension of the raster and the horizontal or major dimension is produced by the low speed scan. The data to be displayed is stored in shift registers in the form of binary code, each register storing bits related to characters in a column and in a sequential series of columns. At the same time, registers are arranged in word parallel so that a group of three registers contains the code representative of the character to be displayed and information as to the manner of display; that is, whether it is a flashed or protected display, etc.

A clearer understanding of this invention may be had from the following description and drawings, in which:

FIG. 1 is an illustration of the appearance of the dis- P y;

FIG. 2.is a block diagram of the master clock and the various frequencies necessary to operate the system;

FIG. 3 is a block diagram of the system showing functional blocks only;

FIG. 4 is a time graph of the various data stores showing the arrangement of information in each store;

FIG. 4a is a detailed diagram of a portion of FIG. 4 illustrating the data in one store.

Considering first FIG. 1, it will be seen that the display is assumed to be normal page format consisting of lines of characters including both alphabetic and numeric characters. The lines are arranged horizontally, running in the widest dimension of the display assuming a normal television raster ratio of width to heighth. It will also be seen that the high speed sweep is in the vertical direction and that the characters are arranged in colurrms so that any character is formed from a brightup modulation of the beam in one or more of five vertical sweeps. In the case illustrated, for example, it will be seen that the first sweep, in the first group of five commencing with the character E is to be brightened up to form the back edge of the E and will then be brightened up to form the first bar of the M, which is the first character in the second line and one of the characters in the first column of characters. In a similar manner, all the characters in this first column of characters are formed by brightening up the display in the first five vertical traces.

As will be later shown, the first five vertical traces are not sequential in time. In fact, the first line of each group of five belongs to the same set or field and such lines are time sequential. In a similar manner, the second line of each group of five belongs to the same field and such second lines are time sequential. The interlacing of the display is such that there are five fields to each frame, and hence each line in a group of five belongs to a different field. Because of this particular arrangement, it will become apparent that the spacing between the characters in the lines can be adjusted by adjusting the spacing between vertical scan lines and since this spacing is a function of the interlace control, the widths of the columns can conveniently be changed simultaneously.

In order to produce the display it is necessary to provide suitable timing pulses to produce the necessary vertical scan and also the horizontal scan and the proper interlace between the fields to produce complete frames. Pulses are also necessary to time the operation of the memory and coding circuits.

In FIG. 2 there is shown a suitable timing circuit in block form. The output from the master clock, which has a frequency of 6.3 mgH, is divided in a manner well known to those skilled in the art and shown for example in copending application Ser. No. 088,916, first by four to produce pulses for operating the shift registers and then by three to produce the character rate. This is divided by 25 to produce a vertical line synchronizing pulse and then by eight and twelve to produce a field synchronizing pulse. This is then divided by five to produce the frame rate. The output from the divide-by-five circuit is also fed into a three bit digital-to-analog converter to produce the desired interlace which, as was previously indicated, is a five-to-one interlace. The digital-to-analog converter provides a five step shift for producing the displacement of the fields in order to produce the desired five-to-one interlace.

Considering now FIG. 3, there is shown a simplified block diagram of the system. The alpha-numeric signals are received on terminal 12 and converted in coder 13 into suitable six-bit code. The first three bits and the second three bits appear on output terminals 14 and 15 and define the character. The last three bits appear on terminal 16 and define other characteristics such as whether the character shall be flashed or constant. The output from terminals 14, 15 and 16 is applied to an input control 17 which determines whether the information in the system is recirculated or new information is inserted from terminals 14, 15 and 16, and is in effect simply a three-pole, double-throw switch. The output from the input control is applied to recirculation control 18 and to five similar devices, only the last of which is shown and designated as recirculation control 19. Because the circuits for all these portions are identical, they have been omitted from the diagram for simplicitys sake. The three outputs from the recirculation control are applied to three bit stores, bit store A, bit store B and bit store C, designated 20, 21 and 22 respectively. Bit store A stores only bits originating from terminal 14 which represents the first three bits in any character code and will be referred to as the first byte. Bit store B correspondingly stores the second byte, and bit store C stores the third byte. The output from the bit stores A, B and C is applied to three different column selectors 23, 24 and 25. Each column selector has five inputs. Column selector 23 for example receives the output from five bit stores each being the first bit store in each group of three; that is, bit store A, bit store D, bit store G, bit store J and bit store M (only bit stores A and M are shown as previously indicated). In a similar manner, column selector 24 receives the output from bit stores B, E, H, K and N, and in a similar manner, column selector 25 receives the output from bit store C, bit store F, bit store I, bit store L and bit store 0. The output from each column selector 23, 24 and 25 is applied to a three bit store 26, 27 and 28, respectively. The output from these stores appears on terminals 29, 30 and 31 which, it will be noted, also are connected to the input control, and hence the output from the system can be recirculated back into the input as desired in a manner and for the purpose to be described hereinafter.

Bit stores 26 and 27 are each connected to the character generator through three terminals. The character generator with six inputs will define any one of the vari-. ous characters to be displayed. The character generator is a read only memory with seven outputs from five rows of seven points in a five-by-seven matrix. Each row of the character consists of signals representative of the particular character. For example, the character B will produce an outputon the first to seventh output lines during the first row, will produce outputs on lines 1, 4 and 7 on the second row, will produce outputs on output lines 1, 4 and 7 on the third row, on lines 1 and 7 on the fourth row and lines 1 and 7 on the fifth row. Three further inputs to the character generator from five-bit counter 38 determine which row is being read at any particular time. These inputs select one of the five rows in response to the counter output which is driven from the master clock terminal 41..The seven outputs from the character generator are applied to video generator 33, and from thence to the display where it intensity-modulates the cathode ray tube beam. A line scan generator 35 produces a deflection voltage which is applied to the display device 34 causing vertical deflection of the cathode ray beam. Similarly, a field scan generator 36 and an interlace generator 37 produce the desired field and frame deflections to produce the display as shown in FIG. 1.

A clearer understanding of the arrangement of the information in the storage portion of the system, which consists of bit stores 1 to 15, may be had from a consideration of FIGS. 4 and 4a. As will be seen in FIG. 4, bit store 20 contains all bytes one from column 1. In the next segment of time, it contains all bytes one from column 2, and so on until we come to the last periodof time in bit store 20 which contains all bytes one in column 16. Bit store 21 will be seen to contain all bytes two in column 1, and bit store 22 contains all bytes three in column 1. The next group of stores, that is, bit. stores D, E and F (not shown in FIG. 3) contain the information from columns 17, 18, 19 etc. up to column 32 and finally, bit store M contains all bytes one from column 65, bytes one from column 66, etc. Bit store N contains all bytes two from column 65, column 66, etc. and bit store 0 contains bytes three from columns 65 and 66, etc.

As is shown in FIG. 4a, the bytes one from column 1 consist of the first three bits of information relating to the first character in the first column. In the immediately subsequent space is the first three bits of information relating to the second character in the first column, and so on until we arrive at the last piece of information relative to column 1 which is the first three bits of information relating to the twentieth character in column 1. Bit store 21 similarly contains the next three bits of information or the second byte, relating to the characters 1 to 20 in column 1, and bit store 22 similarly contains the last three bits or the last byte relating to the characters contained in column 1. Standard bit stores of the type used in the system being described are capable of containing 1024 bits. Each bit store will then contain sixteen groups of 64 bits, each group representing one column. Therefore, with a bit store containing groups representing sixteen columns and five bit stores, there is storage space for eighty columns as required. As seen in FIG. 4a, the bits relative to a particular column in one bit store will be at a maximum of three bits times 20 or bits. There is then provided a spacing before the information relative to the next column is inserted. This spacing is equivalent to. four bits. The bit store then contains, as previously indicated, sixteen groups of sixty bits with a four-bit spacing between each group.

OPERATION Rather than describing the loading ofv the system, it will be assumed that a complete message has been received and is stored in the system and is being displayed on a display device 34. The manner in which the display is generated will be described in relation to the first vertical sweep. At time zero at the beginning of the first vertical sweep, the information at the output of the bits stores 20, 21 and 22 appears at the input of the column selectors 23, 24 and 25. The column selectors which essentially consist of selector switches are all switched to their first position coupling their number one inputs to their outputs and the bit stores 26, 27 and 28 are shifted at clock rate by a signal derived from the master clock chain at terminal 40. The six bits defining the first character in the first row then appear on the terminal of three- bit stores 26 and 27 which are connected to the character generator. Associated with the character generator is a' five bit counter 38 which is driven with pulses from terminal 41 in the master clock which provides the field synchronization rate.

The three lines from the five bit counter 38 which are connected to the character generator 32 determine which one of the five rows is to be readout into the video generator from the character generator. The nature of the signal read out of course is determined as previously indicated by the character information supplied from three bit stores 26 and 27. In this way, on the first count, the first line of characters is generated in the character generator and is applied as seven outputs to the video generator. Therefore the first field is provided with video signal representative only of the first line of each character as it appears in the character generator. During the first vertical sweep, bit stores 1, Y

2 and 3 are provided with clock pulses from terminal 40 causing the information relative to the first column to appear at their output terminals. As long as no new information is being entered, this information recirculates to the input of the stores through the recirculation control 18 and is re-applied to the bit stores 1, 2 and 3. The information in the bit stores then may be considered to be circulating and their outputs appear at the column selectors as previously described 23, 24 and 25. At the end of the sixteenth sweep, the column selectors, which are driven from tenninals 44, 45 and 46 in the master clock, now switch to couple their second input to the three bit stores, and therefore the outputs from the bit stores D, E and F are connected through the column selector into the three bit stores and thence to the character generatores and produce the desired video display.

This process continues until a complete field has been displayed at which time the counter 38 energizes the second row and the process is repeated. By this time, the information in bit store number 1 which is appearing at the output once again represents characters in column 1, but when these are transferred to the three bit stores and to the character generator, it is the second line of the character which is read out into the video generator. At the same time, the interlace generator has supplied a step waveform, which causes the first vertical sweep of the second field to be displaced from the first vertical sweep of the first field. This procedure repeats until five fields have been displayed and the characters built up from five vertical sweeps. By ad 5 justing the voltage applied to terminal 11 of the three bit digital-to-analog converter, theposition of corresponding lines of sequential fields can be varied. Thus, the five lines representing a column of characters can be close together or further apart depending upon analog value produced by the interlace generator.

In order to enter new information into the display, it is necessary that the new'information be addressed. To this end, row comparator 9 and column comparator lO in FIG. 2 produce outputs from their terminals designated E when the desired address corresponds to the current address of the information being circulated into the store. During this inflow, the recirculation control, such as the recirculation control 18, switches its input from the output of the bit stores 20, 21, etc. to the output of the input control 17. Therefore, the information which is being fed in from terminal 12 through the coder 13 and input control 17 is applied to the bit stores at the proper location. In order for the information to be available at the input control it is only necessary for it to be present during one complete circulation of the bit stores; that is, 16 lines or about 800 microseconds, depending upon the exact frequency used for the master oscillator. This evidently will be a sufficiently short a period of time to accept any teletype or keyboard input which would normally have a rate of 9600 bits per second.

In addition to inserting new information at a particular point in the display, it may at times be desirable to insert a new line of information at some point in the display and drop off the lowest line. In order to do this, first one must erase line 20. This is accomplished by inhibiting recirculation during line 20. For example, in bit store 1 as shownin FIG. 4a, byte 1, symbol 20, column 1 will be prevented from recirculating, and simultaneously, byte 2, symbol 20, column 1 in bit store 2 is inhibited from recirculating. This inhibit is applied at the same time to all bit store recirculation controls and during the same time periods by which means all the information relative to symbol 20 in each column is eliminated.

Next, assuming the new line of information is to be applied at line n, every time the column comparator indicates a line n position, the output from the bit stores rather than being recirculated directly back to the recirculation control, is circulated through the three bit stores to terminals 29, 30 and 31 and appears back at the input control. The recirculation control at the same time is operated so as to couple the output from the input control to the bit stores. During the period of line n, the new information is input from the coder through the input control to the recirculation control into the bit stores. At n+1 the information that was on line it which has now been delayed by three bits by means of the three bit stores 26, 27 and 28 is recirculated through terminals 29, 30 and 31 to the input control. All subsequent lines of information are similarly delayed until the information which was on line 19 having been delayed by three bits now appears on line 20. Alternatively, data from row n can be deleted and the data can be moved up in a very similar manner simply by applying a three bit delay to the information being circulated in rows l to n and then when row n is in the three bit store, switching the recirculation control on again so that the n+1 information is immediately circulated into the bit store and the output from terminals 29, 30 and 31 is no longer applied through the input control to the recirculation control. This will leave a blank at line which then can be filled with new information if it is available from the input. This will leave all the information displaced in the stores, but this may be corrected by applying three extra clock pulses to all the bit stores simultaneously during a retrace period.

Other modifications to the display may be produced as follows. A character may be inserted in a line by displacing the information one character width by storing the output from the memory for subsequent characters in that line in a three bit store while inserting new information from the input point. Subsequent information in the stores relative to that line of information is then delayed by passing through the three bit stores and through the input control. Of course, if the line is already full, the end character will automatically be dropped off.

Any portion of the display may be erased at any time by inhibiting recirculation. This will permit erasure of lines or the whole display by controlling the recirculation.

Information can be stepped up in the display by the addition of clock pulses, three clock pulses being equal to one line roll-up. At the same time, the information in the first line must be inhibited by switching off the recirculation during the period it would normally be recirculated back into the stores. Similarly, line 20 can be dropped by inhibiting recirculation during the twentieth line and inhibiting three clock pulses to the memory during any retrace period.

As will be seen, the particular arrangement of data storage in the bit stores and the control of recirculation and character generation provides a very flexible manner of varying the display and this flexibility arises because of the relationship between the order of informa tion storage in the memory and the direction of display generation.

It will also be evident that while the initial loading process has not been described, it will correspond to the process used in adding new information except no old information will have to be dropped.

What I claim is:

1. A video display comprising horizontal rows of alpha-numeric symbols arranged in vertical columnar arrangement displayed on a cathode ray tube by means of intensity modulation of the beam of said cathode ray tube during selected period while said beam is deflected vertically at high speed and horizontally at a lower speed to produce a raster at a frame rate sufficiently high as to minimize flicker when directly viewed, means to receive information to be displayed in row order, a plurality of recirculating stores arranged to receive and recirculate the alpha numeric information in the form of binary code arranged sequentially in accordance with the columnar arrangement of the symbols to be displayed with the binary code for any one symbol being distributed amongst at least two stores and available simultaneously in parallel from the output of said stores, means to convert said parallel code into sequential video information to modulate said beam and thereby display said symbols.

2. A display as claimed in claim 1 wherein each frame comprises a plurality of interlaced fields and the number of fields per frame is equal to the maximum number of vertical lines in the raster required to display any symbol.

3. A display as claimed in claim 2 wherein the relative position of sequential fields on the face of the tube is adjustable whereby the raster consists of groups of vertical lines with variable spacing there between.

Claims (3)

1. A video display comprising horizontal rows of alpha-numeric symbols arranged in vertical columnar arrangement displayed on a cathode ray tube by means of intensity modulation of the beam of said cathode ray tube during selected period while said beam is deflected vertically at high speed and horizontally at a lower speed to produce a raster at a frame rate sufficiently high as to minimize flicker when directly viewed, means to receive information to be displayed in row order, a plurality of recirculating stores arranged to receive and recirculate the alpha numeric information in the form of binary code arranged sequentially in accordance with the columnar arrangement of the symbols to be displayed with the binary code for any one symbol being distributed amongst at least two stores and available simultaneously in parallel from the output of said stores, means to convert said parallel code into sequential video information to modulate said beam and thereby display said symbols.

2. A display as claimed in claim 1 wherein each frame comprises a plurality of interlaced fields and the number of fields per frame is equal to the maximum number of vertical lines in the raster required to display any symbol.

3. A display as claimed in claim 2 wherein the relative position of sequential fields on the face of the tube is adjustable whereby the raster consists of groups of vertical lines with variable spacing there between.

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