US3916109A - Stereo demodulating circuits and method of demodulation - Google Patents

Stereo demodulating circuits and method of demodulation Download PDF

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US3916109A
US3916109A US455841A US45584174A US3916109A US 3916109 A US3916109 A US 3916109A US 455841 A US455841 A US 455841A US 45584174 A US45584174 A US 45584174A US 3916109 A US3916109 A US 3916109A
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signal
electrode
electron control
control means
stereo
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Michael J Gay
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Motorola Solutions Inc
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Motorola Inc
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Priority to JP3706275A priority patent/JPS5513658B2/ja
Priority to FR7510021A priority patent/FR2266372B1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2227—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using switches for the decoding

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  • a plurality of stereo demodulator circuits are disclosed which are suitable for providing left channel and right channel stereo signals in response to a composite stereo signal and a stereo decoding signal.
  • Each of the demodulator circuits includes a multiplier circuit which operates in cooperation with a summing circuit.
  • Each demodulator circuit configuration enables a monaural signal to be applied through the summing circuit with no significant distortion. Moreover, undesirable transient signals due to initiation or termination of the stereo decoding signal are severely attenuated.
  • the various demodulator configurations are suitable for operation by either a single phase binary stereo demodulating signal, two binary stereo demodulating signals or three level stereo demodulating signals. A novel method of demodulation is also disclosed.
  • composite stereophonic signals are transmitted in the United States and in foreign countries to provide entertainment. These signals are designed to facilitate compatible monaural and stereophonic reception in PM receivers.
  • the composite stereo signal is defined as including a main channel summation signal, a continuous wave pilot signal, and a subchannel double sideband signal. More specifically, a left audio source and a right audio source, e.g., a disc recording or magnetic tap, which may be located at a transmitter, respectively provide a left (L) and a right (R) channel stereo signal.
  • the two signals are applied to a linear matrix which provides a main channel signal which is equal to the sum of the left and right signals (L R) and a subchannel signal which is equal to the difference between the left and right signals (L R).
  • the (L R) signals have frequencies ranging between approximately 50 Hz and kilohertz (kHz).
  • the subchannel signal is applied along with a 38 kilohertz subcarrier to a balanced modulator, which produces a double sideband, suppressed carrier output signal comprising the subchannel sideband signal.
  • the main channel signal, the subchannel sideband signal and a pilot carrier are then added together and transmitted as an FM modulation on a station carrier whose frequency is between 88 and 108 megahertz.
  • Monaural type receivers then select and demodulate the main channel signal to provide monaural reception.
  • stereophonic receivers select and demodulate a combination of the main channel and subchannel sideband signals to provide left and right stereo output signals.
  • the foregoing multiplication is generally performed only if the received signal is indeed a stereo encoded signal and if it is of sufficient amplitude. This is because the multiplying process can translate some of the high frequency noise occurring in the FM detected 7 spectrum into the audio frequency band thereby degrading the signal noise ratio of the receiver.
  • stereo-mute circuitry which detects the presence of an adequate stereo signal and which suppresses the multiplication process in the absence of an adequate level of such a signal.
  • a transient signal is produced whenever the multiplication process is initiated and terminated. These transients result in audible clicks which often have magnitudes comparable with the magnitude of the left and right stereo signals and hence can cause unde- 2 sirable sounds to occur at the loudspeakers of the stereophonic system.
  • a further problem is created by some prior art demodulators. More specifically, while the multiplication process is inhibited, the received signal tends to pass through transistors of prior art demodulator circuits. This is because even though the demodulator circuit is disabled, the transistors thereof are often biased in an intermediate state between saturation and nonconduction. Consequently, a significant unbalance can result between the output signals of the stereo demodulator circuit and these signals can also be distorted.
  • the foregoing problems it is possible to solve the foregoing problems by carefully choosing components such as transistors and biasing resistors so that perfect balance is obtained in the demodulator circuit.
  • This technique is costly and incompatible with the present trend toward providing stereo demodulators either at consumer prices or in integrated circuit form. More particularly, present day integrated circuit processes provide transistors and resistors having parameter values that extend over certain tolerance ranges. Hence, because of the variations in the process of manufacture, devices which are intended to have identical parameters in a particular circuit can have parameters which in reality are somewhat different.
  • Another object of this invention is to provide a stereo demodulator circuit which is suitable for manufacture in integrated circuit form.
  • Still another object of this invention is to provide a stereo demodulator circuit which is capable of being enabled and disabled without creating undesirable transient signals which could result in undesirable audio sounds.
  • a further object is to provide a stereo demodulator circuit configuration which does not provide an undesirable amount of distortion to a monaural signal being passed therethrough.
  • a further object is to provide a stereo demodulator circuit configuration which has improved match between monaural signal levels occurring at the output terminals of the demodulator.
  • a still further object is to provide a stereo demodulator circuit configuration which is adaptable to be operated by single phase, antiphase and three-level stereo demodulating signals.
  • the stereo demodulator circuit configurations and method of demodulation of the invention are suitable for providing left channel and right channel stereo signals in response to a composite stereo signal and a stereo decoding signal. Moreover, these demodulator circuits provide only insignificant distortion or imbalance to monaural signals passed therethrough.
  • the demodulator circuit includes a multiplier circuit and a summing circuit.
  • the multiplier circuit has input terminals to which the composite stereo and stereo decoding signals are applied and output terminals at which a subchannel signal is developed.
  • the summing circuit includes first and second portions having a pair of input terminals connected to receive the subchannel signal from the multiplier and another pair of input terminals connected to receive the composite signal.
  • the first portion of the summing circuit responds to the subchannel and composite signals to provide the left channel stereo signal at an output terminal thereof.
  • the second portion of the summing circuit develops the negative of the subchannel signal and adds it to the composite stereo signal to provide the right channel stereo signal at an output terminal thereof.
  • the summing circuit is adapted to provide a monaural signal at the output terminals of both portions thereof if the multiplying circuit is disabled in response to the nonexistence of an adequate stereo signal.
  • Various modifications of the stereo demodulator circuitry of the invention render it suitable for utilizing either a binary or two-level stereo decoding signal, two antiphase binary stereo decoding signals or a tri-level stereo decoding signal. All of the configurations of the demodulator circuit of the invention have the advantage that the output signal quality is not deleteriously affected by the multiplier being enabled and disabled.
  • FIG. 1 is a block diagram of a stereophonic receiver including a prior art stereo demodulating circuit shown in schematic form;
  • FIG. 2 is a partial block and partial schematic diagram illustrating a stereo demodulator circuit of one embodiment of the invention
  • FIG. 3 is a partial block and partial schematic diagram illustrating the stereo demodulator circuit of another embodiment of the invention.
  • FIG. 4 is a partial block and partial schematic diagram illustrating a stereo demodulator circuit of still another embodiment of the invention.
  • FIG. 1 there is shown a stereophonic multiplex receiver including a prior art demodulator circuit in the form of an integrated circuit which is enclosed by dotted lines.
  • a frequency modulated (FM) carrier wave contains a main channel or sum signal of the left and right audio signals (L R), a subchannel or difference signal of the left and right audio signals (L R), which is amplitude modulated on a suppressed subcarrier wave, and a pilot signal having a frequency one half that of the suppressed subcarrier frequency.
  • This wave is received by antenna and is applied to receiver front end circuit 11 which includes an RF amplifier, converter, IF amplifier and limiter which may all be of designs well known in the art.
  • the output of circuit 11 is then supplied to an FM detector and preamplifier circuit 12 where the composite stereo signal is detected.
  • the 19 kc. pilot component is then separated by 19 kc. signal separating circuit 13, which may include a filter circuit tuned to the 19 kc. signal frequencyf
  • the output of the 19 kc. signal separator is supplied to fre- 4 quency doubler 14 which reconstructs the suppressed subcarrier 38 kc. signal, which is defined as the "stereo decoding signal.
  • the frequency doubler 14 should be of a type which provides a symmetrical output signal in order to provide the best possible SCA, or storecast, rejection in the system with which it is used.
  • the composite stereo signal is supplied from the output terminal of detector and preamplifier stage 12 over a lead 16, through coupling resistor 17 to the base of an input NPN transistor 18 and to audio mute circuit 23 which shorts the base of transistor 18 to ac. ground in response to the magnitude of the FM signal decreasing below a predetermined threshold.
  • a stable direct current collector potential for transistor 18 is obtained from voltage reference string 20.
  • Transistor 18 is operated as an emitter follower and the composite stereo signals present across its emitter resistor 19 are applied to the base of a first demodulator input transistor 22.
  • the collector of the transistor 22 is connected to the emitters of a pair of transistors 24 and 26 which are operated as a first gated synchronous demodulator 28.
  • the 38 kc. stereo decoding signal obtained from the output of frequency doubler circuit 14 provides gating signals for demodulator 28.
  • the base of the transistor 26 is supplied with a constant d.c. reference potential through lead 30.
  • the operation of the demodulator circuit 28 is such that the 38 kc. gating signal applied thereto from frequency doubler circuit 14 is effective on each cycle to alternately render transistors 24 and 26 conductive and nonconductive. Transistor 26 is cut off, due to the differential action of the transistors 24 and 26, when transistor 24 is driven to conduction and vice versa.
  • transistor 22 is operated Class A so that the composite stereo signals present at the collector of the transistor 22 are coupled through the fully turned on transistor 24 or 26 to corresponding output terminals 32 or 34.
  • Right and left audio frequency amplifiers 36 and 38 are connected to output terminals 32 and 34 and amplify the demodulated stereo signals developed across load resistors 40 and 41 which are connected to output terminals 32 and 34.
  • the output terminals of amplifiers 36 and 38 are coupled to loudspeakers 40 and 44.
  • the 38 kc. stereo decoding signal from frequency doubler 14 gates demodulator transistors 24 and 26 to separate the R signal components from the L signal components.
  • Synchronous demodulator 28 produces a substantially equal and predictable amount of undesirable crosstalk at each of the output terminals 32 and 34.
  • a second synchronous demodulator 46 is provided and includes a second pair of switching transistors 48 and 50 which correspond to transistors 24 and 26 in demodulator 28.
  • the emitters of the transistors 48 and 50 are supplied with signals from the collector of a second demodulator input transistor 52, the base of which is connected to a source of direct current reference potential obtained from the bias string 20.
  • Input signals for driving second demodulator input transistor 52 are coupled to the emitter thereof through a resistive T network consisting of resistors 54, 56 and 58.
  • This resistor network applies the composite stereo signal in attenuated form to the emitter of the transistor 52.
  • the values of resistors 54, 56 and 58 are chosen to provide a predetermined amount of attenuation which causes the L and R signals appearing at the collectors of transistors 48 and 50 to be equal in magnitude and opposite in polarity to the crosstalk signal components appearing at the collectors of transistors 24 and 26.
  • the crosstalk is attenuated as explained in the aforementioned patent. If transistors 24, 26, 48 and 50 could be closely matched, the composite stereo signal or monaural signal appearing at nodes 32 and 34 would have equal amplitudes. Audio frequency amplifiers 36 and 38 would then produce equal drive signals of equal amplitudes for speakers 40 and 44, respectively.
  • transistor pairs 24 and 26 and 48 and 50 do not have identical parameters.
  • In monaural operation when no switching or stereo decoding signals are applied from frequency doubler 14 to demodulator 21, uneven current sharing. results between transistor pairs 24 and 26 and 48 and 50. This causes an undesirable unbalance of both the a.c. and d.c. components of the output currents at output terminals 32 and 34.
  • the amount of unbalance of current sharing between transistor pairs 48 and 50 and 24 and 26 is a function of the level of the magnitude currents conducted by transistors 22 and 52. This nonlinearity produces distortion in the demodulator output currents.
  • the monaural signals supplied to the left audio amplifier 38 and to the right audio amplifier 36 are of unequal amplitudes and are distorted.
  • this unbalance and distortion under monaural operation somewhat decreases the attractiveness of circuit 21 for use in high fidelity stereo receivers.
  • a bias potential is applied to the bases of transistors 24 and 48 by frequency doubler 14.
  • the bias from doubler 14 has a magnitude equal to the bias from circuit 20. Because of the unbalanced conditions within the demodulator, a transient is created by the resulting difference in d.c. potentials at nodes 32 and 34 as the demodulator changes from the balanced stereo condition to the unbalanced monaural condition. Similar transients occur when multiplication is reinitiated. These transients have significant magnitudes as compared to the magnitudes of the recovered audio signals. Thus, these transient responses can create undesired noise or audible clicks in speakers 40 and 44 as the demodulator changes back and forth between its monaural and stereo nodes of operation.
  • FIG. 2 illustrates a stereo demodulator of one embodiment of the invention which eliminates or reduces the preceding problems and which could replace demodulator 21 in the receiver of FIG. 1.
  • the composite stereo or monaural signals are applied by FM detector 12 or some other signal supply, shown schematically by generator 74 through coupling resistors 76 and 78 to terminals 86 and 88. These signals are also applied to resistors 92 and 94 by conductors 91 and 93.
  • the two multiplier or chopper transistors 80 and 82 are connected between bias terminal 84 and terminals 86 and 88, respectively. Transistors 80 and 82 may be operated in the inverted mode in order to obtain low offset collector-to-emitter voltages during conductive operation.
  • Bias terminal 84 is adapted to receive a constant d.c. potential from a supply of known configuration.
  • Transistors 80 and 82 are switched between on and off conditions by two antiphase 38 kHz stereo decoding signals applied to the bases thereof by frequency doubler 14, for instance. Because of the phase relationship between the 38 kHz stereo decoding signals, one of chopper transistors or 82 is in an on state while the other chopper transistor is in an off state. If chopper transistor 80 is in the on condition, terminal 86 is connected to bias terminal 84. Since terminal 84 provides an a.c. ground, the composite'stereo signal does not appear at terminal 86. Simultaneously, the composite stereo signal does appear at terminal 88 because multiplying transistor 82 is in an off condition. During the next half cycle of the stereo decoding signals, transistor 80 is rendered nonconductive and transistor 82 is conductive.
  • a differential signal comprising the subchannel (L R) information is developed between terminals 86 and 88.
  • the differential subchannel (L R) signals are applied to the bases of transistors 108 and 110 of differential amplifier 90.
  • This subchannel information is then amplified by differential amplifier 90 providing in phase and antiphase subchannel (L R) information components at nodes and 97 which are connected to collector resistors 92 and 94.
  • the left minus right signal (L R) or subchannel signal and the negative of the left minus right signals (L R) or inverted subchannel signal are matrixed with the main channel signal conducted by resistors 92 and 94 at nodes 95 and 97.
  • transistors 80 and 82 are each held in either an open or short circuit state by, for instance, frequency doubler 14.
  • the short circuit state is preferred because it causes the voltages at the emitters of transistors 86 and 88 to be defined with greater precision. These emitter voltages are the input voltages of the summing circuit.
  • no subchannel differential signals are impressed between the bases of differential transistors 108 and 110. Therefore, no subchannel information appears at the outputs of differential amplifier 90.
  • the composite stereo signal or monaural signal supplied by generator 74 is applied through resistors 92 and 94 to the input terminals of current amplifiers 98 and 96.
  • the monaural balance in the circuit of FIG. 2 is a function of the value resistors 92 and 94, which can be matched to a high degree during the process of manufacture. Also since resistors 92 and 94 have linear transfer chracteristics, they contribute virtually no distortion to a monaural signal even if mismatched a small amount.
  • stereo decoding signals used therewith can be of different phase or form provided that their d.c. components are equal.
  • this demodulator circuit can be driven by 38 kHz fifty percent duty cycle square wave stereo decoding signals displaced by 60 which thereby provide cancellation of the third harmonic of the stereo decoding signal, as described in the aforementioned patent application.
  • FIGS. 3 and 4 the same reference numbers are used for components corresponding to like compo nents of FIG. 2.
  • the structure of the circuit of FIG. 3 is the same as FIG. 2 except that transistor 83 has a conductivity which is opposite to the conductivity of transistor 80 and the bases of transistors 80 and 83 are connected together.
  • transistor 83 has a conductivity which is opposite to the conductivity of transistor 80 and the bases of transistors 80 and 83 are connected together.
  • the circuit of FIG. 3 can operate as a three-level multiplier to eliminate undesired responses to signals around 114 kHz. Otherwise, the circuit of FIG. 3 functions identically to that of FIG. 2.
  • the circuit of FIG. 3 is adapted to tri-level multiplier operation because it requires only one tri-level drive signal whereas the circuit of FIG. 2 would require two separate tri-level drive signals to eliminate the undesired 114 kHz response.
  • the configuration of the circuit of FIG. 4 differs from the configuration of the circuit of FIG. 2 in that resistor 104 is exchanged for current source 91 and the output terminal of composite stereo supply 74 is not directly connected to collector resistors 92 and 94. Also, collector resistors 92 and 94 are connected to bias conductor 111.
  • the matrix summing of the main and subchannel signals is accomplished in the output circuits of differential amplifier 90.
  • the matrix summing occurs in the emitter circuit of differential amplifier 90. More specifically, during stereo operation, the composite stereo signals from generator 74 are multiplied by the stereo decoding signals gated through transistors 80 and 82 to derive the differential subchannel (L R) signals that are impressed onto the bases of transistors 108 and 110 of amplifier 90.
  • L R differential subchannel
  • subchannel (L R) information is then amplified by differential amplifier to provide in phase and antiphase subchannel (L R) information components at the collectors of transistors 108 and 110.
  • the main channel (L R) information of the composite stereo signal which is applied as a common mode input, appears in phase on the bases of transistors 108 and 110 and across resistor 104 to produce a common mode current signal at node 106. This common mode current is divided equally between transistors 108 and 110 and creates in phase main channel collector outputs.
  • the common mode (L R) signals are added at node 106 to the subchannel signals, (L R), and to the inverted subchannel signals, (L R). to cause the left channel and right channel stereo output signals at output terminals 112 and 114 of differential amplifier 90.
  • chopper transistors 80 and 82 During monaural operation, chopper transistors 80 and 82 must be held in an off condition by the driving circuit thereby enabling the main channel (L R) information to be applied to the input terminals of differential amplifier 90.
  • the amplified monaural information occurs at output terminals 112 and 114.
  • a stereo decoding signal is first derived, for instance, by blocks 13 and 14 of FIG. 1 or by the systems described in the aforementioned related patent application.
  • the composite stereo signal is multiplied by the stereo decoding signal in the multiplier by transistor 80 and either transistor 82 or 83 to form a subchannel signal at the bases of transistors 108 and 110 of differential amplifier 90.
  • Transistor 108 amplifies the non-inverted subchannel signal which is then added to the composite stereo signal to form a left channel output stereo signal.
  • Transistor 110 provides an inverted subchannel signal which is added to the composite stereo signal to form a right channel stereo signal.
  • the demodulator circuit configurations of FIGS. 2 and 3 do not provide an undesirable amount of distortion to a monaural signal being passed therethrough because this signal is conducted through a resistive network rather than through active transistors.
  • negative feedback is employed in all of the demodulator configurations to reduce distortion.
  • the resistive networks and negative feedback tend to prevent undesirable transients from being created as the stereo decoding signal is applied and removed from the demodulator circuit.
  • the stereo demodulator circuit configurations provide improved match between monaural signal levels occurring at the output terminals of the de modulator and are flexible enough to be operated by single phase, multiphase and three-level stereo demodulating signals. All of the disclosed circuit configurations utilize the same method of demodulation which is described above.
  • first signal supply means having first and second output terminals for providing monaural and composite stereo signals
  • second signal supply means adapted to provide a stereo decoding signal
  • multiplier means for multiplying said composite stereo signal with said stereo decoding signal to derive a differential subchannel signal at first and second output terminals thereof, said multiplier means being operatively coupled to said first and second signal supply means;
  • summing means for deriving said left and right channel stereo signals at first and second output terminals respectively in response to said differential subchannel signal from said multiplier means and said composite signal from said first signal supply means, said summing means having first, second and third input terminals, said first and second input terminals being respectively coupled to said output terminals of said multiplier means and said third input terminal being coupled to said first output terminal of said first signal supply means, said summing means also being responsive to the existence of only said monaural signal to provide said monaural signal in a substantially undistorted form at said output terminals thereof.
  • third supply means adapted to produce a bias supply at an output terminal thereof, said output terminal being coupled to said second output terminal of said first signal supply means;
  • first electron control means having first, second and third electrodes, said first electrode being coupled to said first input terminal of said summing means, said second electrode being connected to said second signal supply means, said third electrode being connected to said third supply means;
  • first circuit means coupling said first output terminal of said first signal supply means to said first electrode of said first electron control means
  • second electron control means having first, second and third electrodes, said first electrode of said second electron control means being coupled to said second input terminal of said summing means, said second electrode of said second electron control means being connected to said second signal supply means and said third electrode of said second electron control means being connected to said third supply means;
  • second circuit means coupling said first output terminal of said first signal supply means to said first electrode of said second electron control means.
  • said first electron control means includes a first bipolar transistor of a first polarity type
  • said second electron control means includes a second bipolar transistor also of said first polarity type.
  • said first electron control means includes a bipolar transistor of a first polarity type
  • said second electron control means includes a bipolar transistor of a second polarity type.
  • first electron control means having first, second and third electrodes, said second electrode being connected to said first input terminal of said summing means; third circuit means connecting said third electrode to said third input terminal of said summing means;
  • second electron control means having first, second and third electrodes, said second electrode of said second electron control means being connected to said second input terminal of said summing means, said first electrode of said second electron control means being coupled to said current supply means;
  • fourth circuit means connecting said third electrode of said second electron control means to said third input terminal of said summing means, said third electrodes of said first and second electron control means providing said first and second output terminals for the stereo demodulating circuit.
  • multiplier means having first and second input terminals and first and second output terminals, said first input terminal being adapted to receive the stereo decoding signal, said second input terminal being adapted to receive the composite stereo signal, said multiplier means providing a subchannel stereo signal between said output terminals thereof;
  • first summing portion having first and second input terminals and an output terminal, said first input terminal of said first summing portion being connected to said first output terminal of said multiplier means, said second input terminal of said first summing portion being adapted to receive said composite stereo signal; said first summing portion being responsive to said subchannel signal and the composite stereo signal to provide the left channel stereo signal at said output terminal thereof;
  • said first summing means including first electron control means having a first electrode, a second electrode and a third electrode, said second electrode being connected to said first input terminal of said first summing portion, and said third electrode being coupled to said output terminal of said first summing portion, first resistive means connecting said third electrode to said second input terminal of said first summing portion, current supply means, second resistive means connecting said first electrode of said first electron control means to said current supply means; and
  • first electron control means having first, second and third electrodes, said first electrode being connected to said first input terminal of said first summing portion, said second electrode being adapted to receive the stereo decoding signal and said third electrode being adapted to receive a bias potential;
  • second electron control means having first, second and third electrodes, said first electrode of said second electron control means being connected to said first input terminal of said second summing portion, said second electrode of said second electron control means being adapted to receive the stereo decoding signal, said third electrode of said second electron control means being connected to said third electrode of said first electron control means, said third electrode of said second electron control means also being adapted to receive said bias voltage.
  • said multiplier means further includes:
  • said first electron control means includes a first bipolar transistor of a first conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said first electron control means; and said second electron control means includes a second bipolar transistor of said first conductivity type having emitter, base and collector electrodes respectively providing said first, second and third electrodes of said second electron control means.
  • said multiplier means further includes:
  • said first electron control means includes a bipolar transistor of a first conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said first electron control means;
  • said second electron control means includes a bipolar transistor of a second conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said second electron control means;
  • first circuit means coupling said base electrode of said first transistor to said base electrode of said second transistor, said first circuit means being adapted to apply said stereo demodulating signal to said base electrodes of said transistors; and second and third circuit means being adapted to apply said composite stereo signal to said emitter electrodes of said first and second transistors respectively.
  • said second summing portion further includes:
  • second electron control means having a first electrode, a second electrode, and a third electrode, said second electrode of said second electron control means being connected to said first input terminal of said second summing portion, and said third electrode of said second electron control means being connected to said output terminal of said second summing portion; third resistive means connecting said third electrode of said second electron control means to said secchannel and right channel stereo signals, including in combination:
  • first signal supply means adapted to provide monaural and composite stereo signals
  • second signal supply means adapted to provide a stereo decoding signal
  • multiplier means coupled to said first signal supply means and to said second signal supply means, said multiplier means being adapted to multiply said composite stereo signal and said stereo decoding signal together to provide a subchannel signal at first and second output terminals, said multiplier means including third supply means adapted to produce a bias supply at an output terminal thereof, first electron control means having first, second and third electrodes, said first electrode being coupled to said first output terminal of said multiplier means, said second electrode being connected to said second signal supply means, said third electrode being connected to said third supply means, first circuit means coupling said first signal supply means to said first electrode, second electron control means having first, second and third electrodes, said first electrode of said second electron control means being coupled to said second output terminal of said multiplier means, said second electrode of said second electron control means being connected to said second signal supply means, said third electrode of said second electron control means being connected to said third supply means, second circuit means coupling said first signal supply means to said first electrode of said second electron control means;
  • summing means being connected to said first and second output terminals of said multiplier means and receiving said subchannel signal and deriving an inverted subchannel signal;
  • said summing means being responsive to the existence of said composite stereo signal and said subchannel signal and said inverted subchannel signal to provide left channel and right channel stereo signals at output terminals thereof, said summing means also being responsive to the existence of only said monaural signal to provide said monaural signal in a substantially undistorted form at said output terminals thereof, said summing means including third electron control means having first, second and third electrodes, said second electrode being connected to said first output terminal of said multiplier means, fourth circuit means connecting said third electrode to said third circuit means, current supply means coupled to said first electrode, fourth electron control means having first, second and third electrodes, said second electrode of said fourth electron control means being connected to said second output terminal of said multiplier means, said first electrode of said fourth electron control means being coupled to said current supply means, fifth circuit means connecting said third electrode of said second electron control means to circuit.

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Abstract

A plurality of stereo demodulator circuits are disclosed which are suitable for providing left channel and right channel stereo signals in response to a composite stereo signal and a stereo decoding signal. Each of the demodulator circuits includes a multiplier circuit which operates in cooperation with a summing circuit. Each demodulator circuit configuration enables a monaural signal to be applied through the summing circuit with no significant distortion. Moreover, undesirable transient signals due to initiation or termination of the stereo decoding signal are severely attenuated. The various demodulator configurations are suitable for operation by either a single phase binary stereo demodulating signal, two binary stereo demodulating signals or three level stereo demodulating signals. A novel method of demodulation is also disclosed.

Description

United States Patent [191 Gay [ 1 Oct. 28, 1975 STEREO DEMODULATING CIRCUITS AND METHOD OF DEMODULATION [75] inventor: Michael J. Gay, Geneva,
Switzerland [73] Assignee: Motorola, Inc., Chicago, Ill.
[22] Filed: Mar. 28, 1974 [21] Appl. No.: 455,841
Primary ExaminerDouglas W. Olms Attorney, Agent, or Firm-Harry M. Weiss; Michael D. Bingham; Maurice J. Jones [57] ABSTRACT A plurality of stereo demodulator circuits are disclosed which are suitable for providing left channel and right channel stereo signals in response to a composite stereo signal and a stereo decoding signal. Each of the demodulator circuits includes a multiplier circuit which operates in cooperation with a summing circuit. Each demodulator circuit configuration enables a monaural signal to be applied through the summing circuit with no significant distortion. Moreover, undesirable transient signals due to initiation or termination of the stereo decoding signal are severely attenuated. The various demodulator configurations are suitable for operation by either a single phase binary stereo demodulating signal, two binary stereo demodulating signals or three level stereo demodulating signals. A novel method of demodulation is also disclosed.
11 Claims, 4 Drawing Figures CURRENT AMPLIFIERS US. Patent 0a. 28, 1975 Sheet 1 of 2 3,916,109
US. Patent Oct. 28, 1975 Sheet 2 of2 3,916,109
CURRENT AMPLIFIERS OUTPUTS I00 I06 I02 Fig.4
38 kHz SIGNALS STEREO DEMODUL'ATING CIRCUITS AND METHOD OF DEMODULATION CROSS REFERENCE TO A RELATED APPLICATION AND PATENT The subject matter of the subject invention is related to the subject matter of US. Pat. No. 3,617,641, entitled Stereo Multiplexing Demodulator, by James H.
BACKGROUND OF THE INVENTION At present, composite stereophonic signals are transmitted in the United States and in foreign countries to provide entertainment. These signals are designed to facilitate compatible monaural and stereophonic reception in PM receivers. The composite stereo signal is defined as including a main channel summation signal, a continuous wave pilot signal, and a subchannel double sideband signal. More specifically, a left audio source and a right audio source, e.g., a disc recording or magnetic tap, which may be located at a transmitter, respectively provide a left (L) and a right (R) channel stereo signal. These two signals are applied to a linear matrix which provides a main channel signal which is equal to the sum of the left and right signals (L R) and a subchannel signal which is equal to the difference between the left and right signals (L R). In this system, the (L R) signals have frequencies ranging between approximately 50 Hz and kilohertz (kHz). The subchannel signal is applied along with a 38 kilohertz subcarrier to a balanced modulator, which produces a double sideband, suppressed carrier output signal comprising the subchannel sideband signal. The main channel signal, the subchannel sideband signal and a pilot carrier are then added together and transmitted as an FM modulation on a station carrier whose frequency is between 88 and 108 megahertz.
Monaural type receivers then select and demodulate the main channel signal to provide monaural reception. Alternatively, stereophonic receivers select and demodulate a combination of the main channel and subchannel sideband signals to provide left and right stereo output signals. To provide this function, it is sometimes necessary to multiply the subchannel sidebands with a 38 kilohertz signal which is phase related to the 19 kilohertz pilot signal. The foregoing multiplication is generally performed only if the received signal is indeed a stereo encoded signal and if it is of sufficient amplitude. This is because the multiplying process can translate some of the high frequency noise occurring in the FM detected 7 spectrum into the audio frequency band thereby degrading the signal noise ratio of the receiver.
Thus, modern stereophonic receivers are equipped with stereo-mute circuitry, which detects the presence of an adequate stereo signal and which suppresses the multiplication process in the absence of an adequate level of such a signal. Unfortunately, because of the configuration of some present day stereo demodulator circuits, a transient signal is produced whenever the multiplication process is initiated and terminated. These transients result in audible clicks which often have magnitudes comparable with the magnitude of the left and right stereo signals and hence can cause unde- 2 sirable sounds to occur at the loudspeakers of the stereophonic system.
A further problem is created by some prior art demodulators. More specifically, while the multiplication process is inhibited, the received signal tends to pass through transistors of prior art demodulator circuits. This is because even though the demodulator circuit is disabled, the transistors thereof are often biased in an intermediate state between saturation and nonconduction. Consequently, a significant unbalance can result between the output signals of the stereo demodulator circuit and these signals can also be distorted. In discrete circuits, it is possible to solve the foregoing problems by carefully choosing components such as transistors and biasing resistors so that perfect balance is obtained in the demodulator circuit. This technique is costly and incompatible with the present trend toward providing stereo demodulators either at consumer prices or in integrated circuit form. More particularly, present day integrated circuit processes provide transistors and resistors having parameter values that extend over certain tolerance ranges. Hence, because of the variations in the process of manufacture, devices which are intended to have identical parameters in a particular circuit can have parameters which in reality are somewhat different.
A need exists to develop a solution to the problems caused by transient signals, imbalances and distortions generated by prior art demodulator circuits due to the component tolerances of said circuits. Morover, some prior art demodulator configurations are not flexible enough to be operated by a variety of stereo decoding signals.
SUMMARY OF THE INVENTION It is an object of this invention to provide an improved demodulator circuit and method of demodulation.
Another object of this invention is to provide a stereo demodulator circuit which is suitable for manufacture in integrated circuit form.
Still another object of this invention is to provide a stereo demodulator circuit which is capable of being enabled and disabled without creating undesirable transient signals which could result in undesirable audio sounds.
A further object is to provide a stereo demodulator circuit configuration which does not provide an undesirable amount of distortion to a monaural signal being passed therethrough.
A further object is to provide a stereo demodulator circuit configuration which has improved match between monaural signal levels occurring at the output terminals of the demodulator.
A still further object is to provide a stereo demodulator circuit configuration which is adaptable to be operated by single phase, antiphase and three-level stereo demodulating signals.
The stereo demodulator circuit configurations and method of demodulation of the invention are suitable for providing left channel and right channel stereo signals in response to a composite stereo signal and a stereo decoding signal. Moreover, these demodulator circuits provide only insignificant distortion or imbalance to monaural signals passed therethrough. The demodulator circuit includes a multiplier circuit and a summing circuit. The multiplier circuit has input terminals to which the composite stereo and stereo decoding signals are applied and output terminals at which a subchannel signal is developed. The summing circuit includes first and second portions having a pair of input terminals connected to receive the subchannel signal from the multiplier and another pair of input terminals connected to receive the composite signal. The first portion of the summing circuit responds to the subchannel and composite signals to provide the left channel stereo signal at an output terminal thereof. The second portion of the summing circuit develops the negative of the subchannel signal and adds it to the composite stereo signal to provide the right channel stereo signal at an output terminal thereof. The summing circuit is adapted to provide a monaural signal at the output terminals of both portions thereof if the multiplying circuit is disabled in response to the nonexistence of an adequate stereo signal. Various modifications of the stereo demodulator circuitry of the invention render it suitable for utilizing either a binary or two-level stereo decoding signal, two antiphase binary stereo decoding signals or a tri-level stereo decoding signal. All of the configurations of the demodulator circuit of the invention have the advantage that the output signal quality is not deleteriously affected by the multiplier being enabled and disabled.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a stereophonic receiver including a prior art stereo demodulating circuit shown in schematic form;
FIG. 2 is a partial block and partial schematic diagram illustrating a stereo demodulator circuit of one embodiment of the invention;
FIG. 3 is a partial block and partial schematic diagram illustrating the stereo demodulator circuit of another embodiment of the invention; and
FIG. 4 is a partial block and partial schematic diagram illustrating a stereo demodulator circuit of still another embodiment of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A stereophonic receiver will first be described. Then a prior art demodulator circuit will be described along with some of the problems therewith so that the advantages of the demodulator circuit structures of the present invention can be more fully appreciated. Referring to FIG. 1, there is shown a stereophonic multiplex receiver including a prior art demodulator circuit in the form of an integrated circuit which is enclosed by dotted lines. A frequency modulated (FM) carrier wave contains a main channel or sum signal of the left and right audio signals (L R), a subchannel or difference signal of the left and right audio signals (L R), which is amplitude modulated on a suppressed subcarrier wave, and a pilot signal having a frequency one half that of the suppressed subcarrier frequency. This wave is received by antenna and is applied to receiver front end circuit 11 which includes an RF amplifier, converter, IF amplifier and limiter which may all be of designs well known in the art. The output of circuit 11 is then supplied to an FM detector and preamplifier circuit 12 where the composite stereo signal is detected.
When stereophonic signals are detected by detector 12, the 19 kc. pilot component is then separated by 19 kc. signal separating circuit 13, which may include a filter circuit tuned to the 19 kc. signal frequencyfThe output of the 19 kc. signal separator is supplied to fre- 4 quency doubler 14 which reconstructs the suppressed subcarrier 38 kc. signal, which is defined as the "stereo decoding signal. The frequency doubler 14 should be ofa type which provides a symmetrical output signal in order to provide the best possible SCA, or storecast, rejection in the system with which it is used.
The composite stereo signal is supplied from the output terminal of detector and preamplifier stage 12 over a lead 16, through coupling resistor 17 to the base of an input NPN transistor 18 and to audio mute circuit 23 which shorts the base of transistor 18 to ac. ground in response to the magnitude of the FM signal decreasing below a predetermined threshold. A stable direct current collector potential for transistor 18 is obtained from voltage reference string 20.
Transistor 18 is operated as an emitter follower and the composite stereo signals present across its emitter resistor 19 are applied to the base of a first demodulator input transistor 22. The collector of the transistor 22 is connected to the emitters of a pair of transistors 24 and 26 which are operated as a first gated synchronous demodulator 28. The 38 kc. stereo decoding signal obtained from the output of frequency doubler circuit 14 provides gating signals for demodulator 28. The base of the transistor 26 is supplied with a constant d.c. reference potential through lead 30.
The operation of the demodulator circuit 28 is such that the 38 kc. gating signal applied thereto from frequency doubler circuit 14 is effective on each cycle to alternately render transistors 24 and 26 conductive and nonconductive. Transistor 26 is cut off, due to the differential action of the transistors 24 and 26, when transistor 24 is driven to conduction and vice versa. At the same time, transistor 22 is operated Class A so that the composite stereo signals present at the collector of the transistor 22 are coupled through the fully turned on transistor 24 or 26 to corresponding output terminals 32 or 34. Right and left audio frequency amplifiers 36 and 38 are connected to output terminals 32 and 34 and amplify the demodulated stereo signals developed across load resistors 40 and 41 which are connected to output terminals 32 and 34. The output terminals of amplifiers 36 and 38 are coupled to loudspeakers 40 and 44. Thus, the 38 kc. stereo decoding signal from frequency doubler 14, gates demodulator transistors 24 and 26 to separate the R signal components from the L signal components.
Synchronous demodulator 28 produces a substantially equal and predictable amount of undesirable crosstalk at each of the output terminals 32 and 34. To eliminate or substantially reduce the crosstalk present in the output signals of demodulator 28, a second synchronous demodulator 46 is provided and includes a second pair of switching transistors 48 and 50 which correspond to transistors 24 and 26 in demodulator 28. The emitters of the transistors 48 and 50 are supplied with signals from the collector of a second demodulator input transistor 52, the base of which is connected to a source of direct current reference potential obtained from the bias string 20. Input signals for driving second demodulator input transistor 52 are coupled to the emitter thereof through a resistive T network consisting of resistors 54, 56 and 58. This resistor network applies the composite stereo signal in attenuated form to the emitter of the transistor 52. The values of resistors 54, 56 and 58 are chosen to provide a predetermined amount of attenuation which causes the L and R signals appearing at the collectors of transistors 48 and 50 to be equal in magnitude and opposite in polarity to the crosstalk signal components appearing at the collectors of transistors 24 and 26. As a consequence, the crosstalk is attenuated as explained in the aforementioned patent. If transistors 24, 26, 48 and 50 could be closely matched, the composite stereo signal or monaural signal appearing at nodes 32 and 34 would have equal amplitudes. Audio frequency amplifiers 36 and 38 would then produce equal drive signals of equal amplitudes for speakers 40 and 44, respectively.
Due to process variations, transistor pairs 24 and 26 and 48 and 50 do not have identical parameters. In monaural operation, when no switching or stereo decoding signals are applied from frequency doubler 14 to demodulator 21, uneven current sharing. results between transistor pairs 24 and 26 and 48 and 50. This causes an undesirable unbalance of both the a.c. and d.c. components of the output currents at output terminals 32 and 34. In addition, the amount of unbalance of current sharing between transistor pairs 48 and 50 and 24 and 26 is a function of the level of the magnitude currents conducted by transistors 22 and 52. This nonlinearity produces distortion in the demodulator output currents. Thus, the monaural signals supplied to the left audio amplifier 38 and to the right audio amplifier 36 are of unequal amplitudes and are distorted. Thus, although demodulator 21 operates satisfactorily in many applications, this unbalance and distortion under monaural operation somewhat decreases the attractiveness of circuit 21 for use in high fidelity stereo receivers.
As the stereo decoding signal is inhibited by stereo mute circuit 15, a bias potential is applied to the bases of transistors 24 and 48 by frequency doubler 14. The bias from doubler 14 has a magnitude equal to the bias from circuit 20. Because of the unbalanced conditions within the demodulator, a transient is created by the resulting difference in d.c. potentials at nodes 32 and 34 as the demodulator changes from the balanced stereo condition to the unbalanced monaural condition. Similar transients occur when multiplication is reinitiated. These transients have significant magnitudes as compared to the magnitudes of the recovered audio signals. Thus, these transient responses can create undesired noise or audible clicks in speakers 40 and 44 as the demodulator changes back and forth between its monaural and stereo nodes of operation.
FIG. 2 illustrates a stereo demodulator of one embodiment of the invention which eliminates or reduces the preceding problems and which could replace demodulator 21 in the receiver of FIG. 1. The composite stereo or monaural signals are applied by FM detector 12 or some other signal supply, shown schematically by generator 74 through coupling resistors 76 and 78 to terminals 86 and 88. These signals are also applied to resistors 92 and 94 by conductors 91 and 93. The two multiplier or chopper transistors 80 and 82 are connected between bias terminal 84 and terminals 86 and 88, respectively. Transistors 80 and 82 may be operated in the inverted mode in order to obtain low offset collector-to-emitter voltages during conductive operation. Inverted mode simply means that the collector and emitter electrodes of the transistors are interchanged to cause the emitter electrode to perform the collector function and vice versa. Bias terminal 84 is adapted to receive a constant d.c. potential from a supply of known configuration.
Transistors 80 and 82 are switched between on and off conditions by two antiphase 38 kHz stereo decoding signals applied to the bases thereof by frequency doubler 14, for instance. Because of the phase relationship between the 38 kHz stereo decoding signals, one of chopper transistors or 82 is in an on state while the other chopper transistor is in an off state. If chopper transistor 80 is in the on condition, terminal 86 is connected to bias terminal 84. Since terminal 84 provides an a.c. ground, the composite'stereo signal does not appear at terminal 86. Simultaneously, the composite stereo signal does appear at terminal 88 because multiplying transistor 82 is in an off condition. During the next half cycle of the stereo decoding signals, transistor 80 is rendered nonconductive and transistor 82 is conductive. By multiplying the composite signal and the 38 kHz signal, a differential signal comprising the subchannel (L R) information is developed between terminals 86 and 88. The differential subchannel (L R) signals are applied to the bases of transistors 108 and 110 of differential amplifier 90. This subchannel information is then amplified by differential amplifier 90 providing in phase and antiphase subchannel (L R) information components at nodes and 97 which are connected to collector resistors 92 and 94. The left minus right signal (L R) or subchannel signal and the negative of the left minus right signals (L R) or inverted subchannel signal are matrixed with the main channel signal conducted by resistors 92 and 94 at nodes 95 and 97. This results in a left (L) channel signal at node 97 and a right (R) channel signal at node 95 which are supplied to current amplifiers 96 and 98. Current amplifiers 96 and 98 could be replaced by voltage amplifiers provided the appropriate voltage level shifts and gains are effected in order to prevent saturation of transistors 108 and 110 of differential amplifier 90.
To inhibit multiplication in response to weak stereophonic conditions or monaural conditions, transistors 80 and 82 are each held in either an open or short circuit state by, for instance, frequency doubler 14. The short circuit state is preferred because it causes the voltages at the emitters of transistors 86 and 88 to be defined with greater precision. These emitter voltages are the input voltages of the summing circuit. In the inhibited or disabled mode, no subchannel differential signals are impressed between the bases of differential transistors 108 and 110. Therefore, no subchannel information appears at the outputs of differential amplifier 90. The composite stereo signal or monaural signal supplied by generator 74 is applied through resistors 92 and 94 to the input terminals of current amplifiers 98 and 96.
One significant improvement provided by the embodiment of FIG. 2 over the prior art is the reduction of the imbalance between monaural signal levels developed at output terminals 112 and 114, which therefore minimizes the imbalance in the sound levels at speakers 40 and 44. The monaural balance in the circuit of FIG. 2 is a function of the value resistors 92 and 94, which can be matched to a high degree during the process of manufacture. Also since resistors 92 and 94 have linear transfer chracteristics, they contribute virtually no distortion to a monaural signal even if mismatched a small amount.
As an aside, if current amplifiers 96 and 98 are replaced by voltage amplifiers, the monaural signal from supply 74 will appear at nodes 95 and 97 with virtually no attenuation. Consequently, the monaural signal would be more nearly balanced and be less distorted.
7 However, the use of voltage amplifiers requires level shifting of the composite stereo signal to prevent saturation of transistors 108 and 110.
If a symmetrical stereo decoding signal is applied to transistors 80 and 82 of the circuit of FIG. 2, the transient responses that occur in prior art circuits during the process of switching between stereo and monaural reception are significantly reduced and become inaudible. More specifically, the dc. components at the collector of transistors 108 and 110 are nearly unaffected by the initiation and inhibition of the multiplier action. This is because any differential d.c. voltage change appearing between terminals 86 and 88 during switching between stereo and monaural operation as a result of process variations or imbalances between resistors 76 and 78 is severely degenerated by the negative feedback provided by emitter resistors 100 and 102.
Another significant advantage of the embodiment of FIG. 2 is that the stereo decoding signals used therewith can be of different phase or form provided that their d.c. components are equal. Thus, this demodulator circuit can be driven by 38 kHz fifty percent duty cycle square wave stereo decoding signals displaced by 60 which thereby provide cancellation of the third harmonic of the stereo decoding signal, as described in the aforementioned patent application.
In FIGS. 3 and 4, the same reference numbers are used for components corresponding to like compo nents of FIG. 2. The structure of the circuit of FIG. 3 is the same as FIG. 2 except that transistor 83 has a conductivity which is opposite to the conductivity of transistor 80 and the bases of transistors 80 and 83 are connected together. These differences enable the use of a three-level stereo decoding signal which can have low, reference and high levels. More particularly, if the stereo decoding signal is high, transistor 80 is rendered conductive and transistor 83 is nonconductive. If the stereo decoding signal is at a reference level, which is approximately equal in magnitude to the bias potential, neither transistor 80 nor 83 is conductive. If the stereo decoding signal is low," transistor 83 is conductive and transistor 80 is nonconductive. Therefore, the circuit of FIG. 3 can operate as a three-level multiplier to eliminate undesired responses to signals around 114 kHz. Otherwise, the circuit of FIG. 3 functions identically to that of FIG. 2. The circuit of FIG. 3 is adapted to tri-level multiplier operation because it requires only one tri-level drive signal whereas the circuit of FIG. 2 would require two separate tri-level drive signals to eliminate the undesired 114 kHz response.
The configuration of the circuit of FIG. 4 differs from the configuration of the circuit of FIG. 2 in that resistor 104 is exchanged for current source 91 and the output terminal of composite stereo supply 74 is not directly connected to collector resistors 92 and 94. Also, collector resistors 92 and 94 are connected to bias conductor 111.
In the previous embodiments of FIGS. 2 and 3, the matrix summing of the main and subchannel signals is accomplished in the output circuits of differential amplifier 90. However, in the embodiment of FIG. 4, the matrix summing occurs in the emitter circuit of differential amplifier 90. More specifically, during stereo operation, the composite stereo signals from generator 74 are multiplied by the stereo decoding signals gated through transistors 80 and 82 to derive the differential subchannel (L R) signals that are impressed onto the bases of transistors 108 and 110 of amplifier 90. The
subchannel (L R) information is then amplified by differential amplifier to provide in phase and antiphase subchannel (L R) information components at the collectors of transistors 108 and 110. The main channel (L R) information of the composite stereo signal, which is applied as a common mode input, appears in phase on the bases of transistors 108 and 110 and across resistor 104 to produce a common mode current signal at node 106. This common mode current is divided equally between transistors 108 and 110 and creates in phase main channel collector outputs. The common mode (L R) signals are added at node 106 to the subchannel signals, (L R), and to the inverted subchannel signals, (L R). to cause the left channel and right channel stereo output signals at output terminals 112 and 114 of differential amplifier 90.
During monaural operation, chopper transistors 80 and 82 must be held in an off condition by the driving circuit thereby enabling the main channel (L R) information to be applied to the input terminals of differential amplifier 90. The amplified monaural information occurs at output terminals 112 and 114.
Direct current differential voltage changes that appear between terminals 86 and 88 during switching from stereo operation to monaural operation as a result of process variations or imbalance between resistors 76 and 78 are severely degenerated by the negative feedback provided by resistors and 102.
The circuits of FIG. 2, FIG. 3, and FIG. 4 all utilize the same method of demodulation. More specifically, a stereo decoding signal is first derived, for instance, by blocks 13 and 14 of FIG. 1 or by the systems described in the aforementioned related patent application. The composite stereo signal is multiplied by the stereo decoding signal in the multiplier by transistor 80 and either transistor 82 or 83 to form a subchannel signal at the bases of transistors 108 and 110 of differential amplifier 90. Transistor 108 amplifies the non-inverted subchannel signal which is then added to the composite stereo signal to form a left channel output stereo signal. Transistor 110 provides an inverted subchannel signal which is added to the composite stereo signal to form a right channel stereo signal.
What has been described, therefore, are improved stereo demodulator circuits which are suitable for manufacture in integated circuit form. The demodulator circuit configurations of FIGS. 2 and 3 do not provide an undesirable amount of distortion to a monaural signal being passed therethrough because this signal is conducted through a resistive network rather than through active transistors. Moreover, negative feedback is employed in all of the demodulator configurations to reduce distortion. In addition, the resistive networks and negative feedback tend to prevent undesirable transients from being created as the stereo decoding signal is applied and removed from the demodulator circuit. Also, the stereo demodulator circuit configurations provide improved match between monaural signal levels occurring at the output terminals of the de modulator and are flexible enough to be operated by single phase, multiphase and three-level stereo demodulating signals. All of the disclosed circuit configurations utilize the same method of demodulation which is described above.
While the above-detailed description has shown, described and pointed out the fundamental novel features of the invention as applied to various embodiments, it
will be understood that various omissions, substitutions 9 and changes in the form and details of the circuits and methods illustrated may be made by those skilled in the art without departing from the spirit of the invention. it is the intention, therefore, to be limited only as indicated by the scope of the following claims I claim:
l. A demodulator circuit suitable for providing left channel and right channel stereo signals at output terminals thereof, including in combination:
first signal supply means having first and second output terminals for providing monaural and composite stereo signals;
second signal supply means adapted to provide a stereo decoding signal;
multiplier means for multiplying said composite stereo signal with said stereo decoding signal to derive a differential subchannel signal at first and second output terminals thereof, said multiplier means being operatively coupled to said first and second signal supply means; and
summing means for deriving said left and right channel stereo signals at first and second output terminals respectively in response to said differential subchannel signal from said multiplier means and said composite signal from said first signal supply means, said summing means having first, second and third input terminals, said first and second input terminals being respectively coupled to said output terminals of said multiplier means and said third input terminal being coupled to said first output terminal of said first signal supply means, said summing means also being responsive to the existence of only said monaural signal to provide said monaural signal in a substantially undistorted form at said output terminals thereof.
2. The stereo demodulator circuit of claim 1 wherein said multiplier means includes in combination:
third supply means adapted to produce a bias supply at an output terminal thereof, said output terminal being coupled to said second output terminal of said first signal supply means;
first electron control means having first, second and third electrodes, said first electrode being coupled to said first input terminal of said summing means, said second electrode being connected to said second signal supply means, said third electrode being connected to said third supply means;
first circuit means coupling said first output terminal of said first signal supply means to said first electrode of said first electron control means;
second electron control means having first, second and third electrodes, said first electrode of said second electron control means being coupled to said second input terminal of said summing means, said second electrode of said second electron control means being connected to said second signal supply means and said third electrode of said second electron control means being connected to said third supply means; and
second circuit means coupling said first output terminal of said first signal supply means to said first electrode of said second electron control means.
3. The stereo demodulator circuit of claim 2 wherein:
said first electron control means includes a first bipolar transistor of a first polarity type; and
said second electron control means includes a second bipolar transistor also of said first polarity type.
4. The demodulator circuit of claim 2 wherein:
said first electron control means includes a bipolar transistor of a first polarity type; and
said second electron control means includes a bipolar transistor of a second polarity type.
5. The stereo demodulator circuit of claim 2 wherein said summing means further includes in combination:
first electron control means having first, second and third electrodes, said second electrode being connected to said first input terminal of said summing means; third circuit means connecting said third electrode to said third input terminal of said summing means;
current supply means coupled to said first electrode;
second electron control means having first, second and third electrodes, said second electrode of said second electron control means being connected to said second input terminal of said summing means, said first electrode of said second electron control means being coupled to said current supply means; and
fourth circuit means connecting said third electrode of said second electron control means to said third input terminal of said summing means, said third electrodes of said first and second electron control means providing said first and second output terminals for the stereo demodulating circuit.
6. A monolithic stereo demodulator circuit suitable for providing left channel and right channel stereo signals in response to a composite stereo signal and a stereo decoding signal, the demodulator circuit including in combination:
multiplier means having first and second input terminals and first and second output terminals, said first input terminal being adapted to receive the stereo decoding signal, said second input terminal being adapted to receive the composite stereo signal, said multiplier means providing a subchannel stereo signal between said output terminals thereof;
first summing portion having first and second input terminals and an output terminal, said first input terminal of said first summing portion being connected to said first output terminal of said multiplier means, said second input terminal of said first summing portion being adapted to receive said composite stereo signal; said first summing portion being responsive to said subchannel signal and the composite stereo signal to provide the left channel stereo signal at said output terminal thereof;
said first summing means including first electron control means having a first electrode, a second electrode and a third electrode, said second electrode being connected to said first input terminal of said first summing portion, and said third electrode being coupled to said output terminal of said first summing portion, first resistive means connecting said third electrode to said second input terminal of said first summing portion, current supply means, second resistive means connecting said first electrode of said first electron control means to said current supply means; and
second summing portion having first and second input terminals and an output terminal, said first input terminal of said second summing portion being connected to said second output terminal of said multiplier means, said second input terminal of said second summing means being adapted to receive the composite stereo signal, said second summing means providing the right channel stereo sig- 1 l nal at said output terminal thereof. 7. The demodulator circuit of claim 6 wherein said multiplier means further includes:
first electron control means having first, second and third electrodes, said first electrode being connected to said first input terminal of said first summing portion, said second electrode being adapted to receive the stereo decoding signal and said third electrode being adapted to receive a bias potential; and
second electron control means having first, second and third electrodes, said first electrode of said second electron control means being connected to said first input terminal of said second summing portion, said second electrode of said second electron control means being adapted to receive the stereo decoding signal, said third electrode of said second electron control means being connected to said third electrode of said first electron control means, said third electrode of said second electron control means also being adapted to receive said bias voltage. 8. The demodulating circuit of claim 7 wherein said multiplier means further includes:
said first electron control means includes a first bipolar transistor of a first conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said first electron control means; and said second electron control means includes a second bipolar transistor of said first conductivity type having emitter, base and collector electrodes respectively providing said first, second and third electrodes of said second electron control means. 9. The demodulating circuit of claim 7 wherein said multiplier means further includes:
said first electron control means includes a bipolar transistor of a first conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said first electron control means; said second electron control means includes a bipolar transistor of a second conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said second electron control means; first circuit means coupling said base electrode of said first transistor to said base electrode of said second transistor, said first circuit means being adapted to apply said stereo demodulating signal to said base electrodes of said transistors; and second and third circuit means being adapted to apply said composite stereo signal to said emitter electrodes of said first and second transistors respectively. 10. The demodulator circuit of claim 6 wherein said second summing portion further includes:
second electron control means having a first electrode, a second electrode, and a third electrode, said second electrode of said second electron control means being connected to said first input terminal of said second summing portion, and said third electrode of said second electron control means being connected to said output terminal of said second summing portion; third resistive means connecting said third electrode of said second electron control means to said secchannel and right channel stereo signals, including in combination:
first signal supply means adapted to provide monaural and composite stereo signals;
second signal supply means adapted to provide a stereo decoding signal;
multiplier means coupled to said first signal supply means and to said second signal supply means, said multiplier means being adapted to multiply said composite stereo signal and said stereo decoding signal together to provide a subchannel signal at first and second output terminals, said multiplier means including third supply means adapted to produce a bias supply at an output terminal thereof, first electron control means having first, second and third electrodes, said first electrode being coupled to said first output terminal of said multiplier means, said second electrode being connected to said second signal supply means, said third electrode being connected to said third supply means, first circuit means coupling said first signal supply means to said first electrode, second electron control means having first, second and third electrodes, said first electrode of said second electron control means being coupled to said second output terminal of said multiplier means, said second electrode of said second electron control means being connected to said second signal supply means, said third electrode of said second electron control means being connected to said third supply means, second circuit means coupling said first signal supply means to said first electrode of said second electron control means;
summing means being connected to said first and second output terminals of said multiplier means and receiving said subchannel signal and deriving an inverted subchannel signal;
third circuit means coupling said first signal supply means to said summing means; and
said summing means being responsive to the existence of said composite stereo signal and said subchannel signal and said inverted subchannel signal to provide left channel and right channel stereo signals at output terminals thereof, said summing means also being responsive to the existence of only said monaural signal to provide said monaural signal in a substantially undistorted form at said output terminals thereof, said summing means including third electron control means having first, second and third electrodes, said second electrode being connected to said first output terminal of said multiplier means, fourth circuit means connecting said third electrode to said third circuit means, current supply means coupled to said first electrode, fourth electron control means having first, second and third electrodes, said second electrode of said fourth electron control means being connected to said second output terminal of said multiplier means, said first electrode of said fourth electron control means being coupled to said current supply means, fifth circuit means connecting said third electrode of said second electron control means to circuit.

Claims (11)

1. A demodulator circuit suitable for providing left channel and right channel stereo signals at output terminals thereof, including in combination: first signal supply means having first and second output terminals for providing monaural and composite stereo signals; second signal supply means adapted to provide a stereo decoding signal; multiplier means for multiplying said composite stereo signal with said stereo decoding signal to derive a differential subchannel signal at first and second output terminals thereof, said multiplier means being operatively coupled to said first and second signal supply means; and summing means for deriving said left and right channel stereo signals at first and second output terminals respectively in response to said differential subchannel signal from said multiplier means and said composite signal from said first signal supply means, said summing means having first, second and third input terminals, said first and second input terminals being respectively coupled to said output terminals of said multiplier means and said third input terminal being coupled to said first output terminal of said first signal supply means, said summing means also being responsive to the existence of only said monaural signal to provide said monaural signal in a substantially undistorted form at said output terminals thereof.
2. The stereo demodulator circuit of claim 1 wherein said multiplier means includes in combination: third supply means adapted to produce a bias supply at an output terminal thereof, said output terminal being coupled to said second output terminal of said first signal supply means; first electron control means having first, second and third electrodes, said first electrode being coupled to said first input terminal of said summing means, said second electrode being connected to said second signal supply means, said third electrode being connected to said third supply means; first circuit means coupling said first output terminal of said first signal supply means to said first electrode of said first electron control means; second electron control means having first, second and third electrodes, said first electrode of said second electron control means being coupled to said second input terminal of said summing means, said second electrode of said second electron control means being connected to said second signal supply means and said third electrode of said second electron control means being connected to said third supply means; and second circuit means coupling said first output terminal of said first signal supply means to said first electrode of said second electron control means.
3. The stereo demodulator circuit of claim 2 wherein: said first electron control means includes a first bipolar transistor of a first polarity type; and said second electron control means includes a second bipolar transistor also of said first polarity type.
4. The demodulator circuit of claim 2 wherein: said first electron control means includes a bipolar transistor of a first polarity type; and said second electron control means includes a bipolar transistor of a second polarity type.
5. The stereo demodulator circuit of claim 2 wherein said summing means further includes in combination: first electron control means having first, second and third electrodes, said second electrode being connected to said first input terminal of said summing means; third circuit means connecting said third electrode to said third input terminal of said summing means; current supply means coupled to said first electrode; second electron control means having first, second and third electrodes, said second electrode of said second electron control means being connected to said second input terminal of said summing means, said first electrode of said second electron control means being coupled to said current supply means; and fourth circuit means connecting said third electrode of said second electron control means to said third input terminal of said summing means, said third electrodes of said first and second electron control means providing said first and second output terminals for the stereo demodulating circuit.
6. A monolithic stereo demodulator circuit suitable for providing left channel and right channel stereo signals in response to a composite stereo signal and a stereo decoding signal, the demodulator circuit including in combination: multiplier means having first and second input terminals and first and second output terminals, said first input terminal being adapted to receive the stereo decoding signal, said second input terminal being adapted to receive the composite stereo signal, said multiplier means providing a subchannel stereo signal between said output terminals thereof; first summing portion having first and second input terminals and an output terminal, said first input terminal of said first summing portion being connected to said first output terminal of said multiplier means, said second input terminal of said first summing portion being adapted to receive said composite stereo signal; said first summing portion being responsive to said subchannel signal and the composite stereo signal to provide the left channel stereo signal at said output terminal thereof; said first summing means including first electron control means having a first electrode, a second electrode and a third electrode, said second electrode being connected to said first input terminal of said first summing portion, and said third electrode being coupled to said output terminal of said first summing portion, first resistive means connecting said third electrode to said second input terminal of said first summing portion, current supply means, second resistive means connecting said first electrode of said first electron control means to said current supply means; and second summing portion having first and second input terminals and an output terminal, said first input termInal of said second summing portion being connected to said second output terminal of said multiplier means, said second input terminal of said second summing means being adapted to receive the composite stereo signal, said second summing means providing the right channel stereo signal at said output terminal thereof.
7. The demodulator circuit of claim 6 wherein said multiplier means further includes: first electron control means having first, second and third electrodes, said first electrode being connected to said first input terminal of said first summing portion, said second electrode being adapted to receive the stereo decoding signal and said third electrode being adapted to receive a bias potential; and second electron control means having first, second and third electrodes, said first electrode of said second electron control means being connected to said first input terminal of said second summing portion, said second electrode of said second electron control means being adapted to receive the stereo decoding signal, said third electrode of said second electron control means being connected to said third electrode of said first electron control means, said third electrode of said second electron control means also being adapted to receive said bias voltage.
8. The demodulating circuit of claim 7 wherein said multiplier means further includes: said first electron control means includes a first bipolar transistor of a first conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said first electron control means; and said second electron control means includes a second bipolar transistor of said first conductivity type having emitter, base and collector electrodes respectively providing said first, second and third electrodes of said second electron control means.
9. The demodulating circuit of claim 7 wherein said multiplier means further includes: said first electron control means includes a bipolar transistor of a first conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said first electron control means; said second electron control means includes a bipolar transistor of a second conductivity type having emitter, base and collector electrodes which respectively provide said first, second and third electrodes of said second electron control means; first circuit means coupling said base electrode of said first transistor to said base electrode of said second transistor, said first circuit means being adapted to apply said stereo demodulating signal to said base electrodes of said transistors; and second and third circuit means being adapted to apply said composite stereo signal to said emitter electrodes of said first and second transistors respectively.
10. The demodulator circuit of claim 6 wherein said second summing portion further includes: second electron control means having a first electrode, a second electrode, and a third electrode, said second electrode of said second electron control means being connected to said first input terminal of said second summing portion, and said third electrode of said second electron control means being connected to said output terminal of said second summing portion; third resistive means connecting said third electrode of said second electron control means to said second input terminal of said second summing portion; and fourth resistive means connecting said first electrode of said second electron control means to said current supply means.
11. A demodulator circuit suitable for providing left channel and right channel stereo signals, including in combination: first signal supply means adapted to provide monaural and composite stereo signals; second signal supply means adapted to provide a stereo decoding signal; multiplier means coupled to said first signal supply means anD to said second signal supply means, said multiplier means being adapted to multiply said composite stereo signal and said stereo decoding signal together to provide a subchannel signal at first and second output terminals, said multiplier means including third supply means adapted to produce a bias supply at an output terminal thereof, first electron control means having first, second and third electrodes, said first electrode being coupled to said first output terminal of said multiplier means, said second electrode being connected to said second signal supply means, said third electrode being connected to said third supply means, first circuit means coupling said first signal supply means to said first electrode, second electron control means having first, second and third electrodes, said first electrode of said second electron control means being coupled to said second output terminal of said multiplier means, said second electrode of said second electron control means being connected to said second signal supply means, said third electrode of said second electron control means being connected to said third supply means, second circuit means coupling said first signal supply means to said first electrode of said second electron control means; summing means being connected to said first and second output terminals of said multiplier means and receiving said subchannel signal and deriving an inverted subchannel signal; third circuit means coupling said first signal supply means to said summing means; and said summing means being responsive to the existence of said composite stereo signal and said subchannel signal and said inverted subchannel signal to provide left channel and right channel stereo signals at output terminals thereof, said summing means also being responsive to the existence of only said monaural signal to provide said monaural signal in a substantially undistorted form at said output terminals thereof, said summing means including third electron control means having first, second and third electrodes, said second electrode being connected to said first output terminal of said multiplier means, fourth circuit means connecting said third electrode to said third circuit means, current supply means coupled to said first electrode, fourth electron control means having first, second and third electrodes, said second electrode of said fourth electron control means being connected to said second output terminal of said multiplier means, said first electrode of said fourth electron control means being coupled to said current supply means, fifth circuit means connecting said third electrode of said second electron control means to said third circuit means, said third electrode of said third and fourth electron control means providing said output terminals for the stereo demodulating circuit.
US455841A 1974-03-28 1974-03-28 Stereo demodulating circuits and method of demodulation Expired - Lifetime US3916109A (en)

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US455841A US3916109A (en) 1974-03-28 1974-03-28 Stereo demodulating circuits and method of demodulation
GB11218/75A GB1505358A (en) 1974-03-28 1975-03-18 Stereo demodulator circuit
DE2513790A DE2513790C2 (en) 1974-03-28 1975-03-27 Stereo demodulator in push-pull circuit
JP3706275A JPS5513658B2 (en) 1974-03-28 1975-03-28
FR7510021A FR2266372B1 (en) 1974-03-28 1975-03-28
HK7/81A HK781A (en) 1974-03-28 1981-01-15 Stereo demodulator circuit

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JP (1) JPS5513658B2 (en)
DE (1) DE2513790C2 (en)
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HK (1) HK781A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4280101A (en) * 1978-06-30 1981-07-21 Pioneer Electronic Corporation Stereophonic signal demodulation circuit
US4288752A (en) * 1978-09-18 1981-09-08 Trio Kabushiki Kaisha Stereo demodulator with high frequency de-emphasis compensation

Citations (1)

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Publication number Priority date Publication date Assignee Title
US3798376A (en) * 1969-12-29 1974-03-19 Rca Corp Multiplex decoding system

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Publication number Priority date Publication date Assignee Title
USRE25699E (en) * 1954-04-26 1964-12-15 Simplified two-channel multiplex system
DE2004572A1 (en) * 1969-02-07 1971-03-04 Motorola Inc Multiplex demodulator circuit for a stereo receiver
DE2127545C3 (en) * 1970-06-09 1979-05-23 Sony Corp., Tokio Transistor gate circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798376A (en) * 1969-12-29 1974-03-19 Rca Corp Multiplex decoding system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4280101A (en) * 1978-06-30 1981-07-21 Pioneer Electronic Corporation Stereophonic signal demodulation circuit
US4288752A (en) * 1978-09-18 1981-09-08 Trio Kabushiki Kaisha Stereo demodulator with high frequency de-emphasis compensation

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JPS50131702A (en) 1975-10-18
FR2266372A1 (en) 1975-10-24
DE2513790C2 (en) 1983-01-20
DE2513790A1 (en) 1975-10-09
JPS5513658B2 (en) 1980-04-10
FR2266372B1 (en) 1980-08-01
GB1505358A (en) 1978-03-30
HK781A (en) 1981-01-23

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