US3909822A

US3909822A - Arrangement for controlling a plurality of lamps

Info

Publication number: US3909822A
Application number: US438154*A
Authority: US
Inventors: David Q Lee; Dinesh K Srivastava
Original assignee: GTE Automatic Electric Laboratories Inc
Current assignee: AG Communication Systems Corp
Priority date: 1974-01-28
Filing date: 1974-01-28
Publication date: 1975-09-30
Anticipated expiration: 1992-09-30
Also published as: CA1031881A

Abstract

An arrangement for controlling a plurality of lamps on a time shared basis, to light individual ones of them to indicate various distinct modes of operation. The lamps are driven by lamp drivers which are individually controlled by an associated latch. The status of the lamps is stored in a memory, with the memory and the latch being simultaneously addressed and selected to control a control signal to the latch to light the lamps. A digitally generated matrix is used, and the control signals are digitally derived from a single input source. All of the control signals therefore are synchronized and the need for multiple sources is eliminated.

Description

Lee et al.

[ 1 Sept. 30, 1975 ARRANGEMENT FOR CONTROLLING A PLURALITY OF LAMPS [75] Inventors: David Q. Lee, Chicago; Dinesh K. Srivastava, Westmont. both of I11.

[73] Assignee: GTE Automatic Electric Laboratories Incorporated, Northlake. Ill.

[22] Filed: Jan. 28, 1974 121] App]. No.: 438,154

[52] U.S. Cl 340/324 R; 340/331; 340/413 [51] Int. Cl. G08B 5/36 [58 Field of Search 340/413, 331, 334. 324 R [56] References Cited UNITED STATES PATENTS 3.550.112 12/1970 Schulenbcrg et a1. 340/334 3.810.150 5/1974 Jacobs t 340/331 60 fbcx PUL 8E8 (32m) SMTUS TRUNK LAMP STA TU 8 MEMO]? Y SYSTEM CON TROL Primary Exmniner-David L. Trafton Attorney, Agent. or FirmRobcrt J. Black [57 1 ABSTRACT An arrangement for controlling a plurality of lamps on a time shared basis, to light individual ones of them to indicate various distinct modes of operation. The lamps are driven by lamp drivers which are individually controlled by an associated latch. The status of the lamps is stored in a memory, with the memory and the latch being simultaneously addressed and selected to control a control signal to the latch to light the lamps. A digitally generated matrix is used, and the control signals are digitally derived from a single input source. All of the control signals therefore are synchronized and the need for multiple sources is eliminated.

6 Claims, 7 Drawing Figures lowzw SELECT" I RESET STATUS HOLD (/mJ 7 ENCODER US. Patfint Sept. 30,1975 Sheet 1 of5 3,909,822

FIG.

60 5/6. CLOCK PUL s s m) /7 I srATus 2 ADDRESS TRUNK ,T 13 LAMP TRK c .3 sTArus V LAMP g MEMORY SE1 8 20 32) DATA SYSTEM ADDRESS T "A" CONTROL f sum; 30

smRE CONTROLLER sELEcr ENCODER SUPPLY 50 RESET srArus HOLD (/ms) 7 LAMP 'i DRIVERS g g LATCHES) [:1 D: q a z r 5 o. E a 3 Q g n I E G (7) s S a i i J J J I I l l I y I "I I nor l I +5v $L' I SELECTOR F"F &

1 LAMP ENABLE J US. Patent Sept. 30,1975 Sheet 2 of5 3,909,822

Emmi

IIIIL m u w 5 38m mEEm n33 N GHQ U.S. Patent STEADY OFF STEADY 0N IZOIPM WINK Sept. 30,1975 Sheet4 of5 3,909,822

FIG. 5

I 5/2 ms L- 256ms +32lns 32ms 64 ms I TIME 4 PERIOD US. Patent Sept. 30,1975 Sheet 5 of 5 3,909,822

ENABLE DECODER F LIP-FLOPS DECODER DE CODE 1-? COUN TE R VOICE 0/? DA TA CHA NNE L S P C M CA RR/ER CENTRAL OFF/CE FIG. 7

DISPLA DISPLAY This invention relates -to a method and apparatus for.

generating a plurality of distinct signals, arid to a Similar reference characters refer to similar parts method and-apparatus for-connecting said plurality of PABX'com'munication' system, for lighting thetrunk lamps at an attendant console' to' display various-distinct modes independently ofother lamps. Conventionally,y"in 'most"systerris, this requires aone-to-one connection -betwe'en'the lamps and theficon-trohsig'nalsf lhein te'i'conne'cti'on b'e'tween'the la'mps and the contro'l-signals"- can be made via' a rc lay matrix or a solid state d'riv'er matrix using trarisistors,SQRs and the like. The; rela'y'rnatrix,however, 'im'poses*strict; power requirement's'i'on the signalsources; and" is itself very expensiveand' bulky. Trar'isistor-drivers-and the like require large numbers-of discrete components; Use of RC networks or'monostable multivibrators are means for' solving the problem, but they, also re quire large numbers of parts and do not lend themselves to accurate cbntr'oloftiming. iln 'the hereinafter'de'scr'ibed embodiment of the invention, the interconnections between-the lamps and the control signals areestablished"using a time-shared technique and-a digitallyj 'generat'e'd'rnatrix. Furthermore, the control signals for generating the various distinct m ode's for the lighting all of the lamps are digitally derived from a single input source, hence all of 'the'control'signa ls are synchronized and the ne'edformultiple soiirces is 'elimiriate'dfwith this arrangement; loading is no problem andan attendant can more easily visually interpret the status of th'lamps'. i

Accordingly, it isan object ofthe present invention to provide an imp'rovedrneth'odand apparatus for generating a plurality of distinct signals." 3

A related object is to provide an improved method and arrangement'ifor connecting aplurality of distinct signals toiindividual onesof'a plurality of lamps for the purposeof lighting'thetn.'

Oth er obje c ts'fof the invention will in part be obvious and williin part"appeanhereinafter. I

For" a fuller u'nder'stariding'of thenature and objects of the" invention, referen'ce 'should be had to the following detailed description taken in connection with the accompanying drawings, in which: 1

FIG. 1 is a block diagram schematic of the arrangemnt of the invent ion;

FilGS 2 "3 are block diagram schematics illustrat- ;the arrangement 5f Fil Gr. 1 in greater detail;

F IG'. 4 is ascheriiatic type diagrarnillustrating the mannerin which the Various control signals for producirigthe various distinct li'ghtin g 'r'riodesare' generated;

FIGQ S 'iIIustrates the varioiis pulse trains used in 'generating' the different distinct lighting modes;

FIG. is a block diagram'schematic illustrating an alternative embodiment of the invention using two'de- AH H ,FlC'. 7 is a block :(iiagra'm schematic generally'illustra ting another embodiment for controlling the display of a variety of lamps in a variety of modes at several locations, sending time multiplexed control signals in one or more channels of 'a'PCM carrier."

throughout the several views of the drawings. e

Referring now to the drawings, in FIGS. 1-3, the invention is disclosed as embodied within a PABX communication system, for indicating to an attendant the status of the system s trunks, by the'attendant visually observing thedist in'ct mode of operation' of each-of a plurality of lamps L1-L32' at an attendantconsole (not shown). The number of lamps can be increased, or decreased, as more fully. explained below. T he lamps-Ll- LBZ' are drivenby lamp drivers D1-D32 which are, in turn, controlled by 'latches- S1"-.S32."Each lamp L1-L32 therefore has only one associated latch and lamp driver, and the-mode of operation of the lamps is controlled by applying proper logic signals to the latches. The-means for applying these logic signals include? a trunk larnp status memory 10,? a lamp status: decoder 20,-'a trunk lamp status store controller.30, a trunk lamp selector-40, a trunk

lamp select encoder

50,1 and alamp status generator 60, each of which is more fully described below. Generally, the arrangement is such that a time sharingtechnique is employed to control the flashing rates and intensity of'the lamps Ll-L32, with the end result being that each lamp acquires a distinct state of display, indicative of the current status of its associated trunk: All of the lamps are scanned sequentially at a rapid rate relative to the flashing rates, with the lamps being turned ON in fixed time slots if so dictated by the control signals simulating the display modes, and after a pause, all of the lamps are turned OFF simultaneously. This cycle is repeated several times during the smallest period'of the fastest control signal. Also, the arrangement includes means for digitally synthesizing a variety of signals to provide the control signals simulating the display modes, with a single input signal being used to derive all of the control signals. v

The description and operation of each of the various different components comprising the arrangement are set forth in the title paragraphs below, followed by a description of the operation of the arrangement with a PABX communication system. I

. TRUNK LAMPS Isl-L32 AND LAMP DRIVERS 7 131-1132 I As indicated above, in' the illustrated embodiment, 32 lamps L1-L32 are illustrated, however, this number can be increased, or modified, as described more fully below. One terminal of each of the lamps L1-L32uis coupled to a +5 volt supply, and the other terminal thereof is coupled to an associate one of the lamp drive ers D1-D32; These lamps drivers Dl-D32 may be of the type well-known in the" art; and are operated by an associated one of the latches-SL832 to couple a ground to'the lamps to light them. I

t y I y LATCHES 31-532 Theslatches Ll-L32 maybe bistable flip-flops of the well-knowntype, such as, for-example, TypiSN74279 sold byTexaslnstruments, Inc.-, and having S andR inpiits-and-a Q output. ln operation,-when flip-flops S inp'ut 'goe's' low, its Q outputgoes high and stayshigh until its input goes low. The Q output controlsthe lamp driver associated with it, so that a lamp once turned ON stays ON until the flip-flop is reset.

' The latches S1-S32,-or flip-flops, are digitally controlled and therefore thereis no ;need for interface circuits that normally are required for analog drivers. Also, since each lamp is individually controlled by a lamp driver and latch, there is no need for a driver matrix.

TRUNK LAMP STATUS MEMORY The trunk lamp status memory 10 is a scratch pad memory with nondestructive readout, and may be a Type SN7489 read/write memory sold by Texas Instruments, Inc. or its equivalent. The latter is a 64-bit memory organized in a matrix to provide l6 words of four bits each, with each word being addressed in straight binary. Since 32 lamps Ll-L32 are used, two of these memories are coupled to provide the 32 words which are necessary to store the status of the lamps.

In theillustrated embodiment, each of the two memories, designated STORE l and STORE 2, respectively, has four address lines A, B, C and D, three data inputs l1, I2 and 13, a write enable R/W and a memory enable ENl or BN2 for controlling the entry and access of data. During the write operation, information present at the data inputs Il-I3 is written into the memory by addressing the desired word and holding both the memory enable ENl, or EN2, and write enable R/W low. The complement of the information which has been written into the memory is nondestructively read out at the three outputs D1, D2 and D3. This is accomplished by holding the memory enable ENl, or EN2, low, the write enable R/W high, and selecting the desired address.

In the illustrated embodiment, the addresses and the status of the trunks are supplied by the systems call processor unit or system control (not shown) to the trunk lamp status memory 10, via the status leads 11 which are directly coupled to the data inputs 11-13 and via the address leads 12 which are coupled to the trunk lamp status store controller 30, in the manner described more fully below.

LAMP STATUS DECODER The lamp status decoder 20 is a data selector or multiplexer which selects one-of-eight data sources, in accordance with the signals coupled to its enable leads. The lamp status decoder 20 may be a type SN7415 1A data selector/multiplexer sold by Texas Instruments, Inc. or its equivalent. The data sources, in the illustrated embodiment, are the various distinct modes or control signals used to light the lamps Ll-L32 and which are generated by the lamp status generator 60, together with two test functions or control signals used to force each of the lamps ON, or OFF. The other distinct modes or control signals include steady bright, dark, steady dim, wink, 120 IPM and 60 IPM. The enable leads are coupled to the output leads D1, D2 and D3 of the trunk lamps status memory 10, and the selected data source is coupled to the decoders output lead OL, to the OR gate 14. All of the lamps L1-L32 are forced ON via the ground coupled through the manually operated switch 15 and the OR gate 14.

In operation, the output of the trunk lamp status memory 10 is coupled to the lamp status decoder 20, to select the one data source or control signal corresponding to the stored status of the associated trunk. The selected data source or control signal is coupled via the output lead 0L and the OR gate 14 to the trunk lamp selector 40 which couples it to the proper one of the latches Ll-L32, as more fully described below.

TRUNK LAMP STATUS STORE CONTROLLER 30 The trunk lamp status store controller 30 is a quadruple 2-line-to-1-line data selector/multiplexer which selects a 4-bit word from one of two sources and routes it to four outputs. A select input lead SL selects the one of two sources, depending upon whether it is at a high or a low logic level. This status store controller 30 may be a Type SN74157 sold by Texas Instruments, Inc. or its equivalent.

In the illustrated embodiment, one of the two sources comprises 4-bit addresses of the trunks from the system control and the other source comprises 4-bit addresses generated by the trunk lamp select encoder 50. Normally, the select input lead is such that the addresses from the encoder 50are selected and coupled to the output leads 17 which form the address lines A, B, C and D to the status memory 10. When the status of a trunk changes, or status data is to be written into the status memory 10, the logic level on the select lead is changed by the system control, to select the address data from the system control, in the manner described more fully below.

TRUNK LAMP SELECTOR 40 The trunk lamp selector 40 decodes 4 binary-coded inputs into one of thirty-two mutually exclusive outputs. The trunk lamp selector 40 is formed of two 4- line-to-l6-line decoders which may be Type SN74154 decoder demultiplexers sold by Texas Instruments, Inc., or the equivalent thereof. Each of these decoder demultiplexers decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs when both of its strobe inputs are low. The demultiplexing function is performed by using the four input lines to address the output line, passing data from one of the strobe inputs with the other strobe input low.

In the illustrated embodiment, the trunk lamp select encoder 50 outputs binary addresses to each of the decoder/demultiplexers four input lines A, B, C and D to address the outputline. The selected source from the lamp status decoder 20, from the OR gate 14, is coupled to the one strobe input 811, and the other strobe inputs 812 are coupled with the respective outputs of a flip-flop F/Fl which functions to enable either the decoder 1 or the decoder 2, as more fully described below. The 16 outputs of each of the two decoders are coupled to respective ones of the latches 81-832, to operate these latches.

TRUNK LAMP SELECT ENCODER 50 The trunk lamp select encoder 50 includes a scanner 51 and the flip-flop F/Fl. The scanner 51 may be a divide-by-sixteen counter such as the Type SN7493 sold by Texas Insruments, Inc. or its equivalent, and the flipflop F/Fl may be of the type well-known in the art.

The scanner 51 is driven by one microsecond clock pulses from the systemss master clock at a 1 MH rate, and provides 4-bit count outputs ,on the leads A, B, C and D coupled to the

decoders

1 and 2 of the trunk lamp selector 40. These 4-bit counts form the binary addresses which are used to address the respective output lines of these decoders. When the count reaches 16, the flip-flop F/Fl is triggered to provide a low logic level signal on the strobe input 512 to the decoder 2, to enable it so that the selected source is coupled to the respective ones of the latches Sl7-S32, as the count of LAMP STATUS GENERATOR 60 As indicated above, the lamp status generator 60 provides the various control signals to generate the distinct modes which, in the illustrated embodiment, include a steady bright, dark, steady dim, wink, 60 IPM and 120 IPM. The arrangement is such that a steady bright is a permanent ON condition, and requires a permanent logic or ground for the control signalpsimilarly, dark is a permanent OFF condition, and hence requires a permanent logic 1 or +5 volts for the control signal. These ground and +5 volt control signals are coupled as two of the sources to the lamp status decoder 20.

All of the other control signals are generated from a single input source which, in the illustrated embodiment, is the systems master clock. The latter provides a 32H, 50 percent duty cycle'puls'e train to a 4-bit or divide-by-sixteen binary counter 61 which may be a Type SN7493 sold by Texas Instruments, Inc. or its equivalent.

As can be seen in FIGS. 4 and 5, this 32I-I 50 percent duty cycle pulse train is used directlyas the steady dim control signal and is coupled to and is one of the sources selected by the lamp status decoder 20. This pulse train will cause the lamps to turn ON and OFF at the 1321-1 rate, giving constant illumination, but with the intensity being reduced proportional to the square of the duty cycle, that is, 1/4 of steady bright.

This 32H, pulse train also is coupled to the counter 61, and the latter provides a pulse train output 62 of 2H, (32 16) or 120 IPM and 50 percent duty cycle. With this pulse train, the lamps are ON for 0.25 seconds and OFF for 0.25 seconds.

The counter 61, at its output 63, provides a 4H pulse train which is coupled to a J-k flip-flop 64. The output of this flip-flop 64 (divide by 2) is a pulse train of [H or 60 IPM and 50 percent duty cycle. The control signal therefore lights the lamps for 0.5 seconds, and then they are OFF for 0.5 seconds.

The wink signal is a brief turn OFF of the lamps every second, and is provided by combining the 4H,, (output 63) and the 2H,, (output 62) at the OR gate 65, with the 1H, output of the flip-flop 64 at the OR gate 66. These signals produce a control signal corresponding to a logic level 1 for /ssecond or 125 milliseconds every second. The lamps therefore are ON for 875 milliseconds and OFF for 125 milliseconds.

Accordingly, with this arrangement, it can be seen that all of these control signals are digitally derived from a single input source and, therefore, they have a common periodicity and are synchronized. This allows an easier visual interpretation of the status of the trunks, by an attendant. Also, the variety of display modes can be increased, or modified, as required. Furthermore, loading is not a problem because the synthesized sources provide control signals to the lamp drivers, and do not drive the lamps themselves. As the number of lamps and/or display modes increase, the digital synthesizer is not affected as in the case of the conventional method where increased power handling capability on a per source basis is required.

OPERATION Now that the various individual components of the arrangement have been described, the operation thereof may be described as follows. As can be seen in FIG. 3, the 32H, 50 percent duty cycle pulse train is coupled to the counter 61 in the lamp status generator 60, to operate the latter to provide the IPM, IPM and the wink control signals, in the manner described above. These control signals, together with the steady bright (ground), the dark (+5 volts) and the steady dim (the 32H, pulse train) control signals all are coupled to the lamp status decoder 20, as sources selectable by the lamp status decoder.

The lMH one microsecond clock pulses from the systems master clock are coupled to the scanner 51 of the trunk lamp select encoder 50, to cause the scanner 51 to count from 1 to 16. The scanner 51 provides these counts, in a 4-bit binary output to the decoders l and 2 in the trunk lamp selector 40, and to the multiplexer of the trunk lamp status store controller 30. These 4-bit binary outputs represent addresses of the various lamps Isl-L32, particularly as they pertain to the status of these lamps stored in the trunk lamp status memory 10.

When an address is coupled to the multiplexer of the trunk lamp status store controller 30, via the address lines A, B, C and D, the status of the trunk associated with that address is nondestructively read out at the three outputs D1, D2 and D3, and coupled to the lamp status decoder 20. As indicated above, this address may be associated with either of the two memories STORE l or STORE 2, and these memories are enabled by holding the memory enable ENl or EN2 low and the write enable R/W high. In this arrangement, the write enable R/W normally is held high by the system control, and the memory enable ENl or EN2 is made low by the state of the output of the flip-flop F/Fl of the trunk lamp select encoder 50 which is coupled to and enables the

gates

72 and 73, in a fashion such that the appropriate enable ENl or EN2 is enabled. Also, the appropriate onev of the

decoders

1 and 2 of the trunk lamp selector 40 is enabled by the flip-flop F/Fl, so that the addresses outputted by both the status store controller 30 and by the trunk lamp selector 40 are the same.

The lamp status decoder 20 decodes the input logic signals on the leads D1, D2 and D3 corresponding to the status of the addressed trunk, and selects the corresponding dataso'urce, that is, the distinct mode generated by the trunk status generator 60, and couples it to the output lead OL. Assuming, for example, that the steady bright control signal is selected as corresponding to the status of the addressed trunk, this steady bright control signal is coupled through the OR gate 14 and the trunk lamp selector 40, via either the decoder 1 or decoder 2, in the manner described above, to the correspondingly addressed one of the latches 81-832. This control signal is coupled to the inputSof the latch and sets it to provide an output to the associated one of the lamp drivers Dl-D32 to operate it to light the lamp.

As the scanner 51 is continuously advanced, each of the lamps Ll-L32 is addressed, and the status of its associated trunk, as stored in the trunk lamp status memory 10, is read out and used to couple the appropriate control signal to it, to light the lamp to visually indicate the status of the associated trunk. After all of the lamps have been sequentially addressed, all of the latches Sl- S32 are simultaneously reset, by means of a 1;; sec reset pulse from the system control, on the reset lead RL. In the illustrated embodiment, this reset pulse occurs every millisecond, hence each of the lampsare sequentially scanned approximately 33 times between the occurrence of each reset pulse. In operation, the maximum scan cycle must be less than the maximum ON or OFF of a lamp, which is from 100 milliseconds to 25 milliseconds, that is, 10-40 flickers per second. Thus, the scan cycle (interval between reset pulses) should be less than l0 milliseconds.

This sequential scanning scheme allows no two lamps to initiate turn ON simultaneously, somewhat distorting the characteristics of the control signals. The maximum delay to set or turn ON a lamp, between the first and last latch, 'is the clock interval times the number of lamps. 'This delay is made a small percentage of the scan cycle, to give almost identical intensity to all lamps in the same mode.

If the status of any trunk changes during the course of operation, the system control provides the data bits indicating the new status on the status lead 11 and the address bits representing the particular trunk on the address leads 12. In addition, when the system control has all of the information available, it outputs a R/W pulse on the strobe lead & to the status store controller 30 and on the ENl/EN2 lead to the gate 71. This R/W pulse operates the multiplexer in the status store controller 30, in the manner described above, to couple the address bits on the address leads 12 to the lamp status memory 10, rather than the address bits from the lamp selector encoder 50, as during normal operation. The R/W pulse also is coupled to the write enable R/W leads on the STORE l and STORE 2 memories. The pulse on the EN1/E N2 lead enables the

gates

71 and 73, to enable the proper one of the STORE 1 and STORE 2, to permit the status bits to be written into the memory, in the addressed location, in the manner described above. When the R/W pulse and the pulse on the EN vii r72 lead are removoed, the operation reverts back to its normal mode of operation, where the addresses are generated by the select encoder 50, to read out the lamp status memory 10.

ALTERNATE OPERATION In FIG. 6, there is illustrated an arrangment having a different reset scheme, using two decoders A and B, each of which may be like the lamp status decoder 20. With this arrangement, a perfectly symmetrical cyclical sequence is obtained, eliminating the need for simultaneously resetting all of the latches 81-832.

In operation, the decoder A will always reset the latch one clock pulse before it can be set. The decoder B allows the latch to set if permitted by the read out of the lamp status memory 10. Thus, reset (mandatory) is followed by set- (optional) for each latch. This sequence is repeated from the first to the last latch, and then back to the first latch. There is no long pause for common reset, allowing the number of lamps to be increased several times over the first described arrangement.

ALTERNATE OPERATION In FIG. 7, there is illustrated an arrangement which lends itself to centralized computer control of remote displays, each location having one or more displays such as time, weather, news and the like. In this case, the sequential scan rate is adjusted to PCM bit stream rate (L544 Mb/s), and the control signals are then allotted one or more channel slots on a standard PCM carrier, with other channels being used for voice or data tranmission by PCM.

Time multiplexed control signals are sent in one or more channels of a PCM carrier, with these signals being generated by a computer and multiplexed into the carrier channel slots. At remote locations (displays 1 and 2), these channels are decoded, and with the sync information available in any PCM carrier, their relative time slots for individual lamps are derived. The associated PCM bits are then used to control latches, lamp drivers and lamps in a predetermined sequence.

It will thus be seen that the objects set forth above among those made apparent from the preceding description, are efficiently attained and certain changes may be made in carrying out the above method and in the construction set forth. Accordingly, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

Now that the invention has been described, what is claimed as new and desired to be secured by letters Patent is:

1. An arrangement for individually controlling each of a plurality of lamps using a time sharing technique comprising, in combination:

a. a plurality of lamps, each having a lamp driver associated with it for lighting it;

b. memory means for storing the status of each of said plurality of lamps;

c. status generating means for providing a plurality of control signals, each corresponding to a different mode of operation of said lamps, said status generating means driven by clock pulses from a single source and deriving a plurality of different ones of said control signals from said clock pulses, said status genreating means comprising a ground potential source for providing a steady bright control signal, a positive potential source for providing a steady dark control signal, said clock pulses being used to provide a steady dim control signal and being coupled to counter means operable to provide on one output thereof a first control signal and on another output thereof a second control signal, and gating means having said first and second control signals coupled to it for providing a wink control signal to turn on said lamps for a said period of time and to turn them off for a shorter set period of time;

. latch means coupled to each of said control drivers and operated by said contro signals to control the operation of said lamp drivers in lighting their associated lamps;

e. addressing means for cyclically and sequentially addressing said memory to read out the status of each of said plurality of lamps and for selecting the latch means associated with the addressed one of said plurality of lamps; and

' f. decoder means coupled to said memory means,

said decoder means decoding the status of each of said addressed lamps from said memory means and selecting and coupling the signified one of said control signals to its latch means to operate said latch means.

2. The arrangement of claim 1, wherein said plurality of latch means are simultaneously reset at predetermined time intervals be means of a reset pulse, the time between each of said reset pulses being greater than the cycle time such that each of said latches is addressed and selected a plurality of times between each of said reset pulses.

3. The arrangement of claim 1, including two decoder means, one of said decoder means resetting each of said plurality of latch means one clock pulse before it can be set, and the other one of said decoder means decoding the status of each of said addressed lamps from said memory means and selecting and coupling the signified one of said control signals to its latch means to operate said latch means, whereby a symmetrical cyclical sequence is provided.

4. The arrangement of claim 1, wherein said addressing means comprises counter means, controller means operable to address said memory means under the control of said counter means, and a latch selector means operable to select individual ones of said latch means under the control of said counter means, said counter means being driven by clock pulses to operate said controller means to address said memory means and said latch selector means to select the corresponding one of said latch means, whereby the decoder means decodes the status of the addressed lamp from the memory means and selects and couples the signified one of the control signals to the selected latch means.

5.'The arrangement of claim 4, wherein said controller means is selectively operable to address said memory means under the control of said counter means and by means of addresses supplied from a system processor,whereby said memory means can be addressed by a system processor to change the stored status of a lamp as the status of said plurality of lamp change, the status of the addressed ones of said lamps being coupled to said memory means from said system processor.

6. The arrangement of claim 1, wherein said clock pulses are 32H, clock pulses with a 50 percent duty cycle and wherein said counter means is a divide by 16 binary counter providing IPM control signals on one output thereof and 60 IPM control signals one another output thereof, said 120 IPM and said 60 IPM control signals being coupled to said gating means so as to provide a wink control signal to turn ON said lamps for 875 milliseconds and to turn them OFF for milliseconds.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION PATENT NO. 3,909,822

DATED SEPTEMBER 30, 1975 lNVENTOMS) DAVID Q. LEE/ DINESH K. SRIVASTAVA it is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 8, line 40, 'genreacing" should be genefating line 53, "control" should be lamp line 54, "contro" should be control Column 9, line 3, "be" should be by Signed and Sealed this sixth D y f January 1976 [SEAL] A ttes t:

RUTH C. MASON C. MARSHALL DANN Arresting Officer Commissioner uj'Parents and Tmdemarks

Claims

1. An arrangement for individually controlling each of a plurality of lamps using a time sharing technique comprising, in combination: a. a plurality of lamps, each having a lamp driver associated with it for lighting it; b. memory means for storing the status of each of said plurality of lamps; c. status generating means for providing a plurality of control signals, each corresponding to a different mode of operation of said lamps, said status generating means driven by clock pulses from a single source and deriving a plurality of different ones of said control signals from said clock pulses, said status genreating means comprising a ground potential source for providing a steady bright control signal, a positive potential source for providing a steady dark control signal, said clock pulses being used to provide a steady dim control signal and being coupled to counter means operable to provide on one output thereof a first control signal and on another output thereof a second control signal, and gating means having said first and second control signals coupled to it for providing a wink control signal to turn on said lamps for a said period of time and to turn them off for a shorter set period of time; d. latch means coupled to each of said control drivers and operated by said contro signals to control the operation of said lamp drivers in lighting their associated lamps; e. addressing means for cyclically and sequentially addressIng said memory to read out the status of each of said plurality of lamps and for selecting the latch means associated with the addressed one of said plurality of lamps; and f. decoder means coupled to said memory means, said decoder means decoding the status of each of said addressed lamps from said memory means and selecting and coupling the signified one of said control signals to its latch means to operate said latch means.

3. The arrangement of claim 1, including two decoder means, one of said decoder means resetting each of said plurality of latch means one clock pulse before it can be set, and the other one of said decoder means decoding the status of each of said addressed lamps from said memory means and selecting and coupling the signified one of said control signals to its latch means to operate said latch means, whereby a symmetrical cyclical sequence is provided. 4. The arrangement of claim 1, wherein said addressing means comprises counter means, controller means operable to address said memory means under the control of said counter means, and a latch selector means operable to select individual ones of said latch means under the control of said counter means, said counter means being driven by clock pulses to operate said controller means to address said memory means and said latch selector means to select the corresponding one of said latch means, whereby the decoder means decodes the status of the addressed lamp from the memory means and selects and couples the signified one of the control signals to the selected latch means.

5. The arrangement of claim 4, wherein said controller means is selectively operable to address said memory means under the control of said counter means and by means of addresses supplied from a system processor,whereby said memory means can be addressed by a system processor to change the stored status of a lamp as the status of said plurality of lamp change, the status of the addressed ones of said lamps being coupled to said memory means from said system processor.

6. The arrangement of claim 1, wherein said clock pulses are 32Hz clock pulses with a 50 percent duty cycle and wherein said counter means is a divide by 16 binary counter providing 120 IPM control signals on one output thereof and 60 IPM control signals one another output thereof, said 120 IPM and said 60 IPM control signals being coupled to said gating means so as to provide a wink control signal to turn ON said lamps for 875 milliseconds and to turn them OFF for 125 milliseconds.