US3895222A - Digital computer to determine the ignition angle in a piston engine - Google Patents

Digital computer to determine the ignition angle in a piston engine Download PDF

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Publication number
US3895222A
US3895222A US468573A US46857374A US3895222A US 3895222 A US3895222 A US 3895222A US 468573 A US468573 A US 468573A US 46857374 A US46857374 A US 46857374A US 3895222 A US3895222 A US 3895222A
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Prior art keywords
counter
adder
divisor
step down
dividend
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US468573A
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English (en)
Inventor
Albert Maringer
Wolfgang Drotziger
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Siemens AG
Siemens Corp
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Siemens Corp
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Priority claimed from DE19732323661 external-priority patent/DE2323661C3/de
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    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
    • F02P5/00—Advancing or retarding ignition; Control therefor
    • F02P5/04—Advancing or retarding ignition; Control therefor automatically, as a function of the working conditions of the engine or vehicle or of the atmospheric conditions
    • F02P5/145—Advancing or retarding ignition; Control therefor automatically, as a function of the working conditions of the engine or vehicle or of the atmospheric conditions using electrical means
    • F02P5/15—Digital data processing
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
    • F02P17/00—Testing of ignition installations, e.g. in combination with adjusting; Testing of ignition timing in compression-ignition engines
    • F02P17/10—Measuring dwell or antidwell time
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/62—Performing operations exclusively by counting total number of pulses ; Multiplication, division or derived operations using combined denominational and incremental processing by counters, i.e. without column shift
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/10—Internal combustion engine [ICE] based vehicles
    • Y02T10/40—Engine management systems

Definitions

  • a counter 235/196. 6 2 is provided for the numerator of the ratio and a comparator used to compare the outputs of the memories [56] References Cited and the numerator counter with operation controlled by a control circuit and the result of the division UNITED STATES PATENTS stored in a result counter.
  • the ignition angle a in a piston engine can be determined by comparing the two time spans and I where the time span i is the time required for the crankshaft to rotate through an angle B as defined by two marks and the time t the time required to rotate through an angle a defined by one of the two marks and the moment of ignition.
  • the time 1 is the time to rotate through the angle B as defined by marks on the crank shaft at the edges of that angle.
  • the time t is the time to rotate through the angle a defined by one of the marks and the point of ignition.
  • an object of the present invention to pro vide a digital computing circuit for solving the above equation to thereby determine the ignition angle in a piston engine. Furthermore, it is the object to do this in such a way that the resolution error resulting from the multiplication by the constant factor is compensated for.
  • Such a device is provided according to the present invention.
  • Two pulse counts proportional to times t and are obtained and stored in digital counters, one being provided for the divisor and dividend.
  • an adder and sum memory Associated with the divisor counter is an adder and sum memory connected in parallel thereto.
  • a comparator is provided for comparing the output of the sum memory and the output of the dividend counter.
  • a control circuit is included along with a result counter for controlling and counting the multiple additions required in order to accomplish division. Multiplication by a constant factor is obtained through the use of a step down counter preceding the divisor counter, the step down counter dividing by the number which is the additional constant factor in the ratio, i.e., the quantity B in the above noted equation.
  • adders and sum memories are also provided in parallel with the step down counter with carry pulses from the additional adder provided to the least significant bit of the adder associated with the divisor counter.
  • the result counter is accordingly expanded by a number of least significant bits corresponding to the division in the step down counter.
  • optimization is achieved by shortening the divisor counter by as many bits as the number of bits contained in the step down counter and by replacing the adders and sum memories associated with the portion of the counter eliminated with simple binary counters.
  • the carry output of the adder associated with the remaining divisor counter bits is coupled to the second least significant bit of the counter replacing the eliminated adders and sum memories.
  • the least significant bits of the result counter is also omitted.
  • the most significant divisor counter bit and most significant dividend counter bit are connected as two inputs to a NOR gate whose outputs is coupled as disabling inputs to gate circuits at the input to the dividend and divisor counters to block count pulses.
  • the second least significant bit of the counter replacing the eliminated adders and sum memories is coupled through an NAND gate, one input of which is connected to the carry pulse output of the adder and the other to the adding pulse output of the control circuit.
  • result counter which is a presettable by-directional counter set to a 20 crank value prior to the start of computation.
  • FIG. 1 is a block-logic diagram of a division circuit of the type used in the present invention.
  • FIG. 2 is a block diagram of a first embodiment according to the present invention.
  • FIG. 3 is an expanded block diagram illustrating in more detail the block diagram of FIG. 2.
  • FIG. 4 is a similar block diagram illustrating a optimized version of the embodiment of FIG. 3.
  • FIG. 5 is a diagram illustrating the angles a and B and the measuring range of the apparatus of the present invention with respect to top dead center.
  • FIG. 6 is a logic-block diagram of a preferred type of result counter.
  • FIG. 1 is a block-logic diagram helpful in understanding the computing apparatus of the present invention. Shown is a first gate circuit 11 having as inputs the output of a clock designated f and a gating pulse 1;; representing the time required to rotate through the angle B shown on FIG. 5. For this period of time, the gate 11 will be enabled and provide clock pulses at its output. These clock pulses are counted and stored in a counter 13. In similar fashion, a gate 15 is enabled by a pulse t representing the time to rotate through the angle a of FIG. 5 permitting the clock pulses f to be gated into a counter 17.
  • the numbers associated with the flip-flops correspond to the value of their corresponding bit inputs.
  • the counter outputs are designated Al, A2, A4 and A8 and the second inputs to the adder B1, B2, B4 and B8.
  • the adder 19 will add the values present at its two inputs and provide their sum in binary form at its outputs designated S1, S2, S4 and S8.
  • the second inputs B1 through B8 of the adder are provided respectively, by the outputs of the flip-flops FFl through FF8.
  • These flip-flops are D type flip-flops with the input from the adders being the data input.
  • the clock input to these flip-flops is provided from a control circuit 21 having as inputs a start command and the clock output f
  • the flip-flop outputs are also coupled as inputs to a comparator 23.
  • Comparator 23 has as its second inputs the outputs of counter 17. Comparator 23 will pro ide an output when the value at its input from the flip-flops is equal to or greater than the count stored in counter 17.
  • a line from the control circuit 21 is also provided as an input to a counter 25 which is the result counter.
  • the adder will be providing a 0 output at the sum terminal 51, a 1 output at the sum terminal S2 and 0 outputs on the sum terminals S4 and S8.
  • the adder will now have an input at A2 and an input at B2. This addition will result in a O at S2 and a carry to S4.
  • 0 at the input to FF2 will cause it to be reset and the l at the output S4 will cause flip-flop FF4 to be set.
  • flip-flops FF2 and-F1 4 will be reset and flip-flop FF8 set, to have a 1 output which will be in agreement with the 1 input from counter 17 resulting in an output from comparator 23.
  • This output disables the control circuit 21 from outputting further pulses. If a flip-flop is used therein, this pulse may be used to reset that' flip-flop.
  • the clock pulses were also provided to the counter 25 which is the result counter. Four pulses occured and the count stored in this counter is now four, the correct answer for a division of eight by two.
  • multiplication by the constant reference B can be accomplished by dividing the divisor by rather than multiplying the quotient thereby. Since B is a constant number, this division can be carried out in a simple manner by a step down or dividing counter placed ahead of the divisor counter 13. However, simply providing a step down counter prior to the counter 13 will result in a loss of resolution with the resolution reduced to Z B A circuit which avoids this resolution error is shown in block diagram form on FIG. 2. As in the embodiment of FIG. 1, gates 11 and 15 are provided as are counters l3 and 17 along with the adder 19, an associated flipflop memory designated 27 and the comparator 23. However, there is provided in addition, a step down counter 29 to perform the multiplication by B by division of the divisor by B.
  • a further adder 31 and associated flip-flop memory 33 arranged in similar manner to the adder 19 and memory 27 shown on FIG. 1.
  • the carry output of the most significant bit of the adder 31 is coupled to the carry input of the least significant bit of the adder 19.
  • B should be selected to be a number which is of power of 2. In this way, the division within the binary counter can easily be accomplished. In other words, B should be selected to be a number such as 2, 4, 8,16, 32, 64, 128 etc. It is known from experience that the total ignition angle range in a motor vehicle does not exceed 60 of crank angle. Since it is known that the measuring process will yield the smallest error when a B, it makes sense to put the one mark for the reference angle B in the middle of the ignition angle range, assuming that the angle a will probably vary mainly about a mean angle. Based on this, an angle B 32 crank angle is chosen.
  • the resultant crank angle value When calculated by conventional methods, the resultant crank angle value would be a 32.l01653 crank angle.
  • the result counter of the dividing unit will show a crank angle value of a 33 crank anglev
  • the error present is approximately 1 crank angle.
  • the factor G is treated the same as the factor B. That is, instead of multiplying the quotient by the factor, the division of the divisor is accomplished by stepping it down. Since these two factors act the same, for the purpose of simplicity, the factor B X G will be referred to as B. Thus B 32 X 4 128. Therefore, the step down counter such as step down counter 29 of FIG. 2 must divide by 128. Two four bit binary counters in series will divide by 256. Counters are readily available in this form. If two such counters are used, the result counter 25 of FIG.
  • FIG. 3 shows a computing unit such as that of FIG. 2 in more detail.
  • the counters are labelled with the decimal values corresponding to their binary outputs.
  • the step down counter 29 comprises two four bit counters and the value of its most signifi cant bit is 128.
  • Both the dividend and divisor counters l7 and 13 respectively are l2-bit counters made up of three four bit counters and have a most significant bit value of 2048.
  • the result counter 25 comprises two four bit counters preceded by an additional stage which may simply comprise a flip-flop and as illustrated it has a bit value of /s crank angle.
  • the step down counter 29 comprises two four bit counters and the value of its most signifi cant bit is 128.
  • Both the dividend and divisor counters l7 and 13 respectively are l2-bit counters made up of three four bit counters and have a most significant bit value of 2048.
  • the result counter 25 comprises two four bit counters preceded by an additional stage which may simply comprise a flip-flop
  • FIG. 3 solves the following equation:
  • crank angle can be expressed as za' a I 0: MB, here 25 B X (I.
  • FIG. 4 Such an optimized arrangement is illustrated on FIG. 4.
  • the two four bit counters representing the most significant bits in the counter 13 of FIG. are omitted.
  • their associated adders 19 and storage flipflops 27 are omitted.
  • the counter outputs 41 now provide the second inputs to the comparators 23.
  • the carry output of the adder 19 is coupled through a NAND gate to the first counter 41.
  • the NAND gate 43 is enabled by clock pulses from the control circuit 21. Thus, each time a carry is generated, on the next clock pulse, that carry will be entered into the counter 41.
  • a NOR gate is provided having as inputs the outputs of the most significant bit of counter 13 and the output of themost significant bit of counter 17.
  • the output of the NOR gate is coupled as a disabling input to the gate circuits 11 and 15. (This disabling input is not specifically shown in order to simplify the figure.) This permits the arrangement of the present invention to operate with optimum accuracy at all times. Measurement data is counted into the counters until either the divisor counter 2 i.e., the divisor counter 13 or the dividend counter 17 is full and the most significant bit thereby set. In this embodiment, the NOR gate signals the end of data entry.
  • the carry output of adder 19 is coupled into the second bit of the first counter 41 with the least significant bit bypassed.
  • the absolute ignition angle is of interest in an ignition angle measurement.
  • the absolute ignition angle will depend on the relationship between the position of the markings defining the angle [3 with respect to top-dead center designated OT.
  • OT top-dead center
  • a relative ignition angle which is always located in one quadrant is obtained.
  • the selection of 20 after top dead center as a reference point is selected knowing that, in piston engines, timing is almost never retarded beyond after top dead center.
  • the lead angle must be subtracted from the relative value obtained.
  • the angle [3 extends from 20 after to 12 before top dead center.
  • the range over which ignition angle a can be measured extends 64 from the second mark which is 20 after top dead center, in the direction of angular travel 0).
  • the absolute ignition angle is expressed by the following equation:
  • FIG. 6 illustrates a simple manner of carrying out the required subtraction.
  • the result counter is made as a presettable bi-directional counter.
  • a plurality of preset inputs are provided extending from the top, with an arrow indicating that that particular stage is preset to a l and a bar designating that that stage is preset to an 0.
  • the 16 and 4 bits are preset so that the counter contains a count of 20.
  • control circuit 21 isenabled to start counting, in the manner described above, i.e., in counting the number of successive additions required, the counter is first caused to count down until it reaches zero and then caused to count up so that the final count at the end will be the total angular count minus 20.
  • a count direction flip-flop made up of cross coupled NAND gates and designated 51.
  • a reset pulse is provided on line 53 causing the presetting of the stages of the counter 25 representing 16 and 4.
  • This reset line also resets the flip-flop 51 causing it to have an output on line 55 enabling the counter 25 to count down. Counting down continues until zero is reached as detected by the two output lines 57 which are inputs to a NAND gate 59.
  • NAND gate 59 sets the flip-flop 51 changing the signal to the counter 25 to direct'it to count up.
  • the final answer out of the result counter 25 will be an absolute ignition angle.
  • Digital computing apparatus to determine the ignition angle in a piston engine using a division circuit for finding the ratio of two pulse counts
  • division circuit comprises a divisor counter for storing a first pulse count, an adder and sum memory connected in parallel therewith with the outputs of the sum memory coupled as second inputs to the adder, a dividend counter for storing a second pulse count a comparator having as inputs the outputs of the sum memory and the dividend counter, a clock, a result counter, and a control circuit enabled by a start command to couple said clock to said adder and sum memory to cause successive additions to be carried out, said control circuit being disabled by an output from said comparator, said control circuit also coupling said clock to said result counter when enabled to cause said result counter to count the number of successive additions carried out, wherein the improvement comprises:
  • Digital computing apparatus according to claim 1 and further including additional stages in said result counter corresponding to a percentage of said additional factor.
  • said divisor counter has a number of stages omitted equal to the number of stages in said step down counter, with the adders and sum memories normally associated with said omitted stages replaced by an additional counter.
  • said result counter is a presettable bidirectional counter preset to a crank angle prior to the start of the computation.
  • Digital computing apparatus to determine the ig nition angle in a piston engine from the ratio of two pulse counts comprising:
  • a comparator having as inputs the outputs of said sum memory and of said dividend counter and providing an output when the input from said sum memory equals or exceeds the input from said dividend counter;
  • first gating means for gating pulses from said clock into said dividend counter
  • second gating means for gating pulses from said clock into said step down counter
  • control circuit means responsive to a start command to couple said clock to said first and second adders andsum memories to load the adder outputs into the'sum memory inputs, said control circuit also coupling said clock pulses to said result counter. said control circuit being disabled by an output from said comparator.
  • Digital computing apparatus for determining the ignition angle (1 in a piston engine from the ratio of two pulse counts, a first pulse count 2 being proportional to the time I for the crank shaft to rotate through an angle B as defined by two reference marks. and a second pulse count 2.. proportional to the time r required for the crank shaft to rotate through the angle a as defined by one of said reference marks and the point of ignition, the count 2 B being the divisor of said ratio and the count 2 the dividend. said ratio being multipled by the angle B to obtain said angle comprising:
  • a divisor counter in series with said step down counter, the most significant bit output of said step down counter being the input to the least significant bit of said divisor counter;
  • first gating means for gating clock pulses into said step down counter for a time [p to store in said step down counter and said divisor counter the count 2;
  • second gating means for coupling said clock to said dividend counter for a time t to thereby store a count 2
  • a. a full, adder having as many stages as said step down counter and divisor counter combined having first inputs coupled to the outputs of said step down and divisor counters;
  • a further counter having its input coupled to the carry output of said adder, the number of stages in said further counter being equal to the number of stages in said step down counter;
  • a comparator having as first inputs the outputs of said dividend counter and as second inputs the outputs of said further counter and as many stages of said sum memory as required to provide a number of second inputs equal to the number of first inputs;
  • control circuit responsive to a start command for coupling clock pulses to said sum memories to carry out successive additions in said adders, said control circuit further coupling said clock pulses to said result counter.
  • said control circuit being disabled from providing further pulses by an output from said comparator indicating that its second inputs represent a number equal to or greater than that represented by its first input.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Combustion & Propulsion (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Signal Processing (AREA)
  • Combined Controls Of Internal Combustion Engines (AREA)
  • Ignition Installations For Internal Combustion Engines (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
US468573A 1973-05-10 1974-05-09 Digital computer to determine the ignition angle in a piston engine Expired - Lifetime US3895222A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19732323661 DE2323661C3 (de) 1973-05-10 Digitales Rechenwerk zur Bestimmung des Zündwinkels bei Kolben-Brennkraftmaschinen

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US (1) US3895222A (enrdf_load_stackoverflow)
FR (1) FR2229094B1 (enrdf_load_stackoverflow)
GB (1) GB1472874A (enrdf_load_stackoverflow)
IT (1) IT1012143B (enrdf_load_stackoverflow)
SE (1) SE387761B (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2552496A1 (fr) * 1983-09-23 1985-03-29 Bosch Gmbh Robert Dispositif pour la commande electronique de l'instant d'allumage de moteurs a combustion interne; notamment pendant le processus de demarrage
US5975749A (en) * 1997-07-11 1999-11-02 International Business Machines Corporation Zero and one detection chain for a carry select adder

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2501877A1 (fr) * 1981-03-12 1982-09-17 Veglia E D Dispositif de calcul de rapport de deux frequences representatives de deux grandeurs physiques
RU2426908C1 (ru) * 2009-12-09 2011-08-20 Федеральное государственное автономное образовательное учреждение высшего профессионального образования "Южный федеральный университет" (ЮФУ) Система зажигания автомобиля

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3591787A (en) * 1968-01-29 1971-07-06 Ibm Division system and method
US3621218A (en) * 1967-09-29 1971-11-16 Hitachi Ltd High-speed divider utilizing carry save additions
US3684879A (en) * 1970-09-09 1972-08-15 Sperry Rand Corp Division utilizing multiples of the divisor stored in an addressable memory
US3733477A (en) * 1972-02-04 1973-05-15 Control Data Corp Iterative binary divider utilizing multiples of the divisor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE790829A (fr) * 1971-11-22 1973-02-15 Scans Associates Inc Procede et appareil d'essai pour moteurs a combustion interne

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3621218A (en) * 1967-09-29 1971-11-16 Hitachi Ltd High-speed divider utilizing carry save additions
US3591787A (en) * 1968-01-29 1971-07-06 Ibm Division system and method
US3684879A (en) * 1970-09-09 1972-08-15 Sperry Rand Corp Division utilizing multiples of the divisor stored in an addressable memory
US3733477A (en) * 1972-02-04 1973-05-15 Control Data Corp Iterative binary divider utilizing multiples of the divisor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2552496A1 (fr) * 1983-09-23 1985-03-29 Bosch Gmbh Robert Dispositif pour la commande electronique de l'instant d'allumage de moteurs a combustion interne; notamment pendant le processus de demarrage
US5975749A (en) * 1997-07-11 1999-11-02 International Business Machines Corporation Zero and one detection chain for a carry select adder

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FR2229094A1 (enrdf_load_stackoverflow) 1974-12-06
GB1472874A (en) 1977-05-11
DE2323661A1 (de) 1975-01-23
FR2229094B1 (enrdf_load_stackoverflow) 1978-09-22
SE387761B (sv) 1976-09-13
DE2323661B2 (de) 1975-12-11
IT1012143B (it) 1977-03-10

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