US3878324A

US3878324A - Smearing effect attenuator

Info

Publication number: US3878324A
Application number: US457013A
Authority: US
Inventors: Paul S Tubbs; David R Flanders
Original assignee: US Department of Navy
Current assignee: US Department of Navy
Priority date: 1974-04-01
Filing date: 1974-04-01
Publication date: 1975-04-15
Anticipated expiration: 1992-04-15

Abstract

A device for enhancing video reception from a silicon target vidicon by reduction of smeared images. Conventional television scanning parameters are used to display images of the scene being viewed. Light rays from the scene are impinged upon a silicon target of photodiodes within the vidicon. A circuit is provided for grounding the target electrode between successive vertical scans of the electron beam thus reducing the time during which smearing of the image occurs.

Description

United States Patent Tubbs et al.

[ Apr. 15, 1975 SMEARIN G EFFECT ATTENUATOR Inventors: Paul S. Tubbs, Collingswood, N.J.;

David R. Flanders, Pottstown, Pa.

The United States of America as represented by the Secretary of the Navy, Washington, DC.

Filed: Apr. 1, 1974 Appl. No.: 457,013

Assignee:

US. Cl 178/7.2; 178/DlG. 42 Int. Cl l-l04n 5/21; H04n 5/34 Field of Search 178/7.l, 7.2, DlG. 42

References Cited FOREIGN PATENTS OR APPLICATIONS 7/1967 U.S.S.R l78/DlG. 42

Primary ExaminerRobert L. Richardson Attorney, Agent, or Firm-R. S. Sciascia; Henry Hansen ABSTRACT 7 Claims, 3 Drawing Figures PMENTEDAPR 1 5 197a 8 7 8 324 1 m A "1 a F/GIZ TIME SMEARING EFFECT ATTENUATOR STATEMENT OF GOVERNMENT INTEREST The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION This invention relates generally to apparatus for use in reducing smearing in video signals produced by television cameras and more particularly to a device wherein the silicon target of a vidicon is periodically grounded between successive vertical scans of theelectron beam to reduce smearing.

Television cameras that utilize a silicon target vidicon tube receive light rays that are reflected from an image being viewed. The image is focused upon the target which is comprised of photodiodes, and variations in the received light rays alter the electrical characteristics of the individual photodiodes. The tube generates an electron beam which sequentially scans the photodiodes within the target. Each photodiode is scanned once during the vertical field active scan time. In a conventional television scanning system with 2:1 interlace, each of the target photodiodes would therefore be scanned by the electron beam approximately once each 33.3 milliseconds. As the beam passes over the photodiodes. it electrically neutralizes the previous image being viewed. Unfortunately, the neutralizing effect does not entirely remove the previous image and, upon viewing a new or moving image. a certain amount of overlap results from the presence of residual portions of previous images. This causes smearing and general deterioration in picture resolution. The smearing is particularly noticable wherein the image being viewed is close up. rapidly changing, or fast moving.

Prior art methods used to reduce the smearing effect provided gating or pulsing of a light source whose energy was reflected from the scene being viewed. This method necessitated somewhat complex circuitry in order to achieve the needed level of radiation within relatively short time intervals. Physically bulky and high powered illuminators were required for apparatus of this type and operational life was shortened due to the pulsing effect. Spectral filtering at the camera was also needed in order to assure that the camera responds only to the pulsed radiation. Another method utilized in the prior art is to increase the horizontal or the vertical, or both. scanning frequencies. The peripheral equipment necessitated by this mode of operation is often unconventional and relatively expensive.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a device which will enhance the image produced by a silicon target vidicon by reducing smearing effects. Another object is to utilize a relatively simple and compact electronic circuit, the components of which are easily obtainable, assembled, and installed in the respective camera control apparatus or camera itself. Yet another object of the present invention is to retain the scan circuitry and timing utilized within conventional television systems and thereby obviate any possible attendant loss of either vertical or horizontal resolution due to the use of unconventional equipment.

Briefly, these and other objects are accomplished by neutralizing the information content of the entire silicon target of a vidicon and subsequently restoring the target to its normal operating information level within time periods that are synchronized with a conventional vertical drive deflection signal. Light rays from the image being viewed enter the vidicon through a lens assembly which focuses the rays upon the silicon target which is formed from an array of semiconductor p-n junctions. Under conventional operating conditions, the target is constantly reverse biased by applying a nominal dc voltage signal to the target electrode. The target side nearest the vidicon cathode then acquires a positive charge pattern which varies from point to point in accordance with light and dark areas of the viewed image. An electron beam emanating from the cathode scans the target and thus generates the video output signal. In accordance with the present invention, a circuit is provided to periodically discharge the target within the vertical blanking interval between successive vertical fields. The circuit discharges the target by grounding the target electrode during the vertical blanking interval. and gating the target to its normal operating voltage during the active vertical scan intervals.

For a better understanding of these and other aspects of the invention. reference may be made to the following detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a drawing of a vidicon as used within the present invention;

FIG. 2 is a schematic diagram of an electronic biasing and gating circuit used in conjunction with the vidicon shown in FIG. I; and

FIG. 3 is a timing diagram of gating signals processed within the circuit of FIG. 2 and applied to the vidicon shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. I, there is shown a diagram of a typical silicon target vidicon 10 operating in conjunction with incoming light rays 12 which are reflected from an external scene (not shown).

A lens assembly 14 focuses the incoming light rays 12 upon a face plate 16. An array of semiconductor p-n junctions such as, for example, photodiodes constitutes a silicon target 18 mounted adjacent to and in contact with the rear of the face plate 16. An electrode 20 provides an electrical connection to the target 18. At the rear of the vidicon 10, a cathode 22 generates electrons which are formed into an electron beam 24 which is directed toward the target 18.

Referring now to FIG. 2, there is shown a schematic diagram of an electronic gating circuit which is suitable for use in conjunction with the vidicon 10 shown in FIG. 1. A resistor 28 and a capacitor 30 are parallely connected at one end to receive an input signal at an input terminal 26 and are connected at the other end in common with the base of a first transistor 32 and one end of a resistor 34 whose other end is connected to a positive voltage source of approximately 6 volts. A resistor 36 is connected between the emitter of the transistor 32 and ground. The collector of transistor 32 is commonly connected to one end of a first resistor 38,

a second resistor 40, and a capacitor 42. The other ends of resistor 40 and capacitor 42 are commonly connected to the base of a second transistor 44 whose emitter is connected to ground. The collector of transistor 44 is commonly connected to one end of a resistor 46 and a capacitor 48. The other end of resistor 46 is commonly connected with the remaining end of resistor 38 to a negative voltage source of approximately 20 volts. The other end of capacitor 48 is commonly connected to the cathodes of a first diode 50 and a second diode 52. The anode of diode 50 is connected to ground and the anode of diode 52 is commonly connected to one end of a resistor 54, whose other end is connected to a positive voltage source of approximately 20 volts, and an output terminal 56.

The operation of the invention will now be described with reference to FIG. 1 in conjunction with FIG. 2 and FIG. 3. The light rays 12 reflected from the image being viewed (not shown) enter the vidicon through the face plate 16. The lens assembly 14 focuses the rays 12 upon the silicon target 18. The silicon target 18 is formed from an array of semiconductor p-n junctions such as. for example. photodiodes. Under conventional operating conditions the silicon target 18 is reverse biased by applying a positive constant voltage of approximately 8-l0 volts dc to the target electrode 20. With such a biasing voltage applied, the side of the target nearest the cathode 22 acquires a positive charge pattern which varies from point to point in accordance with the light and dark areas associated with the image being viewed. The electron beam 24 which emanates from the cathode 22 neutralizes the positive charge pattern on target 18 and thereby generates small voltage variations on the target electrode which represents the video output signal from the vidicon I0. Assuming conventional television operation with double (2:1 interlace and a vertical scanning rate of 60 fields per second. two-sixtieth of a second or approximately 33.3 milliseconds elapses between successive vertical scans of any particular photodiode within the target 18. This scanning time concept is shown in waveform A of FIG. 3 wherein a periodic pulse typical of a conventional vertical drive signal is shown, As obvious to those skilled in the art. such a vertical drive signal might be most easily obtained from a convenient signal point with conventional vertical and horizontal deflection circuitry which is utilized to cause the beam 24 to scan the target 18. A field of vertical lines is scanned every 16.6 milliseconds. which time period is denoted as t,,r in waveform A. The full scan period t.,t is partitioned into a vertical blanking interval l,,t, of approximately [.2 milliseconds and an active vertical scan period t,t of approximately 15.4 milliseconds. Since there is a 2:] vertical interlace, field No. 2 is shown being sequentially scanned after field No. l. The blanking time period -1 is used by the present invention to discharge the entire target 18 and thereby neutralize any information content that may have been superimposed upon it. Target 18 is then subsequently restored to its normal operating voltage range during the active scan time 1,4

By gating the target 18 between a neutralizing potential such as ground and a positive dc voltage, it is ensured that the entire target 18 is neutralized once each field time of 16.6 milliseconds. Since the target 18 is discharged only during the vertical blanking time interval in which image information is not acted upon by the vidicon 10, the active scan time remains undisturbed with normal scanning resolution being maintained. As will now be obvious to those skilled in the art. the present invention reduces smearing by neutralizing the entire target 18 every 16.6 milliseconds as opposed to neutralization by the electron beam 24 every 33.3 milliseconds in a conventional camera system.

Referring now to FIG. 2, there is provided an electronic circuit to assure synchronization and proper signal amplitude for periodically discharging and restoring the target 18. The input signal to the circuit of FIG. 2 comprises a conventional vertical drive signal as shown in waveform A of FIG. 3. Such an input signal typically provides a periodic pulse ranging from a zero voltage level to an approximate negative 4 volts and is synchronized with the vertical scan of the vidicon target by the bear 24. The input signal is amplified by a first amplifier

stage comprising resistors

28, 34, 36, 38; capacitor 30; and transistor 32. The output signal of the first amplifier stage is produced at the collector of transistor 32 and forms a pulse type waveform varying between --20 volts and 2 volts. Resistor 28 and capacitor 30 are used to improve the rise times of the input signal to the first amplifier stage. A second amplifier comprising resistors 40 and 46., capacitor 42, and transistor 44 further amplifies the signal from the first amplifier stage and produces an output signal which varies between ground and negative 20 volts at the collector of transistor 44. Resistor 40 and capacitor 42 function to improve the rise times of the input signal to the second amplifier. Capacitor 48 and diode 50 form a clamping circuit which clamps the peak negative voltage of the second amaplifier output signal to ground. Amplitude distoration of the signal appearing at the junction of capacitor 48 and the cathode of diode 50 is eliminated by the use of a diode-resistor logic circuit formed from diode 52 and resistor 54. The gating circuit output signal is provided at the output terminal 56 in the form of pulse as shown in waveform B of FIG. 3 and which is in synchronization with and approximately five times the voltage amplitude of the input signal. The component values which have provided the most optimum results for the circuit illustrated in FIG. 2'are as noted in Table I shown hereinbelow.

When applied to the electrode 20 of the vidicon 10, the output signal discharges the target 18 during the vertical blanking time intervals by biasing the target to a ground potential and thereby neutralizing previous target information. When beam 24 begins to actively scan the target 18, the output signal applies a positive voltage of approximately 20 volts. While the foregoing teachings have illustrated a gating signal which ranges between zero and +20 volts, it has been determined that other voltages substantially approaching the foregoing values are capable of producing satisfactory results. For example, the neutralizing potential may be made slightly negative or the activating potential may range from approximately +11 to +20 volts dc. Obviously, one skilled in the art could adjust, for example, the supply voltages in the circuit of FIG. 2 in order to effect a varying range of output signal levels.

Thus it may be seen that there has been provided a novel device for reducing smeared images in a silicon target vidicon by repetitively grounding the target during inactive vertical scanning times.

Obviously, many modifications and variations of the invention are possible in light of the above teachings, it is therefore to be understood that within the scope of the appended claims the invention may be practiced than as specifically described.

What is claimed is:

1. In a television camera system including a vidicon tube and horizontal and vertical drive circuits. the vertical drive circuit generating a signal having a first voltage level indicative of a vertical blanking interval and a second voltage level indicative of a vertical active scan time; wherein the improvement comprises.

gating means receiving the vertical drive circuit signal for producing an output signal in phase with the vertical signal and having a first voltage level at substantially ground potential and a second voltage level of positive polarity; and

terminal means electrically connected between the target of said vidicon tube and said gating means for receiving the output thereof;

whereby said target is neutralized upon receipt of said gating means output signal first level and is activated upon receipt of said gating means output signal second level.

2. The improvement according to claim 1 wherein said gating means further comprises:

amplifying means adapted to receive the vertical drive circuit signal and for producing an amplified output signal having first and second voltage levels in phase with the vertical drive circuit signal; clamping means connected to receive said amplifying means output signal for clamping the first voltage level thereof to a substantially ground potential and for producing an output signal having first and second levels in phase with the vertical drive circuit signal; and

logic means connected to receive said clamping means output signal for changing the second voltage level thereof to a positive polarity and for producing said gating means output signal.

3. The improvement according to claim 2 wherein said amplifying means further comprises:

a first transistor having a base operatively connected to receive the vertical drive circuit signal. an emitter operatively connected to ground and a collector for producing an output signal; and

a second transistor having a base operatively connected to receive said first transistor output signal, and emitter connected to ground and a collector for producing said amplifying means output signal.

4. The improvement according to claim 3 wherein said clamping means further comprises:

a capacitor connected to receive at one end the amplifying means output signal; and

a diode having an anode connected to ground and a cathode connected to the other end of said capacitor for providing said clamping means output signal.

5. The improvement according to claim 4 wherein said logic means further comprises:

a diode having a cathode connected to receive said clamping means output signal and an anode; and

a resistor for receiving a positive voltage at one end and connected to the anode of said logic means second diode at the other end for producing said gating means output signal.

6. The improvement according to claim 1 wherein said target comprises photodiodes.

7. The improvement according to claim 3 wherein said amplifying means first and second transistors are of pnp type.

Claims

1. In a television camera system including a vidicon tube and horizontal and vertical drive circuits, the vertical drive circuit generating a signal having a first voltage level indicative of a vertical blanking interval and a second voltage level indicative of a vertical active scan time; wherein the improvement comprises. gating means receiving the vertical drive circuit signal for producing an output signal in phase with the vertical signal and having a firsT voltage level at substantially ground potential and a second voltage level of positive polarity; and terminal means electrically connected between the target of said vidicon tube and said gating means for receiving the output thereof; whereby said target is neutralized upon receipt of said gating means output signal first level and is activated upon receipt of said gating means output signal second level.

2. The improvement according to claim 1 wherein said gating means further comprises: amplifying means adapted to receive the vertical drive circuit signal and for producing an amplified output signal having first and second voltage levels in phase with the vertical drive circuit signal; clamping means connected to receive said amplifying means output signal for clamping the first voltage level thereof to a substantially ground potential and for producing an output signal having first and second levels in phase with the vertical drive circuit signal; and logic means connected to receive said clamping means output signal for changing the second voltage level thereof to a positive polarity and for producing said gating means output signal.

3. The improvement according to claim 2 wherein said amplifying means further comprises: a first transistor having a base operatively connected to receive the vertical drive circuit signal, an emitter operatively connected to ground and a collector for producing an output signal; and a second transistor having a base operatively connected to receive said first transistor output signal, and emitter connected to ground and a collector for producing said amplifying means output signal.

4. The improvement according to claim 3 wherein said clamping means further comprises: a capacitor connected to receive at one end the amplifying means output signal; and a diode having an anode connected to ground and a cathode connected to the other end of said capacitor for providing said clamping means output signal.

5. The improvement according to claim 4 wherein said logic means further comprises: a diode having a cathode connected to receive said clamping means output signal and an anode; and a resistor for receiving a positive voltage at one end and connected to the anode of said logic means second diode at the other end for producing said gating means output signal.