US3875340A - Digital system forming a frequency multiplex system - Google Patents

Digital system forming a frequency multiplex system Download PDF

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US3875340A
US3875340A US376169A US37616973A US3875340A US 3875340 A US3875340 A US 3875340A US 376169 A US376169 A US 376169A US 37616973 A US37616973 A US 37616973A US 3875340 A US3875340 A US 3875340A
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digital
values
quadrature
frequency
output
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US376169A
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English (en)
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Marie-Annick Roy
Alain Cabet
Patrice Desombre
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Alcatel CIT SA
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Alcatel CIT SA
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H04J1/02—Details
    • H04J1/04—Frequency-transposition arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H04J1/02—Details
    • H04J1/04—Frequency-transposition arrangements
    • H04J1/05—Frequency-transposition arrangements using digital techniques

Definitions

  • Frmcc 74032 nels furnishes a band of a frequency multiplex system, for example, a primary base group of twelve channels [s2] U 8 Cl 179/15 FD 79/15 FS of4 kHz each, covering the band 60 108 kHz. and ['51] H04j "04 comprises between an analog-digital input converter [-58] Field '5 F5 receiving the voice frequency channels and a digitalnglls analog output converter emitting the desired band. only members of the digital type operating on digital [56] References Cited information or data words.”
  • a system which furnishes from n voice frequency channels a hand of a frequency multiplex system.
  • the application envisaged is the provision of frequency multiplex systems for telephone transmission.
  • a frequency multiples system or a portion of a frequency multiplex system. for example a primary hase group. by two modulation steps: a first modulation. or premodulution. which furnishes premodulation channels all having the same disposition in the spectrum. and then a second modulation. which has the effect of transposing each premodulated channel into one of the channels of the primary hase group taken as an example. or twelve channels each occupying 4 kHz hetvveen (i and I0? kHl. Such manipulations are effected by means of modulators and associated filters.
  • One particularly advantageous means for producing transposed channels is a modulator with two paths in parallel. one of which comprises a lirst modulator receiving one voice frequency channel and moreover a current ofcos ,1. (II I 'rrFI followed by a low-pass filter and by a second modulator supplied furthermore with a current ofcos IL -I. (1 I I 1W2). and the second path of which comprises a third modulator receiving a current of sin 12,1. followed hy a low-pass filter. and by a fourth modulator supplied with a current of sin $2 1. the output currents of the second and of the fourth modulators heing added in order to furnish at the output the transposed channel.
  • the present invention applies this principle to a de vice having a digital operation between an analogdigital input converter and a digital-analog output converter by manipulating words of a predetermined numher of hits. for example p hits. each of which represents a coded digital value. but while the simple transposition of the analog into the digital method would require two parallel paths of digital operation. the present invention. making use of properties peculiar to the digital operation. employs only a single path. and the only price paid for this simplification of the apparatus is that the frequency of the clock which serves for setting the frequency of operation of the system must he douhled.
  • FIGv I is a schematic diagram of the overall multipleving system according to the present invention.
  • FIG. 2 is a more detailed diagram of the multiplier/- logic and buffer memory portion of the system according to FIG. 1:
  • FIG. 3 illustrates the spectral composition of the different signals
  • FIG. 4 is a schematic diagram showing the application of an implement according to the present invention to a multiplexing system of a more elevated order.
  • FIG. 5 is a diagram of the application of two systems according to the present invention to a multiplexing system of a higher order.
  • FIG. I provides for the multiplexing of II II voice frequency channels covering a total width of 4 kHz into a primary hase group of (i0 I08 kHY.
  • the sampling frequency for a group having a width of 48 kHr is selected to he equal to I-Iv l 1'. kHl l-l X 3 Jv
  • the n channels I ton are applied to an analog-digital converter [0 on a time-sharing hasis. operating at a clock frequency H: I: X Iii I: X l 12 kHv.
  • the movahle contact of the commutator II applies a signal X. .tl) to one input of a suhassemhly I2 which comprises essentially a multiplier and a logic circuit which receives the output of a commutator I3 operating at a frequency of IN: 24 X I I2 kH/ and which furnishes during alternate times a signal cos III I,- and a signal sin !Il!,-. wherein II, 2 7T I"l.
  • the period of I"! 1.850 Hr is 540 us. the frame period heing 8.) us. and there results therefrom a total numher of the values of cos II equal to a little more than o0 per period l/I-l. and as many l'or sin Ila. Each of these values is maintained identical during a frame period of 8.) us. These values are coded in p hits. and it will he assumed for example that p 12.
  • the suhassemhly I2 is also set to a frequency of 2H1. It has two outputs on two buffer memories I4 and I5. From the first one there issues a signal i (I). a product of .v (it by cos 11,1; from the other one there issues a signal .v (I). a product of A (I) by sin ll i.
  • the signals .t;i (I) and i (I) are applied via an ()R cireuit [6 to the input of a conventional digital filter I7 having a pass-hand of Fl t 3/2.
  • the digital filter l7 delivers at the output of a third buffer memory [8 a signal .v (I) and at the output of a fourth buffer memory 19 a quadrature signal .i. t l).
  • the two signals heing applied via an OR circuit 20 to one input of a suhassemhly 2
  • the subassembly 21 receives the output of a commutator 22 which. during a frame period of 8.9 as. picks up l2 values of cos (a r and l'. values of sin w, A varying from l to II.
  • From subassembly 2! issues a signal with 1 bits 1;. (I I. and the signal in quadrature R. (ll.
  • the first signal at the output of a buffer memory 23 and the second signal are applied to the inputs of an adder 24.
  • From adder 24 issues a signal n, I] which is applied to a digital-analog converter 25.
  • the members 23. 24 and 25 operate at a frequency Fh.
  • Fl(i. 2 is a more detailed diagram of the members l2. l4 and IS.
  • the subassembly 12 comprises a multiplier M] which receives on the one hand the p bits of the signal (I). the coding of a channel sample coming from the commutator 1] (FIG. ll.
  • the multiplier Ml receives by way of p ()R circuits 34 the output signals of AND gates 3
  • the buffer memory 14 comprises a first series of p AND gates 35 which receive the outputs l p of the multiplier Ml respectively. as well as the clock signal 2Fh via an inverter 37. which receives the clock signal as well as a second series of AND gates 36. each of which receives the output signal of the AND gate 35 of the saute order and the clock signal ZFh having traversed two inverters 4] and 38 in series.
  • the buffer memory I5 is constituted in an exactly identical fashion with a first series of AND gates 39 receiving the clock signal 2Fh and a second series of AND gates 40 receiving via the inverter 4
  • p ()R circuits 16 each receive an output of the buffer memory I4 and the output of the same order of the buffer memory 15. The outputs of these ()R circuits 16 are applied to the input of the digital filter 17.
  • two buffer memories l8 and 19 are connected exactly in the same fashion as the memories 14 and IS are connected to subassembly I2. This arrangement allows for timesharing of the equipment for each of the two terms in quadrature A ⁇ . (I) and i (1). .v (r) and L (1). respectively.
  • a single buffer memory 23 suffices for applying the terms x (I and i (1) to the adder 24.
  • FIG. 3 shows the spectral composition of the different signals.
  • the hand width W301) 3.40GHz) of the low frcquency signal has been replaced by b (0 4.000 H7). or Fl h/Z. which changes nothing in principle.
  • FIG. 4 shows schematically the application of a multiplexer according to the present invention to the generation of a secondary group of channels covering 312 553 kH7 from two synchronized PCM frames. with 32 channels each. of which 30 are information channels and two are auxiliary channels. For a pass band of 240 kHz. the sampling frequency of the multiplexer must be greater than 480 kHz, and it has been assumed to be equal to 73 X 8 I 584 kHz.
  • Two PM frames. T, and T are provided with a frequency of 2,048 kH/ (32 channels sampled at the fre' quency of 8 kHz. definition of 8 bits).
  • the same clock H serves for setting the frequency for the two synchronized frames at the input. [Zach of these frames is received in a buffer memory (M,. M each containing 30 channels. It is necessary to pass from the PCM frequency to the input frequency of the multiplexer which. for (10 channels. is equal to (it) X 584 kHv. This is done by means of a subassembly G comprising at the input a commutator K. an assembly R of 73 delay lines T in cascade. of l.7 as each. whose outputs are collected by an ()R circuit J. The sub-assembly (i is operated at a frequency of (10 X 584 kHl.
  • a subassembly 0 corresponding to the members l2. l3 23 of FIG. I operating at a frequency of 584 X (it) X 1 kH/ is connected to the output of OR gate J.
  • the frequency of the first modulation Fl is always equal to [.850 Hz.
  • the frequencies of the second modulation. E fk at the number (it). are graduated from 34 to 271) kH/, from 4 to 4 kH/..
  • the subassembly is followed by a subtraction and nonaddition member 28. like the member 24 of PIG. I. so as to take into account the desired sense or direction of the modulation. which is here direct. instead of the inverted sense or direction in the primary base group.
  • the subtraction member 28 is followed by a digitalanalog converter 2) and by a filter 30 with a passband of 3 l 2 552 kH/ at the output of which the secondary group is found at terminal 30a.
  • the members 28 and 2) are operated at the frequency of (it) X 584 kHv.
  • the two synchroniycd input PCM framesT, and T are thus directly transposed into a secondary group of a frequency multiplex.
  • the operating frequency has been indicated beside each member.
  • FIG. 5 has reference to the direct transposition of two PCM frames T, and T,, of 32 channels each. which are not synchronized. into a secondary group of 60 channels 312 552 kHz of a frequency multiplex system.
  • Each frame is set in frequency by its own clock HI and Hlll. Each of these frames is received in the memory MI and MI].
  • the equipment comprises two unitary multiplexers. one formed by elements (ll. Ql. 28l and 29]. the other of eletncnts (ill. OH. 28 and 29]]. These members or subassemblies have a structure and operation analo gous to the elements (i. Q. 28. 29 of FIG. 4. Elements (il and (ill are operated at a frequency of X 584 kHv. elements ()l and OH at a frequency of 2 X 30 X 584 kHz. and elements 28L 28H. 29". and 29" are operated at a frequency of 30 X 584 kHz. At the output of the band-pass filter 30 there is found at terminal 3011 the secondary group 3 l 2 552 kHz. The operating frequency has been indicated beside each member in FIG. 4.
  • a digital system for forming a frequency multiplex group from n incoming channels, operated at a sampling frequency Fs. comprising analog-digital conversion means receiving said 11 incoming channels and furnishing digital values .t!l at the output thereof, first multiplication means for multiplying said digital values .r- .(Il by alternate digital values of cos Ila-F and sin 2111",! and furnishing signals .Yggt ⁇ and Rat! in quadrature. operating at the frequency 2/) Fs. digital filtering means for receiving in common said values . ⁇ 1-,(t) and i t!) and furnishing digital values .r and .iql! in quadrature.
  • second multiplication means operating at the frequency 2n Fs and receiving in common said quadrature values . ⁇ ,(I) and .i.(! for multiplying said values alternately by digital values of cos Err/L! and sin 211151. wherein It varies from l to :1.
  • addition means operating at the frequency n Fs and receiving output signals . ⁇ ;,l I and .t -.(1) in quadrature from said second multiplication means for furnishing signals . ⁇ ',;(t). a digitalanalog converter connected to the output of said addition means. and an analog band-pass filter having a bandwidth of fill Hi8 kHv connected to the output of said digital-analog converter.
  • a system according to claim 1. characterized in that said digital filtering means is associated with an input logic circuit operating as a buffer memory for the alternate application of said values Xgt') and .t tl) in quadrature to said filtering means. and with an output logic circuit operating as a buffer memory for the alternate extraction of the two series of products in quadrature from said filtering means.
  • a system according to claim I. further including means for repeating n times the same value of cos Z'n'F I; and n times the same value of sin ZTrF I; at the input of said first multiplication means.
  • a system according to claim 4. further including means for selectivelychanging said sampling frequency Fr connected to the input of said analog-digital conver sion means.
  • a digital system for forming a frequency multiplex group from two non-synchronized PCM frames. comprising first and second system groups connected to said PCM frames. respectively. said first and second system groups terminating in common at a single bandpass filter. each system group comprising means for changing the sampling frequency of the system.
  • analogdigital conversion means receiving said n incoming channels and furnishing digital values .Ygl) at the output thereof.
  • digital filtering means for receiving in common said values AMI) and i t! and furnishing digital values 14(1) and fat) in quadrature.
  • second multiplication means operating at the frequency In Fx and receiving in common said quadrature values 1) and .f',(! l for multiplying said values alternately by digital values of cos 211 and sin Err/ill. wherein it varies from I to n.
  • addition means operating at the frequency n Fs and receiving output signals . ⁇ '.-,(I) and -,(t) in quadrature from said second multiplication means for furnishing signals . ⁇ '.;(l). and a digital-analog converter connected to the output of said addition means.
  • a system according to claim 7. characteriled in that said second multiplication means is associated with an input logic circuit operating as a buffer memory for the alternate application of said values .utl) and .i tl) in quadrature to said second multiplication means. said addition means being connected to said second multiplication means by means of a direct connection by means of a single logic circuit operating as a buffer memory.
  • a system according to claim 6. further including means for repeating n times the same value of cos 21rF i,- and n times the same value of sin Zn-Fa, at the input of said first multiplication means.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Analogue/Digital Conversion (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
US376169A 1972-07-03 1973-07-03 Digital system forming a frequency multiplex system Expired - Lifetime US3875340A (en)

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FR7224032A FR2191826A5 (fr) 1972-07-03 1972-07-03

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US (1) US3875340A (fr)
BE (1) BE801780A (fr)
DE (1) DE2333870A1 (fr)
FR (1) FR2191826A5 (fr)
GB (1) GB1437205A (fr)
IE (1) IE37872B1 (fr)
IT (1) IT991652B (fr)
LU (1) LU67901A1 (fr)
NL (1) NL7309282A (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001510A (en) * 1975-07-07 1977-01-04 Motorola, Inc. Digital modulator and demodulator system for fdm telephony
US4086536A (en) * 1975-06-24 1978-04-25 Honeywell Inc. Single sideband transmitter apparatus
US4316282A (en) * 1979-11-23 1982-02-16 Rca Corporation Multichannel frequency translation of sampled waveforms by decimation and interpolation
DE3626862A1 (de) * 1986-08-08 1988-02-11 Philips Patentverwaltung Mehrstufige sender- antennenkoppeleinrichtung
US4759013A (en) * 1985-09-10 1988-07-19 Nec Corporation FDM-TDM transmultiplexing system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3120445A1 (de) * 1981-05-22 1983-05-26 AEG-Telefunken Nachrichtentechnik GmbH, 7150 Backnang Verfahren zur frequenzvertausch von teilbaendern

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3676598A (en) * 1970-06-08 1972-07-11 Bell Telephone Labor Inc Frequency division multiplex single-sideband modulation system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3676598A (en) * 1970-06-08 1972-07-11 Bell Telephone Labor Inc Frequency division multiplex single-sideband modulation system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4086536A (en) * 1975-06-24 1978-04-25 Honeywell Inc. Single sideband transmitter apparatus
US4001510A (en) * 1975-07-07 1977-01-04 Motorola, Inc. Digital modulator and demodulator system for fdm telephony
US4316282A (en) * 1979-11-23 1982-02-16 Rca Corporation Multichannel frequency translation of sampled waveforms by decimation and interpolation
US4759013A (en) * 1985-09-10 1988-07-19 Nec Corporation FDM-TDM transmultiplexing system
DE3626862A1 (de) * 1986-08-08 1988-02-11 Philips Patentverwaltung Mehrstufige sender- antennenkoppeleinrichtung

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IE37872B1 (en) 1977-11-09
DE2333870A1 (de) 1974-01-17
IE37872L (en) 1974-01-03
BE801780A (fr) 1974-01-02
LU67901A1 (fr) 1974-01-03
IT991652B (it) 1975-08-30
NL7309282A (fr) 1974-01-07
GB1437205A (en) 1976-05-26
FR2191826A5 (fr) 1974-02-01

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