US3858196A

US3858196A - Display system employing digitally-addressable crt

Info

Publication number: US3858196A
Application number: US00401294A
Authority: US
Inventors: J Vrabel; E Hilborn
Original assignee: DEPARTMENT OF TRANSPORTION
Current assignee: DEPARTMENT OF TRANSPORTION
Priority date: 1973-09-27
Filing date: 1973-09-27
Publication date: 1974-12-31
Anticipated expiration: 1991-12-31

Abstract

A message display system employing a digitally-addressable shaped-beam cathode ray tube is disclosed. The tube includes a message portion defining mask associated with each of a plurality of cathodes. A composite message commensurate with a plurality of masks is displayed by means of addressing the individual cathodes rapidly in a time-shared manner.

Description

United States Patent [191 Vrabel et a1.

m1 3,858,196 [451 Dec. 31,1974

DISPLAY SYSTEM EMPLOYING DIGITALLY-ADDRESSABLE CRT Inventors: Joseph D. Vrabel, Concord; Edwin H. Hilborn, Framingham, both of Mass.

Appl. No.: 401,294

Assignee:

US. Cl 340/324 A, 313/71, 315/13 R,

340/366 CA Int. Cl. G08b 5/36 Field of Search..... 340/324 A, 324 AD, 324 R, 340/366 CA; 178/15, 30; 315/13 R, 21 CH,

[5 6] References Cited UNITED STATES PATENTS 3,111,598 11/1963 Tatham 340/324 A 3,131,328 4/1964 McNaney.... 340/324 A 3,701,988 10/1972 Allaart 340/324 A Primary ExaminerDavid L. Trafton Attorney, Agent, or Firml-1erbert E. Farmer; Harold P. Deeley, Jr.

[5 7] ABSTRACT A message display system employing a digitallyaddressable shaped-beam cathode ray tube is disclosed. The tube includes a message portion defining mask associated with each of a plurality of cathodes. A composite message commensurate with a plurality of masks is displayed by means of addressing the individual cathodes rapidly in a time-shared manner.

13 Claims, 3 Drawing Figures READ ONLY BINARY-TO-OCTAL LEVEL SHIFTER MEMORY) I DECODERS /ARRAYS A a, 1 RECIRCULATING D; 1+ 514 1+ 6 6 53 SHIFT REGISTER D3 BLANK H23 1%; 1 (CURRENT LIMITING A3 8 D RESISTOR ARRAYS 32 4 99 SPACE D5 is u E -u- A2 50 D6 BLANK A| ADDRESS END-OF-MESSAGE EOM REGISTER 3 8 D7 R NTER ENTER REClR CLR EECIR cu CK 6 o 1 62 3 -DS Q WORD R COUNTER Fl ENTER MESSAGE REGISTER- PMENTED 3,858.196

sum 10F 2 DISPLAY SYSTEM EMPLOYING DIGITALLY-ADDRESSABLE CRT ORIGIN OF THE INVENTION The invention described herein was made by employees of the United States government and may be manufactured and used by or for the government for governmental purposes without the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the display of information. More specifically, this invention is directed to a display system employing a cathode ray tube having a plurality of cathodes, each associated with a separate character or message, which are addressed individually in a time-shared manner. Accordingly, the general objects of the present invention are to provide novel and improved methods and apparatus of such character.

2. Description of the Prior Art There are, of course, numerous devices available for receiving and displaying information. The primary objective of adisplay system is that it present the received message in an easily readable and intelligible form. For many applications it is also important that the complete message, as opposed to a character-by-character display, be presented on the display immediately upon the end-of-message transmission.

There are, of course, numerous applications where it is considered desirable to code a message prior to transmission. Examples of such applications are air traffic control wherein use of digital coding represents a substantial increase in transmission speed thereby conserving already severely limited available transmission time. A further example of a field in which message coding is considered preferable is the area of public safey where, for numerous and obvious reasons, it is desired to prevent unauthorized individuals from monitoring communications. Transmission of information in coded form, however, has previously imposed decoding and storage delays on display systems wherein it was desired to simultaneously present all the characters comprising a message to a viewer.

The cathode ray tube is one of the most widely used prior art display devices. Modern cathode ray tubes have the decided advantages of small size coupled with an easily readable display. Prior art message display systems employing cathode ray tubes, however, have a number of serious limitations. The most serious of these limitations has been the inability to display, immediately upon receipt, a complex multi-character message. While complex messages could previously be displayed, this result could only be achieved through the use of devices such as video tape recorders which would be used to store the message for playback. The use of devices such as video tape recorders greatly increases the size, weight and complexity of the display system and thus has a deleterious effect on cost and reliability.

SUMMARY OF THE INVENTION The present invention overcomes the above briefly discussed and numerous other deficiencies and disadvantages of the prior art by providing novel and improved techniques and apparatus for the display of complex messages on a cathode ray tube. In accomplishing the foregoing general objectives the present invention comprises a message coding and address scheme for a digitally-addressable shaped-beam cathode ray tube. Thus, in accordance with the invention, a cathode ray tube having a plurality of separate cathodes is employed. A mask containing a message which the electron optics of the tube enlarges to cover the entire area of the tube face is associated with each cathode. The invention contemplates decoding and storing the received message and thereafter addressing the individual cathodes rapidly in a time-shared manner so as to combine messages or portions of messages as defined by the masks thereby presenting a complex message in easily readable form.

BRIEF DESCRIPTION OF THE DRAWING The present invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawing in which:

FIG. 1 is a front view of a mask which may be incorporated in a cathode ray tube employed in a display system in accordance with the invention and intended for use in air traffic control;

FIG. 2 is a block diagram of time-share circuitry for use in a display system in accordance with a preferred embodiment of the invention; and

FIG. 3 is a timing diagram relative to the operation of the circuitry of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention employs, as a display device, a shaped beam cathode ray tube of the type generally known in the art as a CHARACTRON. The display tubes of the present invention employ multiple cathodes and have no deflection circuitry. Thus, the present invention may, for example, employ a 6500 Series NIMO cathode ray tube available from Industrial Electronic Engineers, Inc. of Van Nuys, Calif; the IEE 6500 Series tubes having 64 separate cathodes.

As is conventional practice, each of the cathodes of the display tube is arranged in juxtaposition to a selected portion of an etched mask. An example of such a mask is shown schematically in FIG. 1. Through the use of a high quality mask, readily readable alphanumeric characters and symbols can be displayed on the face of the tube. Such a display will, in fact, be more readable than characters generated by conventional prior art vector writing techniques with a finely focused beam. Thus, energization of a selected cathode will result in a message commensurate with the etched portion of the mask associated with that cathode being displayed; the message being enlarged by the electron optics of the tube to cover the entire area of the tube face. In accordance with the present invention, the mask may be formed in such a manner that the majority of the tube face will in each case be blanked and each of the 64 etched portions of the shadow mask will occupy its own discrete screen area. Alternatively, as in the case of the mask of FIG. 1, selected mask portions, hereinafter individually called masks, may contain message portions which are never displayed simultaneously.

Considering further the display tube employed with the present invention, each cathode and its associated mask can be thought of as being equivalent to a slide projector. Accordingly, in the same manner that multiple slide projectors could be focused onto a common projection screen to combine messages or portions of messages, the display tube employed with the present invention can provide similar capability using electron optics instead of conventional optics. This objective is achieved by logic circuitry which addresses the cathodes of the display tube individually. Multiple messages; i.e., a plurality of cathodes; can not be addressed simultaneously since this would result in cross-talk between rows and columns and the concomitant presentation of additional unwanted messages. Accordingly, the present invention encompasses a novel method for addressing the individual cathodes rapidly in a timeshared manner.

As discussed briefly above, and as will be obvious from FIG. 1, the position at which a given message or portion of a message appears on the screen is entirely a function of the geometry of the cathode and mask positioning. With the FIG. 1 mask a maximum of six characters on each of three lines is employed. Certain of the messages do not require numerical values. However, when numerical values are required, they always appear on the lower line of the display. Examples of messages which do not require numerical values are cathodes Y-l, X-1;Y-ll, X-2, and Y-l, X-8. Other messages require a three-digit numerical value. Thus, by sequentially addressing mask positions (cathodes) Y-l, X-7;

Y-4, X-l; Y-5, X-7 and Y-6, X-8 at a flicker-free rate would yield the message:

SPEED Using mask portions Y-l, X-7; Y-4, X-7; Y-7, X-l and Y-S, X-3 the following more symmetrical presentation of the same message results:

SPEED Thus, by addressing combinations of four masks in the manner to be described below, any required numerical value through three digits can be presented for heading, altitude and speed.

4 Alerts to traffic normally inform the pilot of the clock position and distance to the potential threat. Thus, in order to alert the pilot to traffic at 11 oclock and 3 miles distance cathodes Y-3, X-l; Y-4, X-l; Y-4, X-7 and Y-7, X-8 would be time-shared and the message would appear as:

TRAFIC l l 3NM TOWER It should be obvious that the blocks which appear in FIG. 1 will not be displayed as part of the message and have been provided merely to indicate the location of characters.

With reference now jointly to FIGS. 2 and 3, the operation of a preferred embodiment of a display system in accordance with the present invention will be described. When power is initially applied the system will be cleared by presenting a certain code, known as the address code, to inputs A A ofa read only memory 30. The read only memory 30, which may be comprised of a pair of National Semiconductors, Inc. type MM5203Q memories, converts the input code to an intermediate code for the purposes to be described below. The read only memory 30 will always provide a true" output on its address output line when the address code is presented to the input of memory 30,'regardless of the status of input lines A -A and will provide a false" output on the address line at all other times. When the address output line of memory 30 goes true a positive pulse will be applied to the clear" (CLR) input of a recirculating shift register network 32. Shift register network 32 may be comprised of seven shift registers with seven bits in each register and may be assembled from RCA type CD4015AE shift registers and RCA CD4019 AND/OR gates. When the address output line of memory 30 goes true, the shift register network 32 will be cleared and, additionally, an enter message register 34 will be set. Register 34 may comprise an RCA type CD4OI3AE flip-flop. The true output on the address output line of memory 30 is also applied, via an OR gate 36, to the reset input of an end-of-message register 38 and, via an inverter 40, to a first input of AND gate 42. Register 38 may be identical to register 34 and OR gate 36 may be comprised of an RCA type CD 400lAE NOR gate and an RCA type CD4009AE inverter. It is to be observed that, while not limited thereto, the invention is being described in terms of positive logic and the components commercially available are inverting NAND and NOR gates.

The output of inverter 40, which may also be an RCA type CD4009AE inverter, will be in the false state when the address output line of memory 30 is true and gate 42 will accordingly, be disabled. The AND gate 42, which may be comprised of an RCA type CD4025 NAND gate and an RCA type CD4009 inverter will, when in the disabled state, block strobe 5 pulses received from the data source. The input timing of the data and strobe pulses may be seen from FIG. 3 and it is to be noted that the strobe pulses are always delayed in the interest of allowing data to settle past read only memory 30. This delay in the strobe pulses permits, in the manner described above, the address output line of memory 30 to block its own strobe pulses.

The enter message register 34 may comprise an RCA type CD4OI3AE flip-flop circuit. When register 34 is set to enter" it will provide an output signal which is applied to the enter/recirculate (ENTER/RECIR) input of shift register network 32. This output from register 34 is also applied as a second input to AND gate 42 and as an input to OR gate 44. The enter signal provided at the Q output of register 34 will be passed by gate 44 to the blank" inputs of a pair of binary-

tooctal decoders

46 and 48. The application of the enter signal to

decoders

46 and 48 will result in the display tube being blanked. The OR gate 44 may be comprised of an RCA type CD4001AE OR gate combined with an RCA type CD4009AE inverter. The

decoders

46 and 48 may be RCA type CD4028AE's. The application of the enter signal, generated by the setting of register 34, to shift register network 32 will stop the recirculation of data in network 32 and ready the shift register network to accept new data from read only memory 30. As noted, the setting of enter message register 34 also provides an enabling signal at a second inputof AND gate 42 whereby the gate will accept strobe pulses when the address output line of read only memory 30 goes false; i.e., when the system is in the data enter mode.

With the system cleared in the manner described above, the address input code is removed from the inputs to read only memory 30 thereby enabling, in the manner described above, AND gate 42. An end-ofmessage (EOM) code is now presented to inputsA -A of memory 30. The read only memory 30 will always provide a true EOM output line when the specific EOM input code is applied, regardless of the status of input lines A through A and a false output at all other times. The positive leading edge of the signal applied at the EOM output line of memory 30 in response to receipt of the EOM code sets the end-of-message register 38/. Register 38 was, in the manner described above, previously reset via OR gate 36 when the address output line of memory 30 went true. The setting of register 38, which may be an RCA type CD40l3AE flip-flop, results in the application of an input signal tothe D input of shift register network 32 via OR gate 50. This input to shift register network 32 is a simulated space. The OR

gates

36 and 50 may be identical to OR gate 44.

The setting of end-of-message register 38 will also apply an enabling signal to AND gate 52; gate 52 in a preferred embodiment being comprised of an RCA type CD40llAE NAND gate and an RCA type CD4009AE inverter. The enabling of gate 52 will permit pulsesprovided by a continuously running clock 54 to be applied to a binary word counter 56 via OR gate 58 and AND gate 42. Clock 54, which provides timing pulses for recirculating information in shift register network 32, may be an RCA type CD4009AE oscillator and associated timing network. Gate 58 may be identical to previously discussed OR gate 44.

The pulses provided by clock 54 are also applied, via

gates

52, 58 and 42, to the enter clock input of the shift register network 32; positive leading edges of clock pulses resulting in the entry of data appearing at the shift register network input terminals. Thus, with the end-of-message code applied to the input of memory 30, the simulated space at input D of shift register network 32 will be entered into the shift register on the positive edge of each clock pulse. After data has been entered on the positive edge of each clock pulse, the negative or trailing edge of each clock pulse will increment the word counter 56 which may be an RCA type CD4024AE counter. The clock pulses continue to enter spaces into the shift register memory 32 and increment the binary word counter 56 until counter 56 reaches a preset count which is detected by an AND gate 60. The AND gate 60, which may be comprised of an RCA type CD4012AE NAND gate and an RCA CD4009AE inverter, decodes the full" condition of shift register network 32. When gate 60 detects the preset count in counter 56 commensurate with the full condition an output signal will be provided which, via OR gate 36, resets the end-of-message register 38 thereby removing the enabling signal from gate 52 and preventing additional pulses from clock 54 from being applied to the enter clock (ENTER/CK) input to shift register network 32. The output of gate commensurate with counter 56 reaching the preselected count is also employed as the reset input to the enter message register 34; the resetting of register 34 removing the enabling signal from gate 42. Accordingly, all strobe and clock pulses will now be blocked at gate 42.

The AND gate 60, through a delay circuit 62, will also reset the word counter 56 to zero after it has counted to the preselected count. Delay circuit 62 may be comprised of two RCA type CD4001AE NOR gates and timing network and will function as a monostable multivibrator. Upon being reset, the enter message register 34, in addition to disabling any strobe pulses at gate 42, will set the shift register memory 32 into a recirculating mode in which no new information may be entered and all data entered while register 34 was in the enter state is time shared at the output of shift register network 32. In the example being described, since all spaces have been entered, the shift register network 32 space output line D remains continually true" and, via OR gate 44 and

decoders

46 and 48, causes the display to be blanked. Accordingly, in the manner described above, the presentation of an end-of-message (EOM) code at the input to read only memory 30 will clear the display by entering all spaces thereby readying the display system for a data entry.

To enter a message, after the system has been cleared by the above explained procedure of first entering an address code and then an end-of-message code, the address code is once again entered. It is to be noted that the system, once in a recirculating mode as will result from the resetting of register 34 pursuant to an EOM code having been applied at the input of memory 30, will not respond to anything but an address code. The address code will set the cleared system into the enter mode, in the manner described above, and when the address code is removed from the input AND gate 42 will enable the strobe input. The first character to be entered in the message sequence is then presented to the input of read only memory 30. Input data will be applied to the system in parallel fashion and will typically be coded in accordance with the conventional ASCll code; the input information, for example, being initially generated at a standard keyboard. The read only memory 30 will convert the input code to an intermediate dual binary code. The output of word counter 56 for the first message character will be A 0 false, A, false and A =false. The read only memory 30 is programmed to take the input character on input lines A;, through A,,, modify the input by the code appearing on input lines A through A and give the character a dual binary coded output B, through E, which is related to the display tube X, Y address assigned to that input character in that message word position. Thus, the three lower bits 3,, B and B of the output of read only memory 30 are the binary code for the X mask address, and the three higher bits, B B and B are the binary code for the Y mask address. This code, B, through 8,, is presented to the shift register 32 inputs and the positive leading edge of the strobe pulse, acting through

gates

58 and 42, enters the data into shift register 32. The negative or trailing edge of each strobe pulse increments word counter 56 by one.

The second character is now presented to the read only memory 30 input and, in combination with the A A and A inputs (1, 0, respectively), produces an output which is the dual binary code of the mask associated with the character in the second message position. The second character is entered in shift register 32in the manner described above and word counter 56 is incremented one additional count.

If the space code is presented to the input of read only memory 30, the read only memory space output line will go true and, via OR gate 50, will store a true in the space portion of the shift register at that word position in the message. This process of entering information into the shift register network 32 continues until a sufficient number of characters have been entered to bring the word counter to the predetermined count which is detected by AND gate 60. When this count is reached, in the manner described above, gate 60 will cause the enter message register 34 to be reset and will return the shift register 32 to the recirculate mode thereby enabling the display. The resetting of register 34 and enabling of the display may also be accomplished by the use of an end-of-message code which will enter spaces in the remaining message word positions as explained previously.

In the recirculating mode the shift register network 32 time shares the dual binary codes in a sequential manner at the output terminals of the shift register and presents the codes to the two binary-to-

octal decoders

46 and 48. Each of the

decoders

46 and 48 provides eight output lines. These 16 lines of time sequenced data are shifted from the logic voltage levels to levels compatible with the display tube by the two

level shifter arrays

64 and 65. The level shifters may, for example, comprise eight National Semiconductors type LM301AN comparators. The 16 lines of data from the

level shifter arrays

64 and 65 are then applied, via resistor current limiting

networks

66 and 68, to the control grids of the 64 cathode display tube. The masks chosen by the input codes are time sequenced on the face of the tube and, as a consequence of the retention capabilities of the phosphor coating of the tube and the speed of recirculation as determined by the output of clock 54, the entire message will be visible on the tube.

While a preferred embodiment has been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustration and not limitation.

What is claimed is:

1. A display system comprising:

a cathode ray display tube, said tube having a plurality of cathodes each preaimed at a shadow mask associated with each cathode, each mask defining indicia which is enlarged by the tube electron optics to cover the entire display screen when its associated cathode is energized;

means for sequentially receiving and storing information commensurate with portions of a desired display; and

means for sequentially addressing the individual cathodes of the display tube in accordance with said stored information whereby indicia commensurate with the portions of the display are sequentially projected on the cathode ray tube display 2. The apparatus of claim I wherein the received information is in the form of electrical signals and wherein said receiving and storing means comprises:

recirculating memory means having a plurality of output terminals;

means controlling the entry of sequentially received information bearing signals in said memory means; and

clock means for causing information stored in said memory means to be circulated therein and sequentially applied to the output terminals thereof.

3. The apparatus of claim 2 wherein the means controlling the entry of signals into said memory means comprises:

coding means for modifying the received information bearing signals in accordance with a display tube cathode location corresponding to a particular display portion received in that sequential position.

4. The apparatus of claim 3 wherein said coding means comprises:

a read only memory, said memory being programmed to convert the received signal into a dual binary code in accordance with the order in which the display portion information is received; and

counter means responsive to the entry of display portion information in said recirculating memory for generating a coding input for said read only memory.

5. The apparatus of claim 2 wherein said means for sequentially addressing the display tube cathodes comprises:

decoder means connected to said recirculating memory means output terminals, said decoder means being responsive to sequentially presented stored display portion information for. generating signals commensurate with the X and Y display tube cathode addresses; and

means coupling the output signals generated by said decoder means to said display tube cathodes.

6. The apparatus of claim 5 wherein said coupling means each include:

voltage level shifting means.

7. The apparatus of claim 5 wherein said decoder means comprises:

a pair of binary-to-octal decoders.

8. The apparatus of claim 4 wherein said means for sequentially addressing the display tube cathodes comprises:

decoder means connected to said recirculating memory means output terminals, said decoder means being responsive to sequentially presented stored display portion information for generating signals commensurate with the X and Y display tube cathode addresses; and

9. The apparatus of claim 8 wherein said decoder means comprises:

a pair of binary-to-octal decoders.

10. A message display method comprising the steps of:

storing serially received message portions;

time-sharing the stored message portions at the output of the storage medium; and

applying the time'shared message portions to individual cathodes of a multiple cathode shaped beam cathode ray display tube with each cathode preaimed at a predetermined section of a shadow mask associated with each cathode, the shaped beam formed by the shadow mask acting on the electron beam then continues, to fill the entire face of the tube at a complete message repetition rate in excess of the retention time of the tube. 11. The method of claim 10 wherein the step of storing includes:

encoding the message portions in accordance with the sequential time received in a message and with the grid location of cathodes associated with a recirculating data in the memory device.

Claims

1. A display system comprising: a cathode ray display tube, said tube having a plurality of cathodes each preaimed at a shadow mask associated with each cathode, each mask defining indicia which is enlarged by the tube electron optics to cover the entire display screen when its associated cathode is energized; means for sequentially receiving and storing information commensurate with portions of a desired display; and means for sequentially addressing the individual cathodes of the display tube in accordance with said stored information whereby indicia commensurate with the portions of the display are sequentially projected on the cathode ray tube display screen and the entire display will be visible due to the retention characteristics of the cathode ray tube screen.

2. The apparatus of claim 1 wherein the received information is in the form of electrical signals and wherein said receiving and storing means comprises: recirculating memory means having a plurality of output terminals; means controlling the entry of sequentially received information bearing signals in said memory means; and clock means for causing information stored in said memory means to be circulated therein and sequentially applied to the output terminals thereof.

3. The apparatus of claim 2 wherein the means controlling the entry of signals into said memory means comprises: coding means for modifying the received information bearing signals in accordance with a display tube cathode location corresponding to a particular display portion received in that sequential position.

4. The apparatus of claim 3 wherein said coding means comprises: a read only memory, said memory being programmed to convert the received signal into a dual binary code in accordance with the order in which the display portion information is received; and counter means responsive to the entry of display portion information in said recirculating memory for generating a coding input for said read only memory.

5. The apparatus of claim 2 wherein said means for sequentially addressing the display tube cathodes comprises: decoder means connected to said recirculating memory means output terminals, said decoder means being responsive to sequentially presented stored display portion information for generating signals commensurate with the X and Y display tube cathode addresses; and means coupling the output signals generated by said decoder means to said display tube cathodes.

6. The apparatus of claim 5 wherein said coupling means each include: voltage level shifting means.

7. The apparatus of claim 5 wherein said decoder means comprises: a pair of binary-to-octal decoders.

8. The apparatus of claim 4 wherein said means for sequentially addressing the display tube cathodes comprises: decoder means connected to said recirculating memory means output terminals, said decoder means being responsive to sequentially presented stored display portion information for generating signals commensurate with the X and Y display tube cathode addresses; and means coupling the output signals generated by said decoder means to said display tube cathodes.

9. The apparatus of claim 8 wherein said decoder means comprises: a pair of binary-to-octal decoders.

10. A message display method comprising the steps of: storing serially received message portions; time-sharing the stored message portions at the output of the storage medium; and applying the time-shared message portions to individual cathodes of a multiple cathode shaped beam cathode ray display tube with each cathode preaimed at a predetermined section of a shadow mask associated with each cathode, the shaped beam formed by the shadow mask acting on the electron beam then continues, to fill the entire face of the tube at a complete message repetition rate in excess of the retention time of tHe tube.

11. The method of claim 10 wherein the step of storing includes: encoding the message portions in accordance with the sequential time received in a message and with the grid location of cathodes associated with a mask commensurate with the message portion data.

12. The method of claim 11 wherein the step of storing further includes: reading the encoded message portions into a memory device.

13. The method of claim 12 wherein the step of time-sharing includes: recirculating data in the memory device.