US3851107A - Fault detecting device for multiplex signal transmission system - Google Patents

Fault detecting device for multiplex signal transmission system Download PDF

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Publication number
US3851107A
US3851107A US00403611A US40361173A US3851107A US 3851107 A US3851107 A US 3851107A US 00403611 A US00403611 A US 00403611A US 40361173 A US40361173 A US 40361173A US 3851107 A US3851107 A US 3851107A
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signal
circuit
block
fault detecting
fault
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US00403611A
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English (en)
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S Akita
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Soken Inc
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Nippon Soken Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • FIG. I3 I i souRcE TRANSMITTER I I EIV R I I RECEIVER n 4 v u 1 I24 R in? i4 (40o (430 R 42! WM 3 C D;O LOAD i 4 I L n I FIG. I582 v v v FIG. I502;
  • the present invention relates to a fault detecting de vice for a multiplex signal transmission system comprising a transmitter and a receiver and employing a multiplex communication method based on time-sharing.
  • a remarkable advantage of the device of the present invention is the use of a fault detecting circuit in a multiplex signal transmission system comprising a transmitter and a receiver and employing a multiplex communication method based on time-sharing with the result that when a fault occurs in the level signal line for send? ing load actuating command signals, the fault is detected to prevent the actuation of all the loads due to the fault.
  • FIG. 1 is a block diagram showing an embodiment of 0 generating circuit shown in FIG. 3.
  • FIGS. 6A and 6B are input and output characteristic diagrams of the reset pulse generating circuit shown in FIG. 5.
  • FIG. 7 is an electric circuit diagram showing in detail the internal circuit of the first counting block shown in FIG. 3.
  • FIG. 8 is a block diagram showing a part of the combining block shown in FIG. 1.
  • FIG. 9 is an electric circuit diagram of the whole combining block shown in FIG. 1.
  • FIG. 10 is a block diagram of the second counting block shown in FIG. 1.
  • FIG. 11 is an electric circuit diagram showing a part of the restoring block shown in FIG. 1.
  • FIG. 12 is an electric circuit diagram of the whole restoring block shown in FIG. 1.
  • FIG. 13 is a block diagram of the multiplex signal transmission system incorporating two receivers.
  • FIG. 14 is an electric circuit diagram showing-an embodiment of the fault detecting. circuit used in the device of this invention..
  • FIGS. 15A to 15C are waveform diagrams useful for explaining the operation of the fault detecting circuit shown in FIG. 14.
  • FIG. 16 is an electric circuit diagram showing another embodiment of the faultdetecting circuit in the device of this invention.
  • FIGS. 17A to 171 are waveform diagrams useful for explaining the operation of the fault detecting circuit shown in FIG. 16.
  • FIGS. 1 to 13 An embodiment of a time-sharing multiplex signal transmission system incorporating the device according to the present invention will be described first with reference to FIGS. 1 to 13.
  • FIG. 1 which shows a block diagram of the overall device according to the invention
  • a transmitter I is constituted of a first counting block 2, a combining block 3 and an oscillator 110, while a receiver 4 consists of a second counting block 5 and a restoring block 6, and a power source 7 may be, for example, an accumulator.
  • the general description of the time-sharing multiplex signal transmission system incorporating the device according to the present invention shown in FIG. 1, will now be described by reference to the waveforms shown in FIGS. 2A to 21.
  • the time base indicated at 101 in FIG. 2D is divided into equal periods, each comprising smaller intervals 00, 01, 02, 99, and signals to be transmitted to the receiving end are allotted to the intervals.
  • the receiver discriminates whether the intervals contain the corresponding signals or not and picks up the predetermined ones of the signals only when they are contained in the respective intervals.
  • This time-sharing process is performed on the basis of a synchronous signal indicated at 123 in FIG. 2B and delivered from the first counting block 2 and a timing signal 122 indicated at 122 in FIG. 2A, through the provision of the scale-of-IO counters in the counting blocks 2 and 5 respectively of the transmitter l and the receiver 4.
  • These scale-0H0 counters generate an address signal corresponding to the thus defined intervals, i.e. time-shared intervals.
  • the signals to be transmitted are combined together through the combining block 3 to produce a level signal indicated at 124 in FIG. 2C, which is transmitted from the combining block 3.
  • the signal transmission between the transmitter 1 and the receiver 4 is through three lines, i.e. line L, for the synchronous signal 123, line L for the timing signal 122 and line L for the level signal 124, while two additional lines L and L are provided therebetween for the purpose of power feeding.
  • the synchronous signal 123 in which a. period corresponding in time to the time-shared interval 00 has a lower level, is transmitted from the counting block 2 to the counting block 5.
  • a reset signal 151 shown in FIG. 2H is obtained from a signal indicated at 161 in FIG. 26 in which a period corresponding to the time-shared interval 00 has a higher level.
  • the reset signal 151 resets frequency dividers and the scale-of-IO counters in the counting blocks 2 and 5.
  • the level signal 124 to be transmitted from the transmitter I to the receiver 4 is obtained by passing, i.e. taking a logical product of, three signals; a predetennined input signal to be transmitted, an address signal from the scale-of-ll counter containing addresses indicative of the numeral-pairs (such as 02 or 04) of the time-shared-intervals into which theinput signal is allotted, and a strobe signal indicated at 181 in FIG. 2E; through an AND gate.
  • the level signal 124 shows a case where a signal to be transmitted is superposed on the addresses in the timeshared intervals indicated by the numeral-pairs 01 and 02. This level signal 124 is then restored through the restoring block 6 in the receiver 4 in the manner described below.
  • the initial state is established by applying the reset signal 151 shown in FIG. 2H to the reset input of a first memory circuit during the time-shared interval 00. Then, an output signal which is the logical product of the address signal appearing in the predetermined time-shared intervals and the level signal 124, is applied to the set input of the first memory circuit. Therefore, if an AND signal is applied to the set input the initial state of the memory circuit is cleared, while the initial state is maintained if there is no input to the memory circuit.
  • the state of the first memory circuit is determined depending upon whether there is a level signal in respective time-shared intervals or not.
  • the state is again cleared when the following timeshared interval 00 has been reached and it is necessary to transfer the content of the first memory to a second memory circuit before the former is cleared.
  • This transfer operation is performed during the time-shared interval 99 by applying a transfer signal 171 shown in FIG. 2F, which is the logical product or AND of the interval 99 and the strobe signal 181 in FIG. 2E, to a gate which controls the transmission of the signal between the first and second memories.
  • the content of .the first memory is continuously fed to and stored in the second memory during the duration of a signal 191 shown in FIG. 2I from the time-shared interval 99 in a period to the interval 99 in the next period.
  • the signal 124 a predetermined signal is in the interval 02, the transfer of the content takes place in a similar manner, but during the duration of a signal .192 shown in FIG. 2] with a delay of one period with respect to the signal 191. Therefore, if in the level signal 124 a predetermined signal appears in every interval 01, the signal 191 will last without interruption from the interval 99 shown in FIG. 21 onward.
  • FIG. 3 shows the constitutions of the oscillator 110 and the first counting block 2 in the transmitter 1.
  • the oscillator 110 may be constituted of a tuning fork and quartz or have resort to a capacitor-resistor compensated feedback method.
  • the n-th output 121 and (n-l )th output 122 (timing signal shown in FIG. 2A) of the n-th stage of a frequency divider circuit 120 are applied to a logic circuit 180, which takes the NAND of the outputs.
  • the output of the NAND circuit 180 is then fed to an inverting gate 182, which in turn delivers the strobe signal 181.
  • the strobe signal 181 is used to prevent the interference of the signals indicative of the time-shared intervals in transmission and reception.
  • the logic circuit 180 may be substitutedby an OR ELSE circuit which takes the exclusive logic sum of the signals 121 and 122.
  • Reference numerals 130 and 140 indicate scale-of-10 counters.
  • the scale-of-l0 counter must be a device which delivers at its output terminals 130-0 to 130-9 output signals having waveforms as shown in FIG. 4. This requirement can be satisfied by using the well known MOS IC CD4017D manufactured by RCA or by a combination of suitable gates.
  • FIG. 4A shows an output signal 121 frequency divided by the frequency divider circuit 120, FIG.
  • FIG. 4B shows a reset signal 151 which is an output of a reset pulse generating circuit 150 described below
  • FIGS. 41C to 4L show signals delivered respectively from the output terminals 130-0 to 130-9 of the scale-of-ll0 counter 130
  • FIG. 4M shows an output signal 131 from the counter 130.
  • the signal 131 from the counter 130 indicating the digit of the first place of the numeral-pair representing the time-shared interval, is applied to the scale-of-10 counter which delivers an output signal indicating the digit of the second place of the same numeral-pair.
  • the scale-of-ll0 counter 140 operates in the same manner as the counter 130.
  • the signals derived respectively from the output terminals 130-0 and 140-0 of the counters 130 and 140 are fed to an AND gate 160, the output of which is then applied to an inverting gate 162 to obtain a synchronous signal 123 at its output terminal.
  • the reset pulse generating circuit receives the output signal 161 of the AND gate as its input signal, and an embodiment of the circuit 150 is illustrated in FIG. 5.
  • the reset pulse generating circuit 150 comprises an AND gate 150a, inverting gates 150b to 150d, an input terminal 150e and an output terminal 150f.
  • the reset signal 151 as the output of the reset pulse generating circuit 150 is applied to the reset terminals of the frequency divider circuit 120 and the scale-of-10 counters 130, 140, respectively.
  • FIG. 7 shows a concrete embodiment of a circuit shown in a block diagram in FIG. 3. In FIG. 7, the descriptions of the already mentioned circuit elements are abridged.
  • the oscillator 110 has a well known constitution comprising inverting gates 1100, 110b and 110:, a resistor 110d and a capacitor 110e.
  • the frequency divider 120 comprises a flip-flop 120a and an inverting gate.
  • the scale-of-10 counter 130 is the above-mentioned, well-known MOS IC CD4217D by RCA, which comprises D flip-flops 130a to 130e, negative logic AND gates 130f to 130p, a NOR gate 130q and an inverting gate 130r.
  • the scale-of-10 counter 140 has the same constitution and operates in the same manner as the counter 130.
  • the logic circuit 180 is a NAND gate 180a.
  • An AND gate and an inverting gate 152 in the unit shown in FIG. 7 are useful only where the unit is used for the second counting block 5 in the receiver 4 but useless where the unit is used for the first counting block 2 in the transmitter 1.
  • These elements are incorporated together with other circuit elements in a single lC unit or package and, therefore, if the unit is used for the first counting block 2 of the transmitter 1, the AND gate 170 and the inverting gate 152 are left out of electrical connection.
  • FIG. 8 shows a part of the combining block 3 of the transmitter 1, having a constitution for one channel associated with one address.
  • the terminals 211 and 212 are connected respectively with the selected one of the terminals 130-0 to 130-9 of the scale-of-10 counter 130 and the selected one of the terminals 140-0 to 140-9 of the scale-of-ll counter 140 so as to obtain an address representative of a predetermined time-shared interval.
  • a terminal 220 is an input terminal which receives a signal transmitted from the transmitter 1 to the receiver 4 and an inverting gate 221 is provided to deliver the inversion of the input signal.
  • the NAND gate 240 takes the NAND of the signals applied to the terminals 211 and 212 and the signal delivered from the inverting gate 221. Namely, the gate 240 delivers a low-leveled, 0 signal only when there are applied to the gate 240 a predetermined address signal and an input signal corresponding to the address.
  • a NAND gate 260 takes the NAND of the output signal from the NAND gate 250 and the strobe signal 181 and delivers the level signal 124 to the line L
  • the 9 is adapted for receiving ten inputs, i.e. ten channels, corresponding to ten addresses.'I-Iowever, if, as described later, the receiver 4 has eight input terminals, only eight channels out of ten are used for signal transmission.
  • the selection of any address corresponding to each of the time-shared intervals 00 to 99 can be made by appropriately combining the outputs of the scale-of- 10 counters 130 and 140.
  • the number of channels for signal transmission in this embodiment is not limited to eight but may be increased up to 98, if need be, since there are ninety-eight time-shared intervals 01 to 98.
  • any one of the addresses corresponding to the time-shared intervals 00 to 99 can be arbitrarily selected by means of the counting block 2 and the combining block 3.
  • the receiver 4 comprises the restoring block 6 and the second counting block similar to the counting block 2 shown in FIG. 7 but with a somewhat different'connection.
  • FIG. 10 illustrates in detail the constitution of the counting block 5 for use in the receiver 4.
  • the frequency divider circuit 120' is actuated by the timing signal 122 which is received from the first counting block 2 in the transmitter 1 through the line L,;,.
  • the reset pulse generating circuit 150' receives the output of an inverting gate 152 (see FIG.
  • the circuit of the second counting block 5 in the receiver 4 is the same as that of the first counting block 2 in the transmitter 1 in FIG. 7, but the NAND gate 160 and the inverting gate 162 shown in FIG. 7 are unnecessary for the operation of the second counting block 5 and they are omitted in the circuit shown in FIG. 10.
  • the frequency divider circuit the scale-of-l0 counters and the reset pulse generating circuit and the logic circuit of the second counting block 5 in the receiver 4 have the same constitutions and operate in the same manner as those of the first counting block 2 in the transmitter 1 in FIG. 7.
  • FIG. 11 shows the electrical connection of one of the constituents, i.e. equivalent components, of the restoring block 6.
  • NAND gates 310 and 320 form a setreset type flip-flop serving as a first memory circuit.
  • NAND gates 360 and 370 also form a set-reset type flip-flop serving as a second memory circuit.
  • Numeral 400 designates a fault detecting circuit. This unit receives the strobe signal 181 and the transfer signal 171 from the second counting block 5 shown in FIG. 10 and has terminals 211' and 212"which are adapted to receive an address signal representing a time-shared interval.
  • an address signal indicative of the time-shared interval 13 is introduced to the unit.
  • These connections are represented for simplicitys sake by a dashed line between the second counting block 5 and the restoring block 6 in FIG. 1.
  • the operation of the unit is as follows. The first memory circuit assumes its initial state upon reception of the reset signal 151 from the second counting block 5 to maintain the output terminal 311 at a higher level and the output terminal 321 at a lower level and this state continues after the reset signal 151 has ceased.
  • the terminal 331 is maintained at the higher level. If the strobe signal 181 assumes the higher level in response to the interval 13, the NAND gate 330 is enabled to maintain its output terminal 332 at the lower level. Accordingly, the state of the first memory circuit is changed so that the output terminals 321 and 311 are maintained respectively at the higher and lower level. And this state is maintained even after the time-shared interval 13 has passed away, since both the signal at the output terminal 332 and the reset signal 151 assume the higher level.
  • the levels at the terminals 321 and 311 are transferred respectively to the NAND gates 370 and 360 forming the second memory circuit through the NAND gates 340 and 350 opened by the transfer signal 171 generated during the time-shared interval 99. Namely, the very signal appearing at the terminal 311 when the transfer signal 171 is on the point of being generated, appears at the output terminal 361. This is true also for the terminals 321 and 371. The state of the second memory circuit is maintained until the next pulse of the transfer signal 171 has arrived.
  • FIG. 12 illustrates an exemplary circuit diagram of the restoring block 6 comprising eight equivalent units, one of which is illustrated in FIG. 10.
  • the fault detecting circuit 400 is not shown.
  • the reset signal 151, the level signal 124, the strobe signal 181 and the transfer signal 171 are applied respectively with the input busses common to the eight units.
  • FIG. 13 shows a case where two receivers are connected with one transmitter. This is usual, for example, with the application to an automobile in which it is required to controllably energize the front search light and the tail lamps by a manual switch actuated by the driver. In such a case, the transmitter is placed within the drivers reach and the two receivers are placed within the engine room and the trunk room and the wired OR method using DTL may be resorted to.
  • the fault detecting circuit 400 used in the abovedescribed multiplex signal transmission system to forci bly prevent the actuation of the loads under fault conditions resulting from the grounding of the level signal line, that is, under abnormal conditions where the loads tend to be actuated irrespective of the presence or absence of commands, will now be described with reference to FIG. 14.
  • the fault detecting circuit shown in FIG. 14 is adapted for incorporation in the previously described restoring block 6 and it receives the transmitted level signal 124 as well as the actuation command signal restored in the restoring block 6 and applied to the terminal 361 shown in FIG. 11.
  • the letter R designates a resistor, C a capacitor, 4111 an inverting gate, 420 a NOR gate, 430 a load.
  • the waveform shown in FIG. 15B is generated at a terminal RC by the integrator circuit comprising the capacitor C and the resistor R and the waveform shown in FIG. 15C appears at an output terminal 421 of the inverting gate 410.
  • the l level signal appears upon the occurrence of the fault at the point a.
  • the signal at the output terminal 421 of the inverting gate 410 changes to 0 and therefore the inverted signal of the applied signal at the terminal 36! appears at the output of the NOR gate 420. This signal determines whether the load 430 should be actuated or not.
  • FIG. 16 illustrates another embodiment of the fault detecting circuit in the device of this invention which includes memory circuits.
  • the fault detecting circuit of FIG. 16 receives, for example, the multiplex communication level signal 124 as well as the reset signal 151 and the transfer signal 171 generated by the circuit shown in FIG. 10 and it also receives as in the embodi ment of FIG. 3 the load actuating command signal applied to the terminal 361.
  • a multiplex signal transmission system comprising a transmitter for generating a synchronous signal, a timing signal and a level signal having information to be transmitted superposed on the designated addresses, and a receiver including signal generating means for receiving said signals to generate a reset signal and a transfer signal, and restoring means for receiving said reset signal, said transfer signal and said level signal to generate an actuation signal, a fault detecting circuit comprising detecting means for generating a signal by detecting the fact that said level signal has superposed information on all the addresses, and means connected to said restoring means to block said actuation signal upon the generation of said detected signal.
  • a fault detecting circuit comprises a first flip-flop circuit having a first terminal for receiving said level signal and a second terminal for receiving said reset signal, two logic circuits each thereof having a first input terminal connected to said first flip-flop circuit and a second input terminal for receiving said transfer signal, and a second flip-flop circuit connected to said logic circuits.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
US00403611A 1972-10-05 1973-10-04 Fault detecting device for multiplex signal transmission system Expired - Lifetime US3851107A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2286098A (en) * 1994-01-31 1995-08-02 Daimler Benz Ag Digital information transmission with fault protection

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5167013A (ja) * 1974-12-09 1976-06-10 Nissan Motor Ijokenshutsusochiosonaetashingodensosochi

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2779869A (en) * 1953-07-20 1957-01-29 Collins Radio Co Amplitude distribution analyzer
US3696210A (en) * 1970-08-06 1972-10-03 Motorola Inc Data transferring system utilizing a monitor channel and logic circuitry to assure secure data communication
US3717863A (en) * 1970-10-22 1973-02-20 Philips Corp Switch position supervising device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2779869A (en) * 1953-07-20 1957-01-29 Collins Radio Co Amplitude distribution analyzer
US3696210A (en) * 1970-08-06 1972-10-03 Motorola Inc Data transferring system utilizing a monitor channel and logic circuitry to assure secure data communication
US3717863A (en) * 1970-10-22 1973-02-20 Philips Corp Switch position supervising device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2286098A (en) * 1994-01-31 1995-08-02 Daimler Benz Ag Digital information transmission with fault protection
GB2286098B (en) * 1994-01-31 1998-04-15 Daimler Benz Ag Digital information transmission apparatus for a vehicle control system

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