US3832601A

US3832601A - Phase comparison relaying apparatus with two-count by-pass circuit

Info

Publication number: US3832601A
Application number: US00387070A
Authority: US
Inventors: W Hinman; R Gonnam
Original assignee: Westinghouse Electric Corp
Current assignee: ABB Inc USA
Priority date: 1973-08-09
Filing date: 1973-08-09
Publication date: 1974-08-27
Anticipated expiration: 1991-08-27
Also published as: ES197868U; CA1022666A; ES197868Y; GB1452616A; JPS562723U; DE2356959A1; JPS5045253A

Abstract

A phase comparison unblocking relaying network which includes means to trip the circuit breaker upon the occurrence of a plural number of phase comparisons when the phase comparing information between the local and remote relaying stations has a lesser time overlap than the normal time for which the security timer is set and which will, in the event of a time overlap of a predetermined interval greater than said normal time interval, trip the breaker without waiting for more than one phase comparison.

Description

United States Patent 1191 Hinman, Jr. et a1.

1111 3,832,601 1451 Aug. 27, 1974 [541 PHASE COMPARISON RELAYING 3,470,418 9/1969 Hagberg et a1 317/27 R APPARATUS WITH T CO BY PASS 3,590,324 6/1971 Rockefeller 317/27 R CIRCUIT 3,612,952 10/1971 Hagberg 317/27 R 3,710,189 l/l973 Hagberg 317/27 R [75] Inventors: Walter L. Hinman, Jr., New

' PTOViFIeIICQ; m" Gonllam, Primary Examiner-J. D. Miller Moms P131115, bOth of Assistant Examiner-Patrick R. Salce [73] Assignee: Westinghouse Electric Corporation, Attorney Agent or Stoughton Pittsburgh, Pa.

22 Filed; Aug. 9, 1973 [57] ABSIRACT V A phase companson unblocklng relaying network 1 1 pp N03 337,070 which includes means to trip the circuit breaker upon the occurrence of a plural number of phase compari- 52 us. 01. 317/27 R, 317/28 R, 317/29 A Sons when the Phase comparing information between [51] Int. Cl. H02h 3/28 the local and remote relaying stations has 3135561 time 5 Field of Search. 317/27 A 2 R, 27 R 2 B overlap than the normal time for which the security 317/2911, 29 A 29 B timer is set and which will, in the event of a time over- 1 lap of a predetermined interval greater than said nor- 56] References Cited mal time interval, trip the breaker without waiting for UNITED STATES PATENTS more than one phase comparison. 3,295,019 12/1966 Altfather 317/27 R 7 C 3 Drawing Figures LJ i i L:

W TRIPPING NETWORK g3 OVERCURRENT 95 Si 552 908 m h r 58A 3/ 0 9O 2 COUNT 216 am? Tl E 62x OVERCURRENT o i 548 DELAY 90A 32 63 TIME DELAY A FAULT I 54 145 1491 DETECTOR AND ii To CHANNEL 54A FAILURE 174 1 2'3 182 uua ocx 7 FREQUENCY 87 A 72 il gi EE EE 2 2 13s KE'YER 135 BA 512211190, g-5 coil 1%? 120111 asA 31753? swp DETERhgINATOR OR l l l as 3:55 2 F035 1 DELAY 103 GUARD SQUARER :3 TIMER AND LOW SIGNAL: U R

15s 51 Lt ISQVND 82B 126 111 3.8. swu J sw- 92 ru'u PATENIEDAUBZHBM 'SIIEIIG' 2 xmoawmz 5:00-05 9N m @E 8 93 $2? 024 ll 9N Na is;

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m& m 56 Y PHASE COMPARISON RELAYING APPARATUS WITH TWO-COUNT BY-PASS CIRCUIT CROSS REFERENCE TO RELATED APPLICATIONS This invention relates to phase comparing relay networks generally and is illustrated as being embodied in the phase comparing network shown and described in a copending US. Pat. Application Ser. No. 295,031, filed Oct. 4, 1972 in the name of William Strickland and Walter L. I-Iinman Jr. and assigned to the same assignee as is this application.

BRIEF SUMMARY OF THE INVENTION that when this type of fault occurs a single half cycle thereof will cause energization of the breaker tripping circuit.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS FIG. 1 is a schematic drawing of a phase comparison unblocking relaying apparatus associated with a threephase power transmission line and embodying the invention;

FIG. 2 is a more detailed schematic drawing showing of the relaying apparatus which is associated with each of the three-phase conductors; and,

FIG. 3 is a logic diagram of a two-count network which may be used in the practice of this invention.

DETAILED DESCRIPTION FIGS. 1 and 2 are substantially identical to FIGS. 1 and 2 of the said copending application and the reference characters used herein are the same as far as possible as those used in the said copending application. In view of the more complete showing and description of the phase comparison relaying apparatus in the said copending application only a brief description of the operation thereof will be set forth herein. With the exception of the details shown intermediate the 4/0 time delay 90 and the input terminal 92 the detailed circuitry appearing in the illustrated blocks is substantially as shown in detail in said copending application.

FIG. 1 illustrates the relaying apparatus associated with one of the terminals of the three phase power transmission line being protected and which for convenience will be referred to as the local terminal; it being understood that a similar apparatus is associated with the other or remote terminal of the line being protected. The

reference characters

1, 2 and 3 indicate respectively the three-phase buses at the local station which are supplied with power from one or more suitable sources (not illustrated) and which are respectively connected to the transmission line phase conduc tors 4, 5 and 6 through low-

pass filters

7, 8 and 9 and breakers 10, 11 and 12 respectively. The current flow between the buses l, 2 and 3 and the phase conductors 4, 5 and 6 is monitored by the

current transformers

13, 14 and 15 which are connected to energize isolating transformers 16, l7, l8 and 19 connected in a suitable array such that the transformers 16, 17 and 18 monitor the current flow through the buses 4, 5 and 6 respec tively and the transformer 19 is energized with a residual quantity which represents the ground current. The phase current

responsive relaying networks

20, 21 and 22 and the residual or ground network 23 are energized from the output of the transformers 16, 17, 18 and 19 respectively. Resistors are connected across the secondary windings of the transformers 16, 17, 18 and 19 so that the quantities supplied to the

networks

20, 21, 22 and 23 are voltage quantities, the magnitude of which is determined by the magnitude of the current supplied to the transformer l6, 17, 18 and 19. The

networks

20, 21, 22 and 23 are provided with output conductors 25,

. 26, 27 and 28 which, when a fault occurs, supply out- I put quantities to the tripping network 24.

The tripping network 24 comprises an OR network 34 to which each of the

output conductors

25, 26, 27 and 28 are connected. The output of the OR network 34 is connected to a first input terminal of an OR network 36. Therefore whenever any one or more of these 'conductors25, 26, 27 and 28 are energized with a logical 1 signal, the OR network 36 will be provided with a tripping signal and since its output is connected by means of

conductors

31, 32 and 33 to the breakers 10, 11 and 12, the breakers will be tripped. The

output conductors

25,26 and 27 are also connected to the three input terminals of an AND network 40 for threephase fault detection. The output terminal of the AND network 40 is connected to one input terminal of an OR network 38. The output of this OR network 38 is connected to a second input of the OR network 36 to permit the tripping of the breakers 10, 11 and 12 in response to a logical 1 output signal from the AND network 40. The ground or residual current network 23 is provided with a second output conductor 29 which is connected through a timer 42 to a second input terminal of the OR network 38. The conductor 29 is provided with a logical 1 output signal whenever the magnitude of the ground current is above a predetermined minimum irrespective of its relationship to the ground or residual current at the remote end of the protected line section.

FIG. 2 shows in a greater detail a network 52 which may be used for any of the networks 20-23. The isolating transformer 61 (which corresponds to anyone of the transformers 16-19) has a loading resistor connected across its secondary winding so that the buses 62 and 63 will be energized with a voltage quantity which is proportional to the current'flow through the primary of the winding 61. During normal operation with no-fault current flowing through the transformer 61 the fault detector 58 energized thereby will have a logical 0 output and the time delay 58A will also have a logical 0 output.

When the switch SW1 is in the position illustrated in FIG. 2, the network 52 is conditioned for use as a phase conductor determining network. When the switch SW1 is in its other position, the network is conditioned for use as a ground or residual fault determining network. The logical 0 output of the time delay 58A is supplied to one input terminal 54A of an AND network and also to the output terminal 54B which is connected to the input terminal 98 of the keyer 72A and to the input terminal of the channel failure unblock network A frequency verifier 65 is energized from the buses 62 and 63 and its output is connected to a frequency verifier block 192. The output terminal 210 of the block 192 is connected by the conductor 211 to the input terminal 212 of the phase determinator 56 and therefrom to the NOT input tenninal 213 of the AND network 110. Normally the frequency verifier block 192 will supply a logical signal.

A breaker open detector 66 is energized from the buses 62 and 63 and with the corresponding one of breakers 10, 11 or 12 closed, will supply a logical 1 output signal through the bus 173 to the

input terminals

149 and 174 of the channel failure unblock 140 and the keyer 72A respectively. This logical 1 signal permits the networks to which they are applied to operate normally. If for some reason or other the associated breaker has been opened, a logical 0 signal will be supplied to the conductor 173 which will cause the keyer 72 to terminate any further transmission of the guard signal to the remote station and to transmit continuously a trip negative signal.

An I overcurrent network 60 is also energized from the buses 62 and 63 so that whenever the current flow through the corresponding phase conductor is above the charging current value of this conductor a logical 1 output signal will be supplied by the I overcurrent network 60 to the input terminal 95 of the trip board 94, to the terminal 153 of the channel failure unblock 140 to the terminal 182 of the phase comparison determinator 56. In the absence of the logical output signal from the network 60 the associated one of the breakers 10, 11 and 12 cannot be tripped by its associated one of the

networks

20, 21 and 22. Since no residual or ground current should flow unless there is a ground fault, the I overcurrent network 60 is connected by the switch SW1 to the input terminal 54 and the network 60 is utilized as the ground fault detector. In the event of an extremely high fault current, it is desirable to trip the associated breaker as rapidly as possible and for that purpose an I overcurrent network 64 energized from the buses 62 and 63 is provided. Whenever the phase conductor current is below a predetermined maximum value, the overcurrent network 64 supplies a logical 0 signal to the input terminal 99 of the trip board without effect. However should the fault current exceed this predetermined maximum value, a logical 1 signal will be applied to the conductor 99 which results in an immediate logical 1 output signal to the tripping network 24 so that the tripping network 24 will immediately trip the breakers 10, 11 and 12.

A squarer network 67 has its

input terminals

154 and 155 energized from the buses 62 and 63 and normally provides a pulsating output signal at its

output conductors

68, 69 and 70. The pulsations Iswp on the output conductor 68 represent the length of the positive half cycles of the voltage signal on the conductors 62 and 63 and are in predetermined phase relation therewith. Similarly the pulsating signal I on the output conductor 69 represents the negative half cycles of the input wave to the squarer 67. The output conductor 70 is supplied with a signal 1 substantially the same as that supplied to the output conductor 68 but more nearly represents the true length of the positive half cycle. This conductor 70 is connected to the input terminal 71 of the keyer 72 and through circuitry to be described hereinafter which will, in the event of a fault, cause the transmitter frequency control 76 to actuate the transmitter receiver 78 so that it will operate to terminate the transmission of the guard signal and to transmit an output signal to provide trip positive and trip negative signals over the one of the

conductors

44, 45, 46 and 47 which such transmitter is associated whereby the phase of the current at one station is supplied over the connecting channel (in this case by means of power line carrier frequency) to the corresponding apparatus at the other station of the protected line section. The receiver of the transmitter receiver at the remote station is responsive to the signal transmitted by the transmitter portion of transmitter receiver 78 at the local end and similarly the receiver of the transmitter receiver at the local end responds to the signal supplied by the transmitter receiver at the remote end.

The transmitter receiver 78 is provided with an output conductor 81 which is connected to the input terminal-82 of the phase comparison determinator and therethrough to the non-inverted and inverted terminals of the AND networks 82A and 823 respectively and supplies'the signal Rl thereto. The Iswp and signals are supplied to the delay timer 84 which delays themby substantially the time delay afforded by the communication channel between the local and remote line terminals so that the output quantities 1 and ISWND which are applied to the

input terminals

85 and 86 of the phase comparison determinator 56 for energization of the second non-inverted input terminals of the AND

networks

82A and 82B in proper phase relationship with respect to the signal RI supplied by the transmitter receiver 78. If the fault is within the protected line, the logical 1 portions of the signals Rl and Iswpb will be substantially in phase and an output signal will be supplied from the AND network 82A to one input of the OR network 86A. During the period that the quantity RI has a logical 0 output, it will be substantially in phase with the logical 1 output from the quantity ISWND and the AND network 828 will apply a logical 1 output quantity to the OR network 86A. When a logical 1 input quantity is supplied to one or both of its input terminals the OR network 86A supplies a logical 1 signal to the input terminal 87 of the AND network 110. With a normally operating network 52, the

input terminals

182 and 126 will be provided with logical 1 quantities and the

input terminals

136, 123 and 103 will be supplied with logical 0 signal so that when a logical 2 signal is supplied to the

input terminals

54A and 87 the AND network 110 will supply a logical 1 output quantity or signal to the time delay 90. If this quantity is existent for the total of the timing intervals of the timers 90 and 908 or the timer 90 times out twice in rapid succession (indicative of fault current flowing into the line section from both ends at the same time or flowing outwardly of the line section at the same time) a logical 1 signal will be supplied to the input terminal 92 of the trip board 94. This results in a logical 1 signal on the conductor 25 the tripping of the breakers 10, 11 and 12.

Referring to the operation of the keyer 72 which is more completely shown and described in said copending application, it will be appreciated that its input terminal 174 is normally supplied with a logical 1 signal. In the absence of a fault, a logical 0 signal will be applied to the input terminal 98 assuming a logical 0 input signals to each of the input terminals 100 and 118 whereby a logical 1 signal is supplied at the output terminal 74. Under these conditions, the transmitter frequency control 76 will maintain the transmitter portion of the transmitter-receiver 78 in a condition in which it will transmit its guard signal.

In the event of the occurrence of a fault, the input terminal 98 will be energized with a logical 1 signal thereby establishing a logical 0 signal at the output terminal 74. The alternating logical l and logical 0 signals normally applied to the input terminal 71 by the quantity I provides alternating logical 1 and logical 0 sig nals at the output terminal 73 which with a logical 1 output signal at terminal 74 renders the transmitter frequency control 76 effective to drive the transmitter portion of the transmitter-receiver to terminate the transmission of guard signal and commence the transmission of the trip positive and trip negative signals to provide the phase related signal to the receiver portion of the transmitter-receiver 78 at the remote end of the protected line. Similarly the recognition of a fault at the remote line terminal will cause its transmitter to terminate its transmission of guard signal and commence the transmission of trip positive and trip negative signals from the remote end or station to the local end or station to provide the Rl signal which is indicative of the phase of the current at the remote end. The Rl signal is supplied to the AND

networks

82A and 82B to permit a logical 1 signal to be supplied to the input terminal 87 of the AND network 110 if the phase of the current at the two end portions of the protected line section indicates that the fault is internal and will prevent a logical 1 signal from being supplied to the terminal 87 in the event that the phase relationship of the two currents indicates that the fault is external to the protected lines section.

In the event of a fault current magnitude above the maximum required to energize the I overcurrent network 64, a logical 1 signal will be applied to the input terminal 99. This terminal 99 is connected within the trip board 94 to the conductor 25 and to the conductor which is connected to the terminal 100 of this keyer 72, so that a logical 1 input signal supplied to the

terminals

73 and 73A and a logical 0 signal to the

terminals

74 and 74A as is more fully shown in said copending application. When a logical 0 output signal is supplied to the terminal 74, the transmission of guard signal by the transmitter portion of the transmitter-receiver 78 is interrupted. A continuous logical 1 signal at the output terminal 73 causes the transmitter portion of the transmitter receiver 78 to send a continuous tripping signal to the other terminal so that one of the AND

networks

82A or 82B will be energized to place a tripping logical 1 signal at the input terminal 87 of the AND network 1 of the opposite or remote station to permit tripping of the remote circuit breaker irrespective of the phase relationship of the current at the two ends of the transmission line.

In the said copending application the time delay 90 is shown as a set to time out a time interval of 4 milliseconds, which as used therein, establishes a minimum conicidence time which indicates that the fault is within the protected section. At the end of this 4 millisecond interval the trip signal is supplied by delay 90 in the trip board. It' sometimes happens that in the clearing of a fault external to the protected line section transient currents occur which falsely indicate a 4 millisecond coincidence time which does not occur because of the occurrence of an interval fault. To prevent such an occurrence resulting in a false trip of the associated breakers it has been known to utilize a network 90A which requires at least two timeouts of the coincidence timer 90. When this expedient is used it means not only the second time required for the coincidence timer to time out in this case 4 milliseconds but in addition the second timing out cannot commence until a second half cycle of the alternating current occurs. In the case of a 60 Hz supply and a 4 millisecond timer this results in an additional interval of at least 8 milliseconds. This situation is undesirable especially at high fault currents.

In accordance with this invention, there is connected in shunt circuit with the two-count timer 90A a 2/0 timer 90B. The timers 90A and 90B have their input connections connected to the output connection of the timer 90 and their output connection connected to an OR network 90C. The output connection of the OR network 90C is connected to input terminal 92 of the trip board 94.

With this arrangement, the breakers may be tripped either at the second output of the coincidence timer 90 by means of the-two-count timer 90 or at the first output of the coincidence timer 90A when the time duration of the coincidence of the remote and local current signals is equal to or greater than the total of the timing intervals of the timers 90 and 90B.

With high fault currents, the duration of the coincidence will normally be from 5 to 8 milliseconds depending upon the fault and it is therefore proposed that the total of the timing intervals of the timers 90 and 90B should be from 5 to 8 milliseconds. It has been common to utilize a coincidence timing of 4 milliseconds as a compromise setting between the prompt detection of an interval fault and the protection against false tripping due to the clearing of external faults or otherwise. By using the timer 908 in conjunction with the two-count timer 90A, the interval of timer 90 may be decreased in magnitude upward to at least 75 percent of the normal value of 4 ms since, if a spurious signal to the timer 90 greater than its time interval but less than the total time intervals of timers 90 and 90B occurs it will not cause a false tripping of the breakers.

This reduced timing interval of timer will permit a desired tripping of the breakers due to an interval fault with a current coincidence of only 3 milliseconds during the second of two half cycles which ""sccur within the resetting time of the two-count timer 90A as will be described below to give added breaker tripping protection in the case of interval faults with small current coincidence intervals.

The addition of the timer 908 with its timing interval adjusted relative to that of the timer 90 will permit rapid breaker tripping in the case of internal faults with a high coincidence time such as normally occurs with high fault current which if not promptly interrupted can cause major damage to the effected apparatus and to the system stability.

A suitable two-count timer 90A is shown in FIG. 3 and includes timers 200 and 202 and AND

networks

204 and 206. When a logical 1 signal is applied to input terminal 208 of the timer 90A, the timer 201 times out in a very short interval herein shown as being 0.1 millisecond whereby a logical 1 signal is applied to the noninverted input 210 of AND network 204. AND network 204 is prevented from supplying a logical 1 signal to the timer 202 because of the logical 1 signal then being applied to the inverted or NOT input terminal 212 of the AND network. When the logical 1 signal is removed from terminal 208 at the end of the coincident time (timer 90 being constructed to reset and have a logical signal at its output without intentional time delay) a logical 0 signal will be applied to terminal 212 concurrently with the application of a logical 1 signal to terminal 210 for 25 milliseconds (timer 200 being designed to have a predetermined reset time of 25 ms) and the AND network 204 will supply a logical 1 signal to the timer 202.

Timer 202 after a 0.5 millisecond time delay will provide a logical 1 signal to input terminal 214 of AND network 206. AND network 206 will continue to supply a logical 0 signal to the output terminal 216 of the two-count timer because at this time the logical 0 signal being supplied by timer 90 to the input terminal 208 which is connected to the input terminal 218 of the AND network 206. No further timing out of the timer 90 indicative of a subsequent current coincidence within 25 milliseconds after the initial timing out of the timer 90, the timer 200 resets and supplies a logical 0 signal to input terminal 210. This results in a logical 0 input signal to timer 202 which resets after a 2 millisecond time interval and removes the logical 1 signal at the input terminal 214 whereby the two-count timer is reset to its initial or standby condition.

If, however, the timer 90 times out before the twocount timer resets as would normally occur if an internal fault is detected, the timer 90 will supply a second logical 1 signal to input terminal 208 and thereby to the input terminal 218, while the timer 202 is still maintaining a logical 1 signal on input terminal 214 which condition results in the AND network 206 supplying a logical 1 signal to the output terminal 216. When this occurs the OR network 90C supplies a logical l or tripping signal to the terminal 92 and the trip board 94, thereupon energizes the tripping network 24 to trip the breakers 10, l1 and 12.

It should be appreciated that while there is shown herein a tripping network 24 which acts to trip all of the breakers, this invention is equally applicable when the raising network is arranged to trip i ndividiiaTbrakers such as described in the said copending application.

What is claimed and is desired to be secured by United States letters patent is as follows:

1. A phase comparing relay comprising a phase comparing network having first and second input circuits and an output circuit, said network being effective to actuate its said output circuit solely when the phase of the pulsing signals supplied to its said input circuits are within a predetermined phase relationship, a first timer having its input connected to said output circuit of said comparing network and having an output actuated at the end of a first predetermined time interval following said actuation of said output circuit of said comparing network, a second timer having its input connected to said output of said first timer and having an output actuated at the end of a second predetermined time interval following said actuation of said output of said first timer, a counting network having its input connected to said output of said first timer and having an output actuated as a consequence of a plural number of said actuations of said first timer, a breaker tripping network, and connecting means interconnecting said tripping network to said outputs of said second timer and of said counting network, said connecting means being effective to actuate said tripping network as a consequence of saidactuation of said output of either of said second timer or of said counting network.

2. The relay of claim 1 in which said second predetermined time interval is less than said first predetermined time interval. I

3. The relay of claim 2 in which said plural number is two.

4. The relayof claim 1 in which said plural number is two.

5. The relay of claim 4 in which said pulsing signals have a'frequency of 60 hertz, said first predetermined time interval approximates 3 milliseconds and said second predetermined time interval approximates 2 milliseconds.

6. The relay of claim 1 in which shunt means is provided to connect said tripping network to said output of said first timer in shunt relationship with at least one of said second timer and said counting network.

7. The relay of claim 6 in which said shunt means shunts both of said second timer and said counting network.

Claims

1. A phase comparing relay comprising a phase comparing network having first and second input circuits and an output circuit, said network being effective to actuate its said output circuit solely when the phase of the pulsing signals supplied to its said input circuits are within a predetermined phase relationship, a first timer having its input connected to said output circuit of said comparing network and having an output actuated at the end of a first predetermined time interval following said actuation of said output circuit of said comparing network, a second timer having its input connected to said output of said first timer and having an output actuated at the end of a second predetermined time interval following said actuation of said output of said first timer, a counting network having its input connected to said output of said first timer and having an output actuated as a consequence of a plural number of said actuations of said first timer, a breaker tripping network, and connecting means interconnecting said tripping network to said outputs of said second timer and of said counting network, said connecting means being effective to actuate said tripping network as a consequence of said actuation of said output of either of said second timer or of said counting network.

2. The relay of claim 1 in which said second predetermined time interval is less than said first predetermined time interval.

3. The relay of claim 2 in which said plural number is two.

4. The relay of claim 1 in which said plural number is two.

5. The relay of claim 4 in which said pulsing signals have a frequency of 60 hertz, said first predetermined time interval approximates 3 milliseconds and said second predetermined time interval approximates 2 milliseconds.