US3824349A

US3824349A - Method of transferring information

Info

Publication number: US3824349A
Application number: US00381755A
Authority: US
Inventors: R Buchner
Original assignee: US Philips Corp
Current assignee: US Philips Corp
Priority date: 1971-02-04
Filing date: 1973-07-23
Publication date: 1974-07-16
Anticipated expiration: 1991-07-16
Also published as: AU3848072A; BE778878A; FR2125084A5; DE2201856A1; CA975477A; AU458786B2; DE2201856B2; NL7101468A; GB1336542A

Abstract

A method of transferring information via a time-switched connection which extends via at least one first time channel with which a channel interval of a first cycle is associated, a synchronizer, a data register and a second time channel with which a channel interval of a second cycle is associated. For the loss-free transfer of the information to an information receiver the data register is read out at least three times in a nondestructive manner in each second cycle, the original information being derived from the multiple information thus obtained by elimination of the excess of information.

Description

United States Patent [191 [11] 3,824,349 Buchner July 16, 1974 F I 3,676,599 7/1972 Heetman 1 79/15 BS INFORMATION [75] Inventor: Robert Bertold Buchner, Hilversum, Primary Examiner-Ralph Blakeslee N h l d Attorney, Agent, or Firml rank R. Trifari; Simon L. [73] Assignee: U.S. Philips Corporation, New Cohen York, NY.

[22] Filed: July 23, 1973 [57] ABSTRACT PP 381,755 A method of transferring information via a time- Related Us. Appncation Data switched connection which extends via at least one [63] C f S N 221 234 J 27 1972 first time channel with which a channel interval of a 52 2 2 15 0 first cycle is associated, a synchronizer, a data register r and a second time channel with which a'channel inter- [52] U S Cl 179/15 BS 178/69 5 R 179/15 BY val of a second cycle is associated. For the loss-free [51] H04j 3/06 transfer of the information to an information receiver [58] Fieid BY the data register is read out at least three times in a 179/15 A 17/69 5 non-destructive manner, in each second cycle,. the original information being derived from the multiple 56] References Cited information thus obtained by elimination of the excess of information. UNITED STATES PATENTS t- 3,632,883 1/1972 Aagaard 179/15 AQ 2 Claims, 10 Drawing Figures 101-1 102-1 104 -1 [107 DATA STORE SYNCHRONIZERS 03-1 108 a l 101-8 106 100-8 l/ MULTIPLEXER CYCL'C SIGNALLING STORE INFORMATION STORE Pmmmm 6 m4 DCBA SHEEI30F3 AAA DDD

2B'AA seas SCBB' vccs sccc

Fig.5

Fig.6

METHOD OF TRANSFERRING INFORMATION This is a continuation of application Ser. No. 221,234, filed Jan. 27, 1972, now abandoned.

The invention relates to a method of transferring in formation via a time-switched connection. The connection extends via at least a first time channel with which a channel interval of a first cycle of channel intervals is associated. The information is also transferred through a synchronizer, a data register and a second time channel with which a channel interval of a second cycle of channel intervals is associated. The nominal duration of said second cycle is equal to the nominal duration of the first cycle. The synchronizer transfers the information received via the first time channel to the data register in channel intervals of the second cycle. The position of the latter channel intervals in the second cycle is changed in accordance with the phase difference between these channel intervals and the channel intervals of the first time channel.

This method is used in telecommunication exchanges in which connections are established between channels of pulse code modulation time-division multiplex transmission systems. The data register which is permanently associated with the first time channel determines the location in space of the first time channel. By reading out this register in the channel intervals of the second time channel a (time-switched) connection is maintained between the first and the second time channel. In a connection of this kind information may be lost if the data register is written in at a rate which is higher than the rate which it is read out. The rate in which writing in takes place is dependent upon the rate at which the information of the first time channel is received, while the rate of readout is determined by the clock of the telecommunication exchange. In a nominal sense these two rates are the same, but they may acquire an unlimited phase difference in .nonsynchronized telecommunication systems, so that it may occur that from time to time information is written in twice in succession without information being read out in between. The information which is first written in is then lost. I

The invention has for its object to prevent loss of information in time-switched connections of this kind. This is of special importance if the first time channel is a so-termed common signalling channel.

The method according to the invention is characterized in that for the loss-free transfer of the information to an information receiver, the data register is read out at least three times in a non-destructive manner in each second cycle, the original information being derived from the multiple information thus obtained by elimination of the excess information.

In order that the invention may be readily carried into effect, one embodiment thereof will now be described in detail, by way of example, with reference to the accompanying diagrammatic drawings, in which:

FIG. 1 shows a block diagram of a portion of a telecommunication exchange using pulse code modulation and time-division multiplex,

FIGS. 2a-2c show some time diagrams for illustrating the operation of the portion of the telecommunication exchange shown in FIG. 1,

FIGS. 3a-3c show corresponding time diagrams for illustrating the method according to the invention,

FIG. 4 shows an example of a logic diagram of a device for eliminating the excess of information, and

FIGS. 5 and 6 show tables for illustrating the operation of the device shown in FIG. 4.

The problem of the loss-free transfer of information via time-switched connections, using independent clocks in different parts of the connections, will be described with reference to FIG. 1. This Figure shows a portion of a telecommunication exchange in which time-switched connections are established between receive channels and send channels of PCM transmission systems with time-division multiplex. Each PCM system comprises a receive highway and a send highway, each of which comprises n one-way channels, each channel utilizing a different time interval (channel interval) of a cycle of time intervals. In the present case it will be assumed that n 32. In FIG. 1 the references 100-1 and 100-8 denote the first and the eighth receive highway of a group of eight PCM systems.

Information is transferred via a PCM highway in frames,each of which is divided into 32 character locations, each character location being divided into, for example, 8 bit locations. Accordingly,'the time on a PCM highway is divided into time frames, each of which comprises 32 channel intervals, each channel interval being divided into 8 bit intervals.

The telecommunication exchange under consideration has a cycle which comprises more time intervals than the cycle of a PCM highway. The number of channels of an internal PCM highway of the telecommunication exchange is accordingly larger. In particular, the telecommunication exchange under consideration has a cycle of 16 X 32 512 time intervals, which means that the number of time intervals of a cycle is twice as large as the number of channels of a group of eight external PCM highways. In the exchange the 8-bit characters are transferred in parallel form, utilizing seriesparallel converters at the receive side and parallelseries converters at the send side of the exchange. The converters provide the adaptation between the transfer in series form on the external PCM highways and the transfer in parallel form on the internal PCM highways of the exchange. Each of the 512 time intervals of a cycle of the telecommunication exchange determines a channel interval on each of the internal PCM highways.

The telecommunication exchange also determines the channel intervals on the send highways of the connected PCM transmission systems; for this purpose the cycle of the exchange is divided into 32 main time intervals, each of which comprises 16- of the previously mentioned 512 time intervals, the latter being referred to hereinafter as sub-time intervals. Consequently, each sub-time interval determines an (internal) channel of each internal PCM highway, and each main time interval determines an (external) channel of each external send highway.

The receive highways -1 and 100-8 terminate in the synchronizers 101-1 and 101-8, respectively, which convert the received information characters to the time scale of the telecommunication exchange. Simultaneously with this conversion in time, the characters are converted from the series to the parallel form for each character the channel number is determined.

The synchronizers used are devices of known construction and'operation. Consequently, the operation of these devices will be described only in as far as it is of importance for understanding the present invention.

registers. The received characters are cyclically distributed over the character registers by a first distributor under the control of a receive clock which supplies clock signals which are synchronized with the bits, the

characters and the frames of the receive highway. The characters are read out of the receive buffer in main time intervals under the control of the clock of the exchange. The character registers are read out by a second distributor in a cyclical manner and in the same sequence as during writing in. The bits of a character are read out simultaneously so that each character read out has the parallel form. The read-out characters are applied to an input highway of the telecommunication exchange, the said input highway being denoted in FIG. 1 by the references 102-1 and 102-8, respectively.

The channel numbers are determined by counting the read-out characters modulo-32. The receive clock gives an indication as regards the beginning of each receive cycle. The indication is stored in a flip-flop from which it is read out by the central clock with the same relative time delay as is caused by the receive buffer in the transfer of the characters. The indication which is read out of the flipflop is used for-synchronizing a modulo-32 counter to the beginning of the cycle of the receive highway. Each time that a character is read out, the counter contents are increased by one so that for each read-out character the associated channel number is generated. The channel numbers are applied to a number highway which is denoted in FIG. 1 by the references103-1 and 103-8, respectively.

In asynchronous telecommunication systems each exchange has a clock which is independent of the clocks of the other exchanges. As a result, no upper limit exists as regards the phase difference between the clocks. in the telecommunication exchange under consideration the phase difference between the central clock and a receive clock may reach any value. The receive buffer of the synchronizer can compensate for only a limited phase difference.

in the synchronizer the phase of the first distributor is compared with the phase of the second distributor.

The first distributor has a cycle of four channel intervals of the receive clock, while the second distributor has a cycle of four main time intervals of the central clock. Due to differencesin the speed of the receive clock and of the central clock, differences will occur between the cyclic speeds of these distributors. By

measuring the phase difference between two distributors it is determined whether the phase difference is liable to decrease below a critical value. This critical value is the value at which writing and reading are simultaneousl y effected in one and the same channel register. Before the said critical value is reached, a correction signal is generated and the phase of the second distributor is corrected. If, the first distributor gains on the second distributor, then after the correction signal the second distributor is advanced one additional step, corresponding to a decrease of the duration of one of the cycles thereof with one main time interval. One character is then skipped during reading. However, if the second distributor gains on the first distributor, the second distributor is held after the alarm .so that it performs a ration of one of the cycles thereof with one main time interval. During the step in place the character of the character register indicated by the second distributor is read out once more.

The channel number counter is synchronized by making it perform an additional step or a step in place, respectively, simultaneously with the second distributor. The characters are then applied to the input highway and the number highway with the correct channel numbers at all times.

Hereinafter it will be assumed that the instants at which the phase of the second distributor is corrected are chosen to be such that only characters of the synchronization channel, which may be the channel having the number 32, can be skipped. In this way no information characters are lost.

The input highways 102-1 and 102-8 and the number highways 103-1 and 103-8 terminate in a multiplexer 104 having a cycle of one main time interval. The output of multiplexer 104 is formed by an internal highway 105 and an internal number highway 10.6 which terminate in a data store 107. The multiplexer 104 connects the input highway 102-1 to the internal highway 105 in the first sub-time interval of each main time interval, and simultaneously connects the number highway 103-1 to the internal number highway 106. In the second sub-time interval of each main time interval the multiplexer establishes the corresponding connections for the second receive highway of the group of eight, and so on in the third to the eighth sub-time interval inelusive of each main time interval. In this way eight of the sixteen sub-time intervals of each main time interval are used for transferring the characters from receive highways -1 to 100-8 to the data store 107. The remaining eight sub-time intervals of each main time interval can be used for other'purposes or may be left unused.

The data store 107 comprises 256 data registers, i.e. one register for each channel of a group of eight receive highways. Each of these registers is capable of storing one character and can be addressed by a channel number. The data store 107 stores each character which is received from the internal highway in the register which is addressed by the channel number which is received from the internal number highway 106. The output of the data store 107 is formed by the internal highway 108.

a step in place," corresponding to an increase of the du- The data store 107 is controlled by a cyclic store 109 having 512 store locations, i.e. one store location for each channel of the internal highway 108. By storing a channel number in a chosen location of store 109, the register of the data store 107 corresponding to this channel number is read out once every cycle, and the read-out character is applied to the internal highway 108 in the sub-time interval (channel interval) corresponding to the chosen store location. in this way a (time-switched) connection can be maintained between each channel of the relevant group of eight re- The repetition period on the internal highway 108 of the characters originating from one and the same receive channel is always equal to one cycle of the central clock. Due to the differences between the repetition periods on the internal highways 105 and 108, characters will occasionally be skipped in the data store or will be read twice, respectively. In order to illustrate this aspect, a simplified system will be considered, comprising a group of 3 receive highways, each of which comprises 4 channels and having a cycle of 24 sub-time intervals.

It is assumed that a character is written in the data store in the first half of a sub-time interval, and is read out of the data store in the second half of a sub-time interval. Under consideration is a series of characters A, B, C, D, originating from one and the same receive channel. FIG. 2a illustrates the instants at which the characters are written in thedata store 107. The character A is written in in the first sub-time interval of the first main time interval of the cycle of the central clock. This sub-time interval is denoted by 1.1 in the FIG. 2a. In general, the reference i. j. denotes the j" sub-time interval of the i' main time interval. It is assumed that the register of the data store corresponding to the receive channel under consideration is read out in the sub-time interval 1.5. Consequently the character A is read out in the sub-time interval 1.5 following the sub-time interval 1.1 in which the character A is written in, as is illustrated in FIG. 2b. The character B will normally be written in in the sub-time interval 1.1 of the next cycle. However, it is assumed that the repetition period has been prolonged by one main time interval, so that the character B is written in in the sub-time interval 2.1. In the preceding sub-time interval 1.5 the character A is read out again, assuming that the characters are read out from the data store in a non-destructive manner. In the sub-time interval 1.5 of the next cycle the character B is read out, in the sub-time interval 1.5 of the next cycle the character C is read out, and so on.

FIG. 3 illustrates the case where a character is skipped due to a reduction of the repetition pe5iod. Again a series of characters A, B, C, D, originating from one and the same receive channel, is considered. FIG. 3a illustrates the instants at which the characters are written in the data store. The character A is written in in the sub-time interval 1.1. It is assumed that the register of the receive channel under consideration is read out in sub-time interval 3.5. In the sub-time interval 3.5 which follows the sub-time interval 1.1 in which the character A is written in, the character A is read out as is illustrated in FIG. 3b. The character B will normally be written in in the sub-time interval 1.1 of the.

next cycle. However, it is-assumed that the repetition period is reduced by one main time interval so that the character B is already written in the sub-time interval 4.1 of the same cycle. The character B is read out in the sub-time interval 3.5 of the next cycle. The character C is written in in the sub-time interval 4.1 of this cycle. The character D is normally written in in the sub-time interval 4.1 of the next cycle. However, it is assumed that the repetition period is again reduced by one main time interval, so that the character D is written in in the sub-time interval 3.1 of this cycle. The character D is and the channels of the internal highway 108. Whether or not a connection is affected by a phase correction will depend on the relative positions of the sub-time intervals in which writing in the reading out take place in the data store for the connection. For example, FIG. 3 clearly shows that the relevant connection is not affected by the first phase correction which results in a shift of the sub-time interval for writin g in the character B. The character is lost only after the second phase correction, which results in a shift'of the sub-time interval for writing in the character D. In the simplified system comprising only 4 channels per receive highway, a character is skipped or is transferred twice, respectively, in each connection after 4 phase corrections in the same direction. In the system used in practice each connection is affected once after 32 phase corrections in the same direction, corresponding to a phase shift between the cycle of the receive highway and the cycle of the central clock of 360 or one frame. If stable clocks are used in the exchanges, the frequency at which an error occurs error to be understood to mean in this. case the loss of a character or the additional occurrence of a character, respectively is very low. During the transfer of speech signals these errors are hardly noticeable. A problem arises if data are transferred via a connection.

For transferring signalling information, modern telephone systems make use of a so-termed common signalling channel via which the signalling information is transferred in the form of coded messages. In PCM system use is made of a given time channel for this purpose. For this signalling channel it is desirable that the information is transferred without loss. In FIG. 1 the reference 110 denotes a signalling information store which is connected to the internal highway 108 and which acts as the receiver and the buffer of the signalling information which is supplied, by the signalling channels of the group of receive highways -1, 100-8. The connections between the signalling channels on the one side and the store on the other side extend via the data store 107 in the same manner as the speech connections.

In order to preventsignalling characters from being lost due-to phase corrections, the invention proposes that each register of the data store 107 which corresponds to a signalling channel is read out in each cycle of the central clock three times with intervals of at least one main time interval. Each read-out character is transferred to the store 110. Normally, each signalling character is then transferred'three times to the store 110 and, due the phase corrections, this number is occasionally increased or decreased by one, respectively, so that, for example, a series of signalling characters R, S, T, U, originating from a signalling channel changes into the modified'series R, R, R, S, S, S, S, T, T, T, U, U, U, or into the series R, R, R, S, S, T, T, T, U, U, U, The latter series can be restored to the former series by a simple logic operation.

The foregoing is illustrated in the FIGS. 20 and 30 for the already described series of characters A, B, C, D, It is assumed that the relevant register of the data store is read out in the sub-time intervals 1.5, 2.5 and 3.5 of each cycle of the central clock. First FIG. 2 will be considered. In the sub-time interval 1.5 which follows the sub-time interval 1.1 in which the character A is written in in the data store, the character A is read out as is illustrated in FIG. 2c. Similarly, in the subsequent sub-time intervals 2.5 and 3.5 the character A is read out. Due to the shift of the instant at which the character B is written in, the character A is read out again in the sub-time interval 1.5 of the next cycle, so that the character A is read out four times in total. In the sub-time intervals 2.5 and 3.5 of this cycle and in the sub-time interval 1.5 of the subsequent cycle, the character B is read out and so on. In this way the series A, A, A, A, B, B, B, C, C, C, is formed. Now'FlGj 3 will be considered. In the sub-time interval 1.5 which follows the sub-time interval 1.1 in which the character ter D is read out in the sub-time interval 3.5, so that the character C in total is read out twice instead of three times. In the sub-time intervals 1.5 and 2.5 of the subsequent cycle the character D is read out again and so on. In this way the series A, A, A, B, B, B, C, C, D, D, D, is formed.

FIG. 4 illustrates the logic diagram of a logic unit for converting the modified series read out of the data store into the original series. It is to be noted that this logic diagram can be realized in different manners, for example, by a suitable programming of the control processor of the telecommunication exchange. The logic diagram is adapted to the simplified system and the examples of the FIGS. 2 and 3.

The characters originating from the data store 107 are applied to the three-stage shift register 401 via input terminal 400. The shift pulses for the shift register are derived from the output of AND-gate 402, having a first input to which the clock pulses cs are applied, and a second input which is connected to the output of OR-gate 403. The OR-gat'e has a first input to which the clock signal S is applied, a second input. to which the clock signal 5 is applied anda third input to which the clock signal 53.5 is applied. A clock pulsecs is a clock pulse which occurs in a sub-time interval. A clock signal S is'a 2-state signal having the state 1 in each sub-time interval 1.5, and a clock signal S generally is a 2-stage signal having the state 1 in each sub-time interval i.j., i and j being arbitrary integral numbers. Due to the action of AND-gate 402 and OR- gate 403 shift pulses are applied to the shift register 401 only in the sub-time intervals 1.5, 2.5 and 3.5. Consequently, only the characters appearing on the input terminal 400 in the sub-time intervals 1.5, 2.5 and 3.5 are stored in the shift register. Each shift pulse shifts the characters one location further in the shift register so that each character is shifted out of the shift register after three shift pulses,

The three stages of the shift register 401 have individual outputs. The output of the first stage and the output of the second stage are connected to different inputs of a first comparing unit 404. The output of the second stage and the output of the third stage are connected to different inputs of a second comparing unit 405. The output signal of each comparing unit is a 2-state signal which has the state 1 only if the two characters applied to the comparing unit are equal.

A pair of

flipflops

406 and 407 serve for storing the states of the output signals of the comparing

units

404 and 405. Connected between the outputs of the comparing units and the inputs of the flip-flops are a pair of AND-

gates

408 and 409. AND-gate 408 has a first input which is connected to the output of comparing unit 404, a second input which is connected to the output of AND-gate 412, and an output which is connected to the input of flip-flop 406. AND-gate 409 has a first input which is connected to the output of comparing unit 405, a. second input which is connected to the output of AND-gate 412, and an output which is connected to the input of flipflop 407. The

flipflops

406 and 407 are controlled by the clock pulses which are derived from the output of AND-gate 410, under the control of which the state of the output signals of the AND-

gates

408 and 409 is stored in the flip-flops. AND-gate 410 has a first input which isconnected to the output of OR-gate 411, and a second input to which the clock pulses cs are applied. OR-gate 411 has a first input for the clock signal S a second input for the clock signals S and a third input for the clock signal 8 Due to the action of the AND-

gates

408, 409 and 410 and of OR-gate 411, the states of the output signals of the comparing

units

404 and 405 are stored in the

flipflops

406 and 407 in the sub-time intervals 1.6, 2.6 and 3.6, provided that the output signal of AND-gate 412 has the state 1 in these sub-time intervals. If the output signal of AND-gate 412 has the state 0 in these sub-time intervals, the flip-

flops

406 and 407 are reset to the state 0. The latter is dependent of the result of preceding comparisons, as will be described hereinafter. v

Each of, the

flipflops

406 and 407 hastwo outputs which are denotedin the Figure by the

references

1 and 0. These outputs supply inverse 2-stage signals. The 1- output supplies a 2-stage signal which has the state 1, when the state ,1 is stored in the fiipflop. The 0- output then supplies a signal having the state0. The l-outputs of the

flipflops

406 and 407 are connected to differentinputs of AND-gate 413. The 0-output of flipflop 406 and the l-output of flipflop 407 are connected to different inputs of AND-gate 413. The 0-output of fliptlop 406 and the l-output of flipflop 407 are connected to different inputs of AND-gate 414.

The output of AND-gate 413 is connected to the input of flipflop 415, the l-output of which is connected to the input of flipflop 416. The output of AND- gate 414 is connected to the input of flipflop 417. The

. clock pulses for controlling the

flipflops

415, 416 and 417 are derived from the output of AND-gate 418. This AND-gate has a first input to which the clock pulses cs are applied, and a second input which is connected to the output of OR-gate 419. This OR-gate has three different inputs to which the clock pulses S S and S respectively, are applied. The result of the action of AND-gate 418 and OR-gate 419 is that in the sub-time intervals 2.1, 3.1 and 4.1 clock pulses are applied to the flipflops .415, 416 and 417. The O-outputs of the

flipflops

415, 416 and 417 are connected to different inputs of AND-gate 412. The result thereof is that the output signal of OR-gate 412 has the state 1 only if all

flipflops

415, 416 and 417 are in the state 0."

A second shift register 420 serves for storing the original series of characters. The input of shift register 420 is connected to the output of the second state of shift register 401. The shift pulses for shift register 420 are derived from the output of AND-gate 421. This AND- gate has a first input which is connected to the output of AND-gate 402, and a second input which is connected to the output of OR-gate 422. This OR-gate has a first input which is connected to the l-output of flipflop 415, and a second input which is connected to the l-output of flipflop 417. Due to the action of OR-gate 422 and AND-gate-42l, shift pulses are applied to shift register 420 in the sub-time intervals 1.5, 2.5 and 3.5, provided that flipflop 415 or flipflop 417 is in the state is 1.77

Hereinafter x represents a variable which cyclically assumes the

values

1, 2 and 3 in time, x 1 represents the value succeeding the value ofx, x 2 represents the value succeeding the value ofx l, and so on.

The operation of the device shown in FIG. 4 is as follows. In each sub-time interval x.5 a shift pulse is applied to the shift register 401, so that a character is shifted into the first stage and all characters in the shift register are shifted one location. In the subsequent subtime interval x.6 the states of the

comparison units

404 and 405 are taken over by the flipfiops 406 and 407. This continues until flipflop 407 is set to the state 1, which is the case when, after a shift is shift register 401, the character of the second stage is the same as the character of the third stage. Two cases can be distinguished. In the first case flipflop 406 remains in the state when flipflop 407 is set to the state 1, and in the second case flipflop 406 is set to the state I simultaneously with flipflop 407. In the first case flipflop 417 is set to the state "1 in a sub-time interval (.r +1 ).1 under the control of AND-gate 414.

Flipfiop 417 then actuates the AND-gate 421 via OR- gate 422, so that in the first of the sub-time intervals (.r H5 which follows the latter sub-time interval (x l).l the character of the second stage of shift register 401 is transferred to shift register 420. Furthermore, flipflop 417 sets the output signals of the AND-

gates

408 and 409 to the state 0" via AND-gate 412, so that in the sub-time interval (.r l).6 which follows the latter sub-time interval (.r l ).5 the flipflops 406 and-407 are reset to the state 0. As a result, flipflop 417 is reset to the state 0 in the first of the sub-time intervals (.r 2).1 which follows the latter sub-timeinterval (.r +1 ).6. In the first of the sub-time intervals (.r 2).5 which follows the latter sub-time interval (x 2).1 the AND-gate 421 is inoperative and no character is transferred to register 420. After a character has been transferred, the transfer is blocked once, independent of the states of the

comparison units

404 and 405.

In the second of the above-mentioned cases the flipflop 415 is set to the state 1" in a sub-time interval (.r l ).1. This flipflop has the same operation as flipflop 417 so that a character is transferred to register 420 and the

flipflops

406 and 407 are reset to the state 0. In the first ofthe sub-time intervals (.r-l- 2).1 which follows the latter sub-time interval (1' l).l, the flipflop 415 is reset to the state 0, and flipflop 416 is set to the state 1. As a result, the

flipflops

406 and 407 remain in the state 0 in the first of the sub-time intervals (x 2).6 which follows the latter sub-time interval (.r 2).1. The AND-gate 421 is then operative in the first of the sub-time intervals (x 3).5 which follows the latter sub-time interval (x 2 ).6, so that no character is transferred to register 420. After a character has been transferred, the transfer is blocket twice in this 10 second case, independent of the state of the

comparison units

404 and 405.

The first time that equality is detected between the characters of the second and the third stage after a shift in shift register 401, the character of the second stage is transferred to shift register 420. After the next shift in shift register 401, the states of the

comparison units

404 and 405 are not taken over by the

flipflops

406 and 407. As a result,

flipflops

415 and 417 remain in the state 0, and AND-gate 421 remains blocked via OR- gate 422, so that no character is transferred to shift register 420. In other words: after each transfer of a character the transfer is unconditionally blocked once. If equality is also detected between the characters of the first and the second stage of shift register 401 prior to the transfer of a character, the states of the

comparison units

404 and 405 are not taken over by the

flipflops

406 and 407 twice in succession. After the transfer of a character, the transfer is then unconditionally blocked twice in succession.

The operationof the device according to FIG. 4 upon reception of the series A, A, A, B, B, B, B, C, C, C, D, D, D, is illustrated in the table of FIG. 5. The

columns

1, 2 and 3 correspond to the first, the second and the third stage of shift register 401, respectively. The

columns

4, 5, 6 and 7 correspond to the first, the second, the third and the fourth stage, respectively, of shift register 420. Each lineshows the contents of the stages of the shift registers at a given instant. Shift register 401 reaches the state of line 1 after three shifts following the start of the series. In this state equality is detected betweenthe characters of the

columns

2 and 3 and those of the

columns

1 and 2. The character A of column 2 is transferred to shift register 420. The transfer is subsequently unconditionally blocked twice in succession, so that after the states of the

lines

2 and 3 have been reached, no character is tranferred. After the state of line 4 has been reached, the character B is tranferred to shift register 420 and the contents thereof are shifted, one location further. The transfer is subsequently unconditionally blocked twice in succession '(1ines5 and 6). In the state of line 7 no equality is detected between the characters of the

columns

2 and 3, so that also in this case no transfer is effected. After the state of line 8 has been reached, the character C of column 2 is transferred to the shift register 420, and so on. After the state of line 11 has been reached and the subsequent transfer of the character D has been effected, the original series is stored in the shift register 420.

In the table of FIG. 6 the corresponding operation is illustrated which a series A, A, A, B, B, C, C, C, D, D, D, is received. With respect to FIG. 5 it is to be noted that in the state of line.4 equality is detected only between the characters of the

columns

2 and 3, so that after the transfer of the character B of column 2 to shift register 420 the transfer is unconditionally blocked only once.

What is claimed is:

l. A device for transferring information from a first channel in the form of a first cycle of channel intervals to a second channel in the form of a second cycle of channel intervals where the nominal duration of the first cycle of channel intervals is equal to the nominal duration of the second cycle of channel intervals, comprising a data register, synchronization means connected to the first channel for sequentially providing the information of the first channel to the data register 1 1 in channel intervals of the second cycle shifted within the second cycle of channel intervals by an amount corresponding to the phase shift between the first cycle of channel intervals and the second cycle of channel intervals, scanning means for non-destructively reading out the data register at least three times in each second cycle of channel intervals thereby forming multiple information words, means for sequentially storing the scanned information, comparator means for providing a control signal in response to a condition wherein the stored scanned information is identical to the preceding stored scanned information, and logic means responsive to the control signal for transferring the stored scanned information into the second channel one time in response to at most (11 l successive control signals where n is an integer greater than 2 and is equal to the number of times the scanning means reads out the data register in each second cycle of channel intervals 2. A device as claimed in claim 1, wherein the logic means comprises a second comparator means for providing a second control signal in response to a condition wherein the stored scanned information is identical to the succeeding stored scanned information, a first logic gate responsive to a coincidence between the first control signal and the absence of a blocking signal for transferring the stored scanned information to the second channel, and a second logic gate means for pro.- viding the blocking signal for the duration of the next succeeding stored scanned information in response to the transfer of the stored scanned information and for providing a blocking signal for the duration of the next two succeeding information signals in response to a coincidence between the second control signal and a transfer of the stored scanned information.

Claims

1. A device for transferring information from a first channel in the form of a first cycle of channel intervals to a second channel in the form of a second cycle of channel intervals where the nominal duration of the first cycle of channel intervals is equal to the nominal duration of the second cycle of channel intervals, comprising a data register, synchronization means connected to the first channel for sequentially providing the information of the first channel to the data register in channel intervals of the second cycle shifted within the second cycle of channel intervals by an amount corresponding to the phase shift between the first cycle of channel intervals and the second cycle of channel intervals, scanning means for non-destructively reading out the data register at least three times in each second cycle of channel intervals thereby forming multiple information words, means for sequentially storing the scanned information, comparator means for providing a control signal in response to a condition wherein the stored scanned information is identical to the preceding stored scanned information, and logic means responsive to the control signal for transferring the stored scanned information into the second channel one time in response to at most (n + 1) successive control signals where n is an integer greater than 2 and is equal to the number of times the scanning means reads out the data register in each second cycle of channel intervals.

2. A device as claimed in claim 1, wherein the logic means comprises a second comparator means for providing a second control signal in response to a condition wherein the stored scanned information is identical to the succeeding stored scanned information, a first logic gate responsive to a coincidence between the first control signal and the absence of a blocking signal for transferring the stored scanned information to the second channel, and a second logic gate means for providing the blocking signal for the duration of the next succeeding stored scanned information in response to the transfer of the stored scanned information and for providing a blocking signal for the duration of the next two succeeding information signals in response to a coincidence between the second control signal and a transfer of the stored scanned information.