US3821494A - Digital echo suppressor with direct table look up control by delta coded signals - Google Patents

Digital echo suppressor with direct table look up control by delta coded signals Download PDF

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Publication number
US3821494A
US3821494A US00271960A US27196072A US3821494A US 3821494 A US3821494 A US 3821494A US 00271960 A US00271960 A US 00271960A US 27196072 A US27196072 A US 27196072A US 3821494 A US3821494 A US 3821494A
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control signals
channel
transmit
memory
suppressor
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US00271960A
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J Besseyre
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International Business Machines Corp
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International Business Machines Corp
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Priority to US00271960A priority Critical patent/US3821494A/en
Priority to FR7322364A priority patent/FR2193293B1/fr
Priority to JP48071401A priority patent/JPS5249286B2/ja
Priority to DE2332884A priority patent/DE2332884A1/de
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other

Definitions

  • TRANS" MISSION CHANNEL DETECTION 8 CONTROL LOGIC A MOD ENCODER TRANS- MISSION INHIBIT I as TRANS MISSION INHIBIT A MO ENCODER /TERM
  • FIG. 1 A first figure.
  • This invention relates to echo suppressors, and more particularly to echo suppressors having simplified control apparatus responsive to delta coded data signals.
  • echo is understood to mean the portion of an output of a system which is fed back and modulates the system input after a substantial time delay.
  • echo appears as a replica of the speech wave uttered by a talker but perceived by him on his receive channel at least 45 milliseconds later.
  • the points along a communications link where this feedback is thought to occur in a telephone system include the hybrid junctions ordinarily terminating full duplex four-wire telephone paths and the magnetic coupling of channels at some intermediate point along their extent.
  • echo interference is not believed to be a problem.
  • Such systems provide sufficient redundancy coding in their messages to enable early detection of any interference due to echos. This contrasts, however, to the situation involving parallel tone transmission and in bit oriented start-stop systems wherein echos look like any other type of line transition.
  • start-stop systems such as the printing telegraph
  • start-stop systems can be defined as systems in which a fixed time pattern is used for the group of symbols representing a character, but each group is preceded by a signal transition which serves as a symbol to denote where the fixed pattern is to start. Accordingly, to the extent that echo appears as transitions, then a start-stop system would interpret echos as valid characters.
  • Such start-stop systems may be manually operated with no automatic error detection built into them. To this extent, operator review of telegraph printer text may require retransmission over an already slow-speed system, thereby diminishing the data throughput drastically.
  • SUPPRESSION AND THE PRIOR ART Suppression means that the gain and the opened or closed circuit condition of the transmit and receive channels of a talker terminal may be selectively altered during all or some part of the talker time,
  • detectors measure the amplitude level on both the inbound and outbound path.
  • a relative magnitude difference signal and a timing circuit are used for operating the suppressors. It is observed that the problem of contention is not entirely resolved. Given the situation, at the near terminal where a received signal is detected to transmitting, then the transmit side of the near terminal will be suppressed. If the transmit side was first to transmit, then the received side would be suppressed. In these cases, the rule of action appears to be that the suppressors work in favor of the channel having the highest detected level or gain at any point in time and for a fixed time after the relative level shifts from one channel to another.
  • Moye shows a correlator and an adaptive filter for suppressing echos by computing an electrical signal which is equivalent to the echo, inverting the computed signal, and adding it to the signal being received.
  • May discloses a common control logic arrangement for controlling echo suppressors in a. plurality of duplex transmission lines. According to May, a suppressor situated. in a transmit channel would be activated only if the transmit line was idle and the receive line was not.
  • the signals on the transmit and receive channels are delta modulation encoded.
  • Sufficient inertia is introduced into the control system by forming memory addresses not from the delta modulation sequences directly, but from the variable count of the number of successive matched digits.
  • each channel is monitored by a sequence detector which increments or decrements a corresponding reversible counter if a predetermined succession of ones or zeros has been detected.
  • the contents of the reversible counters are real positive integers and together define discrete address locations in the memory. If the magnitude A of the transmit channel counter is greater than or equal to the magnitude A of the receive channel counter, then control signal is extracted from the memory at address AA which keeps the transmit channel conducting and diminishes the receive counter contents by a preset amount. Likewise, if A A then a control signal is extracted which energizes the suppressor thereby opening the transmit channel.
  • FIG. 1 represents a duplex channel in which both the near and far terminal include an echo suppressor having a delta modulation encoder, an inhibit gate in the transmit channel, a delta modulation encoder in the receive channel, and detection and control logic.
  • FIG. 2 sets forth a logic level diagram of the invention emphasizing the detection and control logic, and the delta modulation encoder.
  • FIG. 3 sets forth the compositional arrangement of FIGS. 3A, B, and C.
  • FIGS. 3A, B, and C depict the contents of the memory in which the control signals are stored in selected memory locations whose addresses are defined by the respective transmit and receive channel counters.
  • An analog signal appearing at terminal A would be impressed on channel I and converted into a sequence of digital signals by delta modulation encoder 7.
  • the digital signal sequence is then transmitted through normally conducting transmission inhibit gate 9 over transmission channel 11.
  • the signal is reconverted into an analog varying signal by delta modulation decoder 13.
  • the analog signal is applied to terminal B and may be received by element 19 through transformer coupling over primary and secondary turns 15 and 17.
  • Data originating at terminal B destined for terminal A would in its turn be converted into digital sequences by delta modulation encoder 23 and transmitted through normally conducting inhibit gate 25 over the transmission channel 27.
  • the digital signal would be reconverted into an analog varying signal by delta modulation encoder 29.
  • the channel equipment between the two terminals might be housed in one of several repeaters strung along a communication link. Instead of being exclusively for digital data transmission at the terminal, the invention at the repeaters would require analog to digital conversion means for operating echo suppression, with digital to analog reconversion means to propagate the signals further down the line.
  • a time varying signal applied, for example, to delta modulation encoders 7 would be represented at the encoder output by a series of ones and zeros.
  • a time varying signal is presented to the delta modulation encoder.
  • the output digital sequence is transmitted upon both to the transmission channel and to the detection and control logic.
  • the detection and control logic by monitoring the bit streams in each channel continuously, can directly measure the amplitude or gain of the system.
  • a digital delta modulation encoded bit stream represents an instant numerical measure of the amplitude time rate of change of a corresponding analog signal.
  • control logic will generate on a one to one basis, a control signal on path 39 for operating transmission inhibit gate 9 for each gain magnitude measured on the respective channels. Consequently, for continuous serial input to logic 37 over paths 33 and 35, there will result a continuous serial output of control signals on line 39 to gate 9.
  • the same principles of operation apply to the serial digital inputs on paths 41 and 43 applied to logic 45 for developing a serial control signal output over path 47 to inhibit gate 25.
  • the arrows indicate the direction of communications. At each of the terminals, to the extent that there is an imperfect matching of the terminal impedance Z with the characteristic line impedance Z then a portion of the energy in a receive channel will be fed back into the corresponding transmit channel.
  • FIG. 2 there is shown a logic diagram of the embodiment disclosed in FIG. 1.
  • an amplitude varying signal at terminal A is impressed on the primary winding 3 and induced across the secondary winding 5.
  • Such a signal will be presented at the input of the comparator circuit 70 of delta modulation encoder 7.
  • the modulation encoder can preferably be of the double integrator type such as that, for example, described by P. F. Panter in Modulation, Noise, and Spectral Analysis McGraw Hill Book Co., New York, 1965, at pages 679-699.
  • comparator 70 and digitizer 72 generate a first or second digital signal at a rate determined by clocking means 2 as distributed to various circuits over path 4.
  • a binary l is generated, if at the clocking or sampling time, the instantaneous magnitude appearing on path 91 exceeds the reference magnitude output from double integrator 76.
  • digitizer 72 produces a binary 0 upon the occurrence of the clocking interval if the magnitude upon path 91 is equal to or less than the reference value of the integrator 76 output.
  • the successive ones and zeros generated by digitizer 72 are simultaneously applied to transmission channel 11 and the transmit sequence detector 74.
  • the sequence detector can be formed from a shift register and associated logic. The detector produces a signal on path 78 when four binary ones have been detected in sequence.
  • a signal is impressed on path 80 when four zeros have been detected in sequence. Successive digits are shifted out to double integrator 76 from the sequence detector 74 over path 75.
  • Weston shows the use of a counter at the delta modulator encoder output followed by two stages of integration in the feedback loop to the comparator.
  • the output of delta modulation encoder 7 on path 11 is applied to inhibit gate 9.
  • the inhibit gate is depicted as a NAND gate if a signal is present on channel 11 and inhibit path 39, then there is no output from the NAND gate.
  • the delta modulation decoder 29 has applied to it a series of digital delta modulation encoded pulses originated from terminal B.
  • the decoder 29 is simply an integrating type device which converts the digital sequence back into an amplitude varying waveform.
  • the digital sequence on the receive channel is applied also to receive sequence detector 20.
  • This sequence detector includes a shift register and associated logic for generating a signal on'line 22 upon the detection of four ones in succession. Also, a signal will be impressed on line 24 upon four zeros being detected in succession.
  • the heart of the. control of the system comprises a read-only memory 6 and up/down counters 8 and 34.
  • each occurrence of a predetermined number of successive matched digits as, for example, either four ones or four zeros is used to correspondingly increment or decrement an up/down counter which serves also as the memory address register.
  • sequence detector 74 senses four ones in succession, then counter 8 is incremented by a predetermined amount. Similarly, when detector 74 senses four zeros in succession, counter 8 is decremented by a predetermined amount.
  • the counter states constitute a memory address register A A A,-,. These are shown applied to read-only memory 6 and constitute path 35.
  • sequence detector 20 increments or decrements counter 34 upon the detection of four ones or zeros in succession in receive channel II.
  • the stages of counter 34 A',,, A A A' form another portion of the memory address register and are directly applied as such to read-only memory 6 over path 33.
  • clocking means 2 conditions appropriate gating circuits 82 and 84 and 26 and 28 to enable the signal from the respective detectors 74 and 20 to be applied to the respective counters 8 and 34.
  • an overflow or an underflow protection is needed in order to avoid a maximum gain from jumping to a minimum gain and from disturbing the echo suppressor behavior.
  • up/down counter 8 consisted of four states. If four ones were stored therein, then the outputs of AND gates 60, 62, 64, and 66 would all be one, while the corresponding overflow and underflow outputs on paths 86 and 18 from NAND gates 10 and 12 would each be zero thereby deactivating gates 82 and 84.
  • the rule of action of suppressors is that they work in favor of that channel having the highest detected level or gain at any point in time.
  • the contents of the respective counters represent a digital measure of the rate of change of the corresponding analog signal. Consequently, a succession of ones represents an increasing magnitude or gain while a succession of zeros represents a decrease of magnitude or gain.
  • the contents of each counter then serves two purposes. First, as a designation of a memory address and second, as an indication of relative magnitude difference.
  • the inhibit gate 9 is not activated and the gain of the receive channel is reduced. In this case, this is instrumented by having the memory output shift the contents of counter 34 shifted in a direction so as to diminish magnitude A. If the magnitude A of counter 34 exceeds the magnitude A of counter 8, then the inhibit gate 9 is activated by a signal from the read-only memory 6 over path 39.
  • FIG. 3 there is shown a sketch suggesting the arrangement for the FIGS. 3A, 3B, and 3C.
  • the contents of the control signal at various addresses defined by the counter 8 and 34 contents.
  • the memory content is one. More particularly, each address is defined by eight bits A A A A In all, there are two 2 memory locations.
  • the control signal one stored in the addresses for purposes of this discussion is defined as the signal that disables the inhibit gate and shifts counter34 to the right. For purposes of consistency, if one compares the magnitude of the binary number A A A A A with the magnitude of the binary number A A' A it will be apparent in each case that the first number is equal to or greater than the second number.
  • the read-only memory 6 can consist of, for example, a diode matrix, a magnetic core memory, or any other suitable alterable storage. If alterable storage means are used, then the threshold or suppressor action can be changed at will. Indeed, there may be regions where it may be desired to suppress in contradistinction to other regions of amplitude.
  • any analog to digital and digital to analog conversion technique can be used.
  • delta modulation was shown to illustrate the principle of the invention and avoid equipment complexity.
  • Analog signal functions are usually continuous and analytic, see for example the description of analytic functions by R. V. Churchill, in Introduction to Complex Variables, McGraw Hill Book Co., New York, 1948, pages 18-36. Restated, such functions do not usually exhibit abrupt discontinuities which means that there is a high probability of following them within minimum error with the equivalent of a discrete counting device. It should thus be feasible to convert analog signals into successive PCM samples and measure rates of change. In such PCM systems, a difference exceeding a predetermined amount would be equivalent to a match of successive digits in the delta mod scheme and call for the incrementing or decrementing of a counter corresponding to the direction of change. From that point, the operation of the system should be substantially the same.
  • suppressor means in the transmit channel operatively responsive to control signals
  • a reversible counting means comprises a transmit channel counter and a receive channel counter; the incrementing/decrementing means includes means respectively responsive to successive digital sequences from the transmit and receive channels for detecting a predetermined succession of matched digits of a first kind or of a second kind, and for incrementing the corresponding counter each time the predetermined succession of digits of the first kind is detected, and for decrementing the corresponding counter each time the predetermined succession of matched digits of the second kind is detected.
  • suppressor means in the transmit channel operatively responsive to control signals of a first and a second kind
  • memory means having control signals of a first or second kind stored at discrete memory locations having addressing coordinates AA, those locations having address coordinates A 2 A storing the control signal of the first kind, while those locations having address coordinates A A storing control signals of the second kind;

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
US00271960A 1972-07-14 1972-07-14 Digital echo suppressor with direct table look up control by delta coded signals Expired - Lifetime US3821494A (en)

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US00271960A US3821494A (en) 1972-07-14 1972-07-14 Digital echo suppressor with direct table look up control by delta coded signals
FR7322364A FR2193293B1 (enrdf_load_html_response) 1972-07-14 1973-06-13
JP48071401A JPS5249286B2 (enrdf_load_html_response) 1972-07-14 1973-06-26
DE2332884A DE2332884A1 (de) 1972-07-14 1973-06-28 Nachrichtenuebertragungsanlage mit digitaler echosperre

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US00271960A US3821494A (en) 1972-07-14 1972-07-14 Digital echo suppressor with direct table look up control by delta coded signals

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JP (1) JPS5249286B2 (enrdf_load_html_response)
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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906172A (en) * 1974-04-22 1975-09-16 Gen Electric Digital echo suppressor
US3937907A (en) * 1974-06-13 1976-02-10 Communications Satellite Corporation Digital echo suppressor
US3975588A (en) * 1973-12-21 1976-08-17 International Business Machines Corporation Acoustic feedback control
US4005276A (en) * 1975-03-20 1977-01-25 International Business Machines Corporation Digital voice signaling with digital echo detection and voice activity compression used to cancel echo
US4017695A (en) * 1974-09-30 1977-04-12 Bell Telephone Laboratories, Incorporated Customer operated gain control circuit
US4117277A (en) * 1976-06-28 1978-09-26 U.S. Philips Corporation Arrangement for simultaneous two-way data transmission over two-wire circuits
DE2821536A1 (de) * 1977-05-18 1978-11-23 Fujitsu Ltd Anordnung zum verhindern eines pfeifens
US4237463A (en) * 1977-10-24 1980-12-02 A/S Elektrisk Bureau Directional coupler
US4293038A (en) * 1979-05-24 1981-10-06 Baker International Corporation Ball valve assembly
US4314105A (en) * 1977-01-21 1982-02-02 Mozer Forrest Shrago Delta modulation method and system for signal compression
US4464746A (en) * 1981-02-11 1984-08-07 U.S. Philips Corporation Arrangement for correcting pulse distortion in homochronous data transmission
US4609788A (en) * 1983-03-01 1986-09-02 Racal Data Communications Inc. Digital voice transmission having improved echo suppression
US4611342A (en) * 1983-03-01 1986-09-09 Racal Data Communications Inc. Digital voice compression having a digitally controlled AGC circuit and means for including the true gain in the compressed data
US4648132A (en) * 1982-07-19 1987-03-03 Hitachi, Ltd. Communication control apparatus
US4652703A (en) * 1983-03-01 1987-03-24 Racal Data Communications Inc. Digital voice transmission having improved echo suppression
US4748665A (en) * 1985-07-01 1988-05-31 Rockwell International Corporation Analog echo suppressor
US5022074A (en) * 1985-07-01 1991-06-04 Rockwell International Corporation Digital echo suppressor
US5563944A (en) * 1992-12-28 1996-10-08 Nec Corporation Echo canceller with adaptive suppression of residual echo level
US20050270184A1 (en) * 2004-06-04 2005-12-08 Texas Instruments Incorporated Tri-value decoder circuit and method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3562448A (en) * 1968-06-21 1971-02-09 Bell Telephone Labor Inc Common control digital echo suppression

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3975588A (en) * 1973-12-21 1976-08-17 International Business Machines Corporation Acoustic feedback control
US3906172A (en) * 1974-04-22 1975-09-16 Gen Electric Digital echo suppressor
US3937907A (en) * 1974-06-13 1976-02-10 Communications Satellite Corporation Digital echo suppressor
US4017695A (en) * 1974-09-30 1977-04-12 Bell Telephone Laboratories, Incorporated Customer operated gain control circuit
US4005276A (en) * 1975-03-20 1977-01-25 International Business Machines Corporation Digital voice signaling with digital echo detection and voice activity compression used to cancel echo
US4117277A (en) * 1976-06-28 1978-09-26 U.S. Philips Corporation Arrangement for simultaneous two-way data transmission over two-wire circuits
US4314105A (en) * 1977-01-21 1982-02-02 Mozer Forrest Shrago Delta modulation method and system for signal compression
DE2821536A1 (de) * 1977-05-18 1978-11-23 Fujitsu Ltd Anordnung zum verhindern eines pfeifens
FR2391603A1 (fr) * 1977-05-18 1978-12-15 Fujitsu Ltd Dispositif d'elimination de sifflement par amorcage
US4175218A (en) * 1977-05-18 1979-11-20 Fujitsu Limited Telephone switching system
US4237463A (en) * 1977-10-24 1980-12-02 A/S Elektrisk Bureau Directional coupler
US4293038A (en) * 1979-05-24 1981-10-06 Baker International Corporation Ball valve assembly
US4464746A (en) * 1981-02-11 1984-08-07 U.S. Philips Corporation Arrangement for correcting pulse distortion in homochronous data transmission
US4648132A (en) * 1982-07-19 1987-03-03 Hitachi, Ltd. Communication control apparatus
US4609788A (en) * 1983-03-01 1986-09-02 Racal Data Communications Inc. Digital voice transmission having improved echo suppression
US4611342A (en) * 1983-03-01 1986-09-09 Racal Data Communications Inc. Digital voice compression having a digitally controlled AGC circuit and means for including the true gain in the compressed data
US4652703A (en) * 1983-03-01 1987-03-24 Racal Data Communications Inc. Digital voice transmission having improved echo suppression
US4748665A (en) * 1985-07-01 1988-05-31 Rockwell International Corporation Analog echo suppressor
US5022074A (en) * 1985-07-01 1991-06-04 Rockwell International Corporation Digital echo suppressor
US5563944A (en) * 1992-12-28 1996-10-08 Nec Corporation Echo canceller with adaptive suppression of residual echo level
US20050270184A1 (en) * 2004-06-04 2005-12-08 Texas Instruments Incorporated Tri-value decoder circuit and method
US7098833B2 (en) * 2004-06-04 2006-08-29 Texas Instruments Incorporated Tri-value decoder circuit and method

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Publication number Publication date
JPS5249286B2 (enrdf_load_html_response) 1977-12-16
DE2332884A1 (de) 1974-01-24
JPS4953317A (enrdf_load_html_response) 1974-05-23
FR2193293B1 (enrdf_load_html_response) 1977-09-23
FR2193293A1 (enrdf_load_html_response) 1974-02-15

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