US3820007A - Monolithic integrated voltage stabilizer circuit with tapped diode string - Google Patents

Abstract

This relates to a monolithic integrated voltage stabilizing circuit containing a stabilizing chain of series connected diodes at the connection points of which several stabilized voltages are tapped. All stabilized voltages below the momentary value of the supply voltage are always present. Additional constant current source transistors form a multi-collector lateral pnp transistor.

Description

United States Patent [191 Schilling et al.

[ MONOLITHIC INTEGRATED VOLTAGE STABILIZER CIRCUIT WITH TAPPED DIODE STRING [75] Inventors: Harald Schilling; Wolfgang Hoehn,

both of Freiburg, Germany [73] Assignce: ITT Industries Inc., New York,

[22] Filed: July 9, 1973 [21 1 Appl. No.: 377,477

[52] US. Cl 323/8, 307/297, 317/23 SD, 323/22 Z, 323/25 [51] Int. Cl. G05f 3/14 [58] Field of Search 307/297, 318; 323/1, 8, 323/22 T, 22 Z, 23, 25; 317/23 SD [56] References Cited UNITED STATES PATENTS 3,237,078 2/1966 Mallory 323/22 T June 25, 1974 3,648,153 3/1972 Grzlf 307/297 X 3,742,338 6/1973 Sugano ct a1 323/22 T OTHER PUBLICATIONS Electronies-Multi-Emittcr lCs Stabilize Voltages in Solid State Turners by Eckstein et al., pp. 91-93 Dec. 8, 1969.

Primary ExaminerGerald Goldberg Attorney, Agent, or Firm.lohn T. OHalloran; Menotti J. Lombardi, Jr.; Vincent lngrassia [5 7] ABSTRACT This relates to a monolithic integrated voltage stabilizing circuit containing a stabilizing chain of series connected diodes at the connection points of which sev eral stabilized voltages are tapped. All stabilized voltages below the momentary value of the supply voltage are always present. Additional constant current source transistors form a multi-collector lateral pnp transistor.

5 Claims, 6 Drawing Figures mrzmenwnes 191-1 3,820,007

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MONOLITHIC INTEGRATED VOLTAGE STABILIZER CIRCUIT WITH TAPPED DIODE STRING BACKGROUND OF THE INVENTION This invention relates to a monolithic integrated voltage stabilizing circuit from which several stabilized voltages can be tapped, and more particularly to a voltage stabilizing circuit wherein all stabilized voltages below the momentary value of the supply voltage are always present.

The present invention starts from a monolithic integrated voltage stabilizing circuit which is contained as a subcircuit in the commercially available series regulating circuit CA 3085. The internal circuit of this component is shown, for example, in the Linear Integrated Circuit D.A.T.A.-Book, 7th Edition, Spring 1972, N.J., 1971, of Derivation and Tabulation Associates Inc., on p. 121 in FIG. F 088. In this circuit diagram, the circuit portion serving as the starting point for the invention is shown on the left.

Known stabilizing circuits have the disadvantage that the stabilization of the voltages which can be tapped does not set in until the supply voltage is slightly higher than the highest voltage to be stabilized. It is frequently necessary that the lowest voltage to be stabilized set in as early as possible after the supply voltage is turned on, to immediately render basic functions of the integrated circuit operational. The voltage stabilizing circuit of the above kind has another disadvantage in that short-time drops in supply voltage such as frequently occur, for example, in onboard supplies of vehicles and aircraft may put the stabilizing function of the series connection out of operation, whereby all voltages to be stabilized fail.

SUMMARY OF THE INVENTION It is therefore the object of the present invention to provide a voltage stabilizing circuit of the above referred to kind wherein the voltages to be stabilized by means of the series connection remain stabilized as long as the respective supply voltage lies' above the value to be stabilized. In other words, the invention has for its object to provide a voltage stabilizing circuit in which all those voltages to be stabilized are still present which, when the supply voltage drops, lie below the reduced value.

According to a broad aspect of the invention, there is provided a monolithic integrated voltage stabilizing circuit comprising: a source of supply voltage; a plurality of series connected reference elements having tapping points from which stabilized voltages can be tapped; a first resistor; a first npn transistor having a base connected to the tapping point of the lowest voltage to be stabilized and having an emitter coupled via said first resistor to ground; a first pnp diode connected transistor having an emitter coupled to said source of supply voltage and having a base and collector coupled together and to the collector of said first npn transistor; a starting resistor coupled between the tapping of the lowest voltage to be stabilized and said source of supply voltage; a second pnp transistor having an emitter coupled to said source of supply voltage, a base coupled to the base of said first pnp transistor and a collector coupled to the base of said npn transistor via said plurality of series connected reference elements; and a plurality of additional pnp transistors (T T each having emitters coupled to said source of supply voltage, each having bases coupled together and to the base of said second pnp transistor and each of said plurality having a collector coupled to one of said tapping points of said series connected reference elements.

Using this arrangement each voltage to be stabilized is maintained as long as the supply voltage does not drop below the value to be stabilized. This has the advantage that, in the integrated circuit fitted with the circuit according to the invention, existing memory functions, for example, remain undisturbed as long as the supply voltage does not drop below the lowest voltage to be stabilized.

The voltage stabilizing circuit acording to the invention can be advantageously realized by designing all pnp transistors as a single multicollector lateral transistor. This lateral transistor is advantageously designed so that the emitter region is strip-shaped and located in the center of the base region, that the individual collector regions are located along the circumference of, and opposite to, the emitter region, and that the collector region connected to the tap of the lowest voltage to be stabilized additionally encloses the other collector regions in the form of a closed frame.

However, as will be explained in detail below, the single lateral transistor also may advantageously be designed so that the emitter region is strip-shaped and located in the center of the base region, that the collector regions of the first pnp transistor, of the second pnp transistor, and of the pnp transistor associated with the tap of the lowest voltage to be stabilized are arranged along the circumference of, and opposite to, the emitter region, that the collector region connected to the second-highest voltage to be stabilized lies opposite to the collector region of the second pnp transistor without lying opposite to the emitter region, that the collector region connected to the third-highest voltage to be stabilized lies opposite to the collector region connected to the second-highest voltage to be stabilized without lying opposite to the emitter region, etc., up to the collector region connected to the second-lowest voltage to be stabilized, and that the collector region connected to the lowest voltage to be stabilized additionally encloses the other collector regions in the form of a closed frame.

Both of the above preferred embodiments of the lateral transistor are particularly well suited for the purpose stated if the collector regions edge portions lying opposite to the emitter region are equally long.

The above objects and features will be better understood from the following detailed description taken in conjunction with the accompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the essential parts of a voltage stabilizing circuit according to the prior art;

FIG. 2 shows the voltage stabilizing circuit according to the invention in its general form;

FIG. 3 shows the voltage stabilizing circuit according to the invention for two voltages to be stabilized;

FIG. 4 shows one preferred embodiment of the arrangement of the individual regions of the pnp transistors;

FIG. 5 shows another preferred embodiment of the arrangement of the regions of the pnp transistors; and

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, the known stabilizing circuit consists of the reference element Z, whose voltage U represents the voltage to be stabilized. The current flowing through the reference element is essentially determined by the resistance value of the resistor R1, which is connected as the emitter resistor of the npn transistor T. Via the diode-connected pnp transistor T whose collector-emitter path connects the collector of the npn transistor T to the positive terminal of the supply-voltage source U and via the pnp transistor T whose baseemitter path is connected in parallel to the base-emitter path of the pnp transistor T it is ensured that a current equal to the collector current of the npn transistor T also flows via the collector of the pnp transistor T and thus through the reference element Z. The resistor R2, which connects the reference element to the positive terminal of the supply-voltage source, serves as a starting resistor to ensure, when the supplyvoltage source is turned on, that the stabilizing circuit assumes the stable state. As can be seen, the stabilizing circuit exhibits a bistable behavior, with an unstable state being the second of the bistable states. Instead of the starting resistor, it is also possible to provide for pulsed tum-on.

As can be seen, the known circuit principle shown in FIG. 1 makes use of the principle of a constant current source as shown in IEEE Journal of Solid-State Circuits," June 1969, p. 114, FIG. 8, through the two pnp transistors.

For the voltage supply of monolithic integrated circuit arrangements, the known circuit principle can be extended by using not only one single reference element but a series connection of several reference elements, whereby different stabilized voltages can be tapped from the respective junction points of the individual reference elements. Used as reference elements are, in known manner, diode-connected transistors operated either in the forward direction or in the reverse direction up to the breakdown region.

FIG. 2 shows the voltage stabilizing circuit according to the invention in its general form. The interconnection of the two pnp transistors T and T of the starting resistor R2, of the npn transistor T, and of the emitter resistor R1 is identical to that of FIG. 1, while the reference element 2 of FIG. 1 has been replaced by the series connection of the reference elements Z Z Z,, Z,, and Z The order of numbering of the components is chosen so that the reference element Z is connected to the collector of the second pnp transistor T while the last reference element Z, of the series connection is connected to ground.

From the series connection of these reference elements, as many stabilized voltages can be tapped as there are reference elements. In FIG. 2, these voltages are designated U U U,,,.,, the respective voltage as viewed from the collector of the second pnp transistor T being tapped ahead of the reference element of the same index.

According to the invention, for solving the problem underlying the invention and stated above, each tapping point of the series connection of the reference elements, i.e., each junction point of two adjacent reference elements, is connected via an additional pnp tran sistor to the positive terminal of the supply-voltage source U with the collector of this respective transistor connected to the respective tapping point, teh emitter connected to the supply-voltage source U and the base connected to the bases of the first and second pnp transistors T and T,, respectively. Thus, the baseemitter path of the respective additional pnp transistor is connected in parallel to the base-emitter paths of the first and second pnp transistors.

In detail, the junction point of the reference elements Z and Z has the collector of the additional pnp transistor T connected thereto, or, in other words, the collector of the additional pnp transistor, as viewed from the collector of the second pnp transistor T is connected ahead of the respective reference element of the same index.

Thus, the collector of the additional pnp transistor T,, is connected ahead of the reference elements Z,, i.e., to the junction point of this reference element with the reference element Z,, (not shown in FIG. 2). Accordingly, the last two additional pnp transistors T,, and T are connected to the junction points between the reference elements Z,, Z,, and Z,, Z respectively.

For the graphic representation of the reference elements Z 2,, in FIG. 2, the symbols for zener diodes and diodes were chosen to indicate that both types of components may be used to form the series connection of the reference elements. In this case, the diodes are forward-biased, and the zener diodes reversebiased. The reference elements Z Z are shown as forwardbiased diodes, while the reference elements Z,, Z, and Z,, are shown as zener diodes. However, this order is arbitrary, and any other order may be chosen, in which case, however, the last reference element 2,, should be a zener diode and not a forward-biased diode in order for the current in the resistor R1 to be better adjustable.

FIG. 3 shows the circuit arrangement derived from the general form of the inventive stabilizing circuit of FIG. 2 for two voltages U and U to be stabilized. In this case, the series connection consists of the two reference elements Z and Z for which the zener-diode symbols were chosen. Thus, the series connection of the reference elements has a single tapping point, from which the stabilized voltage U is tapped. According to the invention, this point is connected via the collectoremitter path of the additional pnp transistor T to the positive terminal of the supply-voltage source U The specific coupling of the other components of FIG. 3 is identical to that of FIG. 2.

While FIGS. 1 to 3 are circuit diagrams of the voltage stabilizing circuit according to the invention, FIGS. 4 to 6 show plan views of advantageous structures of the pnp transistors in the monolithic integrated circuit. Particularly advantageously, the pnp transistors are realized as a single lateral transistor with a suitable number of individual collectors.

The characteristics, structure, and operation of such lateral transistors are known from Proceedings of the IEEE, Dec. 1964, pp. 1491 to 1495. By a lateral transistor of a monolithic integrated circuit a transistor is understood whose current flowing from the emitter via the base to the collector flows substantially in parallel to the main surface of the integrated circuit, while, in contrast, the transistors commonly formed in monolithic integrated circuits having a collector-emitter current path vertical to this surface.

Such lateral transistors are particularly suitable for the realization of pnp transistors in monolithic integrated circuits which usually have npn transistors with the above-mentioned vertical current flow. To accomplish this, individual regions separated from each other by p-type material are first fabricated in the commonly n-type, mostly epitaxially grown region of the monolithic integrated circuit by so-called insulation diffusion.

These regions, separated from each other by pn junctions, can be used either for the construction of an npn transistor or for the construction of a lateral pnp transistor. In this case, the n-type region is active as the collector of the npn transistor or as the base of the lateral transistor. By diffusion of impurities producing p-type conductivity, which diffusion forms the base region in the npn transistor, the lateral transistors p-type regions for the emitter region and for the collector region are produced which are located at the semiconductor surface side by side and at a specified distance. According to the reference mentioned above, the location of the collector region may be chosen so that the collector region surrounds the emitter region as a geometrically closed configuration.

The use of several pnp transistors in an integrated circuit which are interconnected after the manner of a multiple constant current source is also known in the art, see IEEE Journal of Solid-State Circuits, Apr. 1972, pp. 105 to II 1, especially FIG. 9 on p. I07. This figure shows a strip-shaped emitter region which is surrounded by the individual collector regions.

Unlike this structure of a lateral transistor with several collectors, the lateral transistor for the realization of the stabilizing circuit according to the invention is designed so that, although, as shown in the different embodiments of FIGS. 4 to 6, individual collectors are arranged along, and opposite to, the likewise stripshaped emitter region E, one of these collector regions, namly the collector region C, of the additional pnp transistor T, connected to the lowest voltage U, to be stabilized, lies opposite to the emitter region E and encloses the other collector regions like a frame with the portion C,,.

The embodiment of the lateral transistor of FIG. 4 shows the insulating region I, which encloses the entire structure like a frame and is obtained by the insulation diffusion mentioned above. Located within this insulating region is the base region B, whose right edge is provided with the base contact B. The broken line indicates the extension of the so-called buried layer BL, which is located below the individual regions in the semiconductor body and, as is well-known, serves to reduce bulk resistances.

In the center of the base region, the strip-shaped emitter region E can be seen which is hatched toward the right and surrounded by the individual collector regions, hatched toward the left, so that, according to the current flowing through the individual collectors, a more or less small portion of the collector region lies opposite to the emitter region, because the edge length of that portion of the respective collector region which additional reference elements Z lies opposite to the emitter region determines the value of the current flowing through the collector.

In the embodiment of FIG. 4, the arrangement of the collector regions C C,, is arbitrary. For example, the collector region C of the first pnp transistor T is shaped like a U enclosing one end of the emitter region, while the collector region C, C,,.{ are also stripshaped and lie opposite to the emitter region.

In the embodiment of FIG. 4, the collector region C,,, which, with the portion C,,, encloses the other collector regions like a frame, has two portions lying opposite to the emitter region E and thus can take over current from this emitter region. However, this embodiment is not mandatory; it is also possible to provide this collector region with only one single portion lying opposite to the emitter region B.

As can be seen, the lateral transistor of FIG. 4 contains six individual collector regions. Thus, the collector region C,, is identical to the collector region C the collector region C,, to the collector region C and the collector region C, to the collector region C the reference characters being added in brackets.

The stabilizing circuit according to the invention as well as the embodiment of the lateral transistor of FIG. 4 operate as follows: When the supply voltage U drops below the value of one of the voltages to be stabilized, e.g., when the supply voltage drops below the value of the voltage U to be stabilized, the collector-emitter voltage of the associated first pnp transistor T collapses and, therefore, no current flows in the reference element 2,, but current is still fed to the remaining portion of the series connection of the reference elements via the additional pnp transistors T T,,, so that only the stabilized voltage U is no longer present. The above-mentioned collapse of the collector-emitter voltage of the second pnp transistor T corresponds to a mode of operation in which this transistor is saturated and in which the saturation current would flow off laterally via the insulating region to the substrate of the integrated circuit because of the blocking action of the buried layer unless the frame-shaped portion C,. of the collector region C took over the saturation current of the respective transistor. Here, the invention starts from he recognition that, through the above embodiment, the saturation current is again supplied at least to the reference element of the lowest voltage to be stabilized, which is accomplished by the collector(s) of the transistor(s) driven into saturation then acting as emitter for that portion of the frame C, which lies opposite to this collector now acting as emitter.

In'case of any further drop in the supply voltage U further voltages to be stabilized can thus fail one after another, but always only those will fail whose value is greater than that of the dropped supply voltage, while the other voltages are maintained.

In case of a drop in supply voltage, the failure of the current flowing in the no longer stabilizing reference elements naturally changes the total current in the series connection of the reference elements so that the Z,, with the exception of the reference element 2,, associated with the lowest voltage to be stabilized are traversed by different currents, while the current through the reference element 2,, remains constant. Particulafly in the forward-biased diodes, because of their characteristics, this results in a change in the stabilized voltage which may be disadvantageous depending on the stabilization quality required.

To avoid this disadvantage, the collector regions of the transistors T T,, are advantageously arranged as'shown in FIG. 5. Here, unlike in the arrangement of FIG. 4, only the collector region C of the first pnp transistor, the collector region C of the second pnp transistor, and the collector region C, of the transistor connected to the lowest voltage U to be stabilized lie opposite to the emitter region E. The other collector regions C C,, from the point of view of area, are connected in series in such a manner that, starting from the collector region C of the second transistor, they succeed one another in accordance with the respective index.

The collector region C of the second pnp transistor T and the collector region C of the first pnp transistor T are U-shaped and each enclose one end of the stripshaped emitter region E. The collector region C of the second pnp transistor is, in turn, enclosed by the U- shaped collector region C of the transistor T connected to the second-highest voltage U to be stabilized, with the U-shaped arrangement continuing up to the collector region C, of the transistor T,, connected to the second-lowest voltage U,,,., to be stabilized.

Compared with the embodiment of FIG. 4, that of FIG. has an additional collector region, namely the collector region C so that this lateral transistor has seven collector regions in accordance with seven voltages to be stabilized. Accordingly, the collector region C,, corresponds to the collector region C the collector region C,, to the collector region C and the collector region C to the collector region C the reference characters being added in brackets like in FIG. 4.

By the special arrangement of the individual collector regions as a series connection from the point of view of area, it is achieved that the saturation current which, in the arrangement of FIG. 4, immediately flows to the collector C,, in case of saturation is first taken over by the adjacent collector region because then the collector of the transistor driven into saturation, in turn, acts as the emitter. Through the suitable spatial series arrangement and because of the fact that, when the supply voltage U,, drops, the individual voltages to be stabilized automatically fail one after another and that the associated pnp transistors, too, are therefore driven into saturation one after another, the effect of the respective current takeover from one collector region on to the other, beginning at the collector region C continues up to the collector region C,,

Thus, however, no current is extracted from the series connection of the reference elements when the individual pnp transistors are driven into saturation, but the saturation current of the transistor driven into saturation again flows into the series connection via the collector region of the adjacent transistor. Thus, however, no changes in current occur within the series connection of the reference elements in case of failure of individual voltages to be stabilized, so that the still effective stabilized voltages are not subjected to any change by the failure of the other voltages.

Based upon the recognition mentioned above, the invention thus takes another step forward and extends the principle of the utilization of the saturation current, leaking off into the substrate without this measure, to

each of the pnp transistors except to the one having the frame-shaped portion.

Although in the embodiment of FIG. 5, the individual collector regions connected in series from the point of view of area are shown to enclose each other in the shape of a U, this embodiment is not mandatory. Another arrangement is conceivable in which, respectively, one collector region is arranged as a strip behind the other. It must only be insured that the subsequent collector regions do not lie opposite to the emitter region E directly but only via the respective preceding collector region.

The other details of the embodiment of FIG. 5 are the same as in FIG. 4, i.e., the embodiment of FIG. 5 also comprises the insulating region I, the base region E, the buried layer BL, and the base contact B.

FIG. 6 shows the arrangement to be derived from FIGS. 4 and 5 for the circuit of FIG. 3. In this case, it is insured from the outset that the collector region of the transistor connected to the lowest voltage U to be stabilized follows from the point of view of area as shown in FIG. 5, the collector region of the transistor associated with the highest voltage U to be stabilized. Otherwise, FIG. 6 corresponds to FIG. 5.

Particularly advantageous conditions are obtained if, in the embodiments of FIGS. 4 to 6, those edge por' tions of the respective collector regions which lie opposite to the emitter region are equally long because, in that case, equal currents flow in the individual transistors. These dimensions have been taken into account in FIG. 6, in which the edge lengths are drawn in accordance with this teaching, it being considered that, in the comer areas shown as broken lines, no injection to the respective collector region occurs, of course.

Although FIGS. 4 to 6 show the emitter region as a rectangular, narrow strip, this embodiment is by no means mandatory. The emitter region may, of course, also have the shape of a more or less curved strip or of a sharply bent line. The shape of the emitter region can thus be chosen according to the respective application and adapted to the integrated circuit area available for the lateral transistor.

It is to be understood that the foregoing description of specific examples of this invention is made by way of example only and is not to be considered as a limitation on its scope.

What is claimed is:

l. A monolithic integrated voltage stabilizing circuit comprising:

a source of supply voltage;

a plurality of series connected reference elements having tapping points from which stabilized voltages can be tapped;

a first resistor;

a first npn transistor having a base connected to the tapping point of the lowest voltage to be stabilized and having an emitter coupled via said first resistor v to ground;

a first pnp diode connected transistor having an emitter coupled to said source of supply voltage and having a base and collector coupled together and to the collector of said first npn transistor;

a starting resistor coupled between the tapping of the lowest voltage to be stabilized and said source of supply voltage;

a second pnp transistor having an emitter coupled to said source of supply voltage, a base coupled to the base of said first pnp transistor and a collector coupled to the base of said npn transistor via said plurality of series connected reference elements; and

a plurality of additional pnp transistors (T l T each having emitters coupled to said source of supply voltage, each having bases coupled together and to the base of said second pnp transistor and each of said plurality having a collector coupled to one of said tapping points of said series connected reference elements.

2. A stabilizing circuit according to claim 1 wherein all pnp transistors (T T are one single lateral transistor having several collectors (C C 3. A stabilizing circuit according to claim 2 wherein said lateral transistor is designed so that the emitter region (E) is strip-shaped and located in the center of the base region (B), and wherein the individual collector regions (C C are arranged along the circumference, over and opposite to, the emitter region, and wherein the collector region (C,,) connected to the tap of the lowest voltage to be stabilized encloses the other collector regions (C C,,.,).

4. A stabilizing circuit according to claim 2 wherein said lateral transistor has an emitter region (E) which is strip-shaped and located in the center of the base region (B), and wherein the collector regions (C,,, C C,,) of said first pnp transistor (T of said second pnp transistor (1",), and of the last of said plurality of additional pnp transistors (T,,) associated with the tap of the lowest voltage to be stabilized are arranged along the circumference, and opposite to, the emitter region, and wherein the collector region connected to the second highest voltage to be stabilized lies opposite to the collector region of said second pnp transistor (T without lying opposite to the emitter region, and wherein the collector region of the third from last of said plurality of additional pnp transistors (C,, is connected to the third highest voltage to be stabilized and lies opposite the collector region (C connected to the second highest voltage to be stabilized without lying opposite the emitter region, and wherein the collector region (C,,) connected to the lowest voltage to be stabilized additionally encloses the other collector regions in the form of a closed frame.

5. A stabilizing circuit according to claim 3 wherein the edge portions of all collector regions (C C which-lie opposite the emitter region (E) are of the same length.

UNETED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,820,007 Dated June 25, 1974 Inventor(s) 8'W. Hoehn It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

30 Add --,-Foreign Application Priority Date July 31, 1972 Germany 1? 22 37 559.3

Signed arid sealed this 8th day of October 1974.

(SEAL) Attest:

McCOY M. GIBSON JR. C. MARSHALL DANN Attesting Officer Commissioner of Patents USCOMM-DC 603164 69 FORM PC4050 (10-69) V Q u.s. oovuemazm ram'rmc on'rc: an o Hun-an UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent no; $820,007 Dated June 25, 1974 Inventor(s) i g-W. Hoehn It is certified that error appeats in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Add -Foreign Application Priority Date July 31, 1972 Germany 1? 22 37 559.3

Signed arid sealed this 8th day of October 1974,

(SEAL) Attest:

McCOY M. GIBSON JR. C. MARSHALL DANN Commissioner of Patents Attesting Officer 9 U.S. GO VUNNENT VRINTXNG OFFICE: I959 O 5*"1'33l DRM PO-I050 (10-59)

Claims (5)

1. A monolithic integrated voltage stabilizing circuit comprising: a source of supply voltage; a plurality of series connected reference elements having tapping points from which stabilized voltages can be tapped; a first resistor; a first npn transistor having a base connected to the tapping point of the lowest voltage to be stabilized and having an emitter coupled via said first resistor to ground; a first pnp diode connected transistor having an emitter coupled to said source of supply voltage and having a base and collector coupled together and to the collector of said first npn transistor; a starting resistor coupled between the tapping of the lowest voltage to be stabilized and said source of supply voltage; a second pnp transistor having an emitter coupled to said source of supply voltage, a base coupled to the base of said first pnp transistor and a collector coupled to the base of said npn transistor via said plurality of series connected reference elements; and a plurality of additional pnp transistors (T2 . . . Tn) each having emitters coupled to said source of supply voltage, each having bases coupled together and to the base of said second pnp transistor and each of said plurality having a collector coupled to one of said tapping points of said series connected reference elements.

2. A stabilizing circuit according to claim 1 wherein all pnp transistors (To . . . Tn) are one single lateral transistor having several collectors (Co . . . Cn).

3. A stabilizing circuit according to claim 2 wherein said lateral transistor is designed so that the emitter region (E) is strip-shaped and located in the center of the base region (B), and wherein the individual collector regions (Co . . . Cn) are arranged along the circumference, over and opposite to, the emitter region, and wherein the collector region (Cn) connected to the tap of the lowest voltage to be stabilized encloses the other collector regions (Co . . . Cn 1).

4. A stabilizing circuit according to claim 2 wherein said lateral transistor has an emitter region (E) which is strip-shaped and located in the center of the base region (B), and wherein the collector regions (Co, C1, Cn) of said first pnp transistor (To), of said second pnp transistor (T1), and of the last of said plurality of additional pnp transistors (Tn) associated with the tap of the lowest voltage to be stabilized are arranged along the circumference, and opposite to, the emitter region, and wherein the collector region connected to the second highest voltage to be stabilized lies opposite to the collector region of said second pnp transistor (T1) without lying opposite to the emitter region, and wherein the collector region of the third from last of said plurality of additional pnp transistors (Cn 2) is connected to the third highest voltage to be stabilized and lies opposite the collector region (C2) connected to the second highest voltage to be stabilized without lYing opposite the emitter region, and wherein the collector region (Cn) connected to the lowest voltage to be stabilized additionally encloses the other collector regions in the form of a closed frame.

5. A stabilizing circuit according to claim 3 wherein the edge portions of all collector regions (Co . . . Cn) which lie opposite the emitter region (E) are of the same length.

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