US3811615A

US3811615A - Recording device control system

Info

Publication number: US3811615A
Application number: US00340465A
Authority: US
Inventors: I Yamanaka; H Sato; Y Takeuchi
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp
Priority date: 1973-03-12
Filing date: 1973-03-12
Publication date: 1974-05-21
Anticipated expiration: 1991-05-21
Also published as: CA982276A

Abstract

A control system for ensuring proper operation of a recording device during the cycling thereof in the event of loss of operating voltages. The recording device is operable in a cycle having a recording preparation phase and a recording phase. The recording phase occurs after the completion of the recording preparation phase and a recording means actuating means, when operated during such recording phase, causes a recording or nonrecording operation which is determined by operation, or not, of a recording control means after completion of such recording preparation phase. The recording device is connected to a power source which has power supply means connected thereto. The control system comprises first detecting means coupled to the power source which is responsive to a voltage failure condition and second detecting means coupled to the power supply means which is responsive to removal of such voltage failure condition. The control system further includes first timing means for developing a first timing signal occurring during the recording preparation phase and second timing means for developing a second timing signal occurring during the recording phase. The control system is further provided with circuit control means coupled to the first and second detecting means and the first and second timing means which is operable to inhibit operation of the recording control means upon occurrence of a voltage failure condition at the power source during the recording preparation phase or upon removal of such voltage failure condition so that the recording means actuating means when operated during the recording phase will effect a non-recording operation. The control system is also operable to cause operation of the recording control means upon lack of a voltage failure condition at the power source or upon the occurrence of a voltage failure condition at the power source during or after initiation of the recording phase so that the recording means actuating means when operated will effect a recording operation.

Description

United States Patent 1 1 Yamanaka et al.

[111 3,811,615 1 May 21, 1974 1 RECORDING DEVICE CONTROL SYSTEM [75] Inventors: lzumi Yamanaka, Hiratsuka;

Hironobu Sato, lsehara; Yoshihiro Takeuchi, Fujiwawa, all of Japan [73] Assignee: The National Cash Register Company, Dayton, Ohio [22] Filed: Mar. 12, 1973 [21] Appl. No.: 340,465

[52] US. Cl. 235/58 P, 235/2, 235/60 P, 101/93 C [51] Int. Cl. B41j 9/38, G06c 11/04 [58] Field of Search 235/58 P, 60 P, 2, 4, 60.25, 235/62 F; 340/253 C, 256; 101/93 C; 317/31 [56] References Cited UNITED STATES PATENTS 3,575,107 4/1971 McDowell et a1 lOl/93 C 3,673,955. 7/1972 Curtiss et a1 101/93 C 3,742,844 7/1973 Arciprete et al.... p 101/93 C Primary Examiner-Stephen J. Tomsky Attorney, Agent, or Firm-J. T. Cavender; Wilbert Hawk, Jr.; John J. Callaham 57 ABSTRACT A control system for ensuring proper operation of a I recording device during the cycling thereof in the when operated during such recording phase, causes a recording or non-recording operation which is determined by operation, or not, of a recording control means after completion of such recording preparation phase. The recording device is connected to a power source which has power supply means connected thereto. The control system comprises first detecting means coupled to the power source which is responsive to a voltage failure condition and second detecting means coupled to the power supply means which is responsive to removal of such voltage failure condition. The control system further includes first timing means for developing a first timing signal occurring during the recording preparation phase and second timing means for developing a second timing. signal occurring during the recording phase. The control system is further provided with circuit control means coupled to the first and second detecting means and the first and second timing means which is operable to inhibit operation of the recording'control means upon occurrence of a voltage failure condition at the power source during the recording preparation phase or upon removal of such voltage failure condition so that the recording means actuating means when operated during the recording phase will effect a non-recording operation. The control system is also operable to cause operation o'f-the recording control means upon lack of a voltage failure condition at the power source or upon the occurrence of a voltage failure condition at the power source during or after initiation of the recording phase so that the recording means actuating means when operated will effect a recording operation.

12 Claims, 17 Drawing Figures PATENTEUMY 2 1 W saw 06 0F 10 wmwnmelw 3,811,615

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0mm 0mm OOm 08 com 0am mmm 12m 0 mmmmwm 822 1 RECORDING DEVICE CONTROL SYSTEM SUMMARY OF THE INVENTION cludes a recording or printing means having a hammer means and a rotatable typewheel carrying a plurality of indicia. The printer device also includes a recording or printing preparation means comprising a typewheel setting means for setting the typewheel so that a selected indicium is in operative association with the hammer means in order to effect a desired printing operation. The printer device further includes a recording or printing means actuating means for operating the printing means (more specifically, the hammer means) and a recording or printing control means for controlling the operation of the printing means actuating means.

The printer device is operable in a cycle having at least two phases. One of the phases is defined as a recording or printing preparation phase during which the typewheel is set by the typewheel setting means, and the other of the phases is defined as a recording or printing phase occurring after the completion of the printing preparation phase and during which a printing or non-printing operation occurs. The printing means actuating means, when operated during the printing phase causes a printing or non-printing operation of the hammer means as determined by operation or not of the printing control means during the printing phase.

The printer device is coupled to a power source, that is, an AC. (alternating current) line voltage which, in turn, supplies D.C. (direct current) voltage to DC. voltage regulation circuits. The power source supplies an operating voltage for a motor means which operates mechanical portions of the typewheel setting means and the printing means actuating means. The DC. voltage regulation circuits supply operating voltages for various electronic circuits of the printer device, for example, electronic circuits of the typewheel setting means.

It will be appreciated that if a power failure condition (loss of operating voltages) occurs prior to completion of the printing preparation phase of the printer device cycle of operation that the typewheel will ordinarily be erroneously set. Accordingly, it is desirable to ensure that incorrect printing, occasioned by such loss of operating voltages, does not occur during the printing phase of such cycle of operation when, for one reason or another, there has been a removal of such voltage failure condition. On the other hand, should a voltage failure condition occur after the completion of the printing preparation phase of the cycle with the typewheel having already been correctly set, it is advantageous to effect a printing operation upon a subsequent removal of such voltage failure condition during the printing phase of the printer device cycle of operation.

It is therefore the primary object of the invention to provide a control system for preventing improper operation of a recording device during the cycling thereof in the event of loss of operating voltages.

It is a further object of this invention to provide a control system for a recording device operable in a cycle having a recording preparation phase and a recording phase, that is responsive to a voltage failure condition occuring during the recording preparation phase to cause the recording device to effect a nonrecording operation upon subsequent removal of such voltage failure condition.

It is another object of this invention to provide a control system for a recording device of the above type, that is responsive to a voltage failure condition occurring after the completion of the recording preparation phase to enable the recording device to effect a recording operation upon subsequent removal of such voltage failure condition.

In its broadest aspect, the invention comprises a control system for a recording device operable in a cycle having at least a recording preparation phase and a recording phase, which system includes a first detecting means coupled to a power source which is responsive to a voltage failure condition. A first timing means is provided for developing a first timing signal which occurs during the recording preparation phase. And, circuit control means is provided which is coupled to both the first detecting means and the first timing means and is operable to inhibit operation of a recording control means upon occurrence of a voltage failure condition at the power source so that a recording means actuating means when operated will effect a non-recording operation.

The control system of this invention further comprises a second detecting means coupled to the power supply which is responsive to removal of a voltage failure condition occurring during the recording preparation phase, and the circuit control means is coupled to the second detecting means and is operable to inhibit operation of the recording control means upon removal of such voltage failure condition so that the recording means actuating means when operated will effect a non-recording operation. The second detecting means is also responsive to a voltage failure condition occurring after the initiation of the recording phase, and the circuit control means is operable to enable operation of the recording control means so that the recording means actuating means when operated will effect a recording operation.

The control system of this invention still further comprises a second timing means for developing a second timing signal occurring when the recording phase is initiated. The second timing means is coupled tothe circuit control means which is operable to cause operation of the recording control means upon lack of a voltage failure condition at the power source during the recording preparation and recording phases, or upon the occurrence of a voltage failure condition at the power source after initiation of the recording phase, so that the recording means actuating means when operated will effect a recording operation. 7

' The novel features of this invention, as well as the invention itself, both as to its organization and method of operation, will best be understood from the accompanying description taken in conjunction with the accompanying drawings in which like characters refer to like parts, and in which:

FIGS. 1A and 13 comprise a schematic block and circuit diagram showing the recording device control FIG. 5 is a circuit diagram of the energizing circuits for solenoids included in the recording control means of FIG. 1B;

FIG. 6 is a schematic block diagram of the signal generator of FIG. 1A;

FIG. 7 is a side view of the preferred recording device with which the control system of the present invention is associated, includingthe'recording control means, the recording means actuating means, and the recording means of FIG. 1B; I

FIG. 8 is a side view showing a portion of the recording means actuating detail;

FIG. 9 is a side view showing a portion of the recording control means of FIGS. 18 and 7 in more detail;

FIG. 10 is a perspective view of the general construction of the recording preparation means (typewheel setting means) of FIG. 1B;

FIGS. 11, 12 and 13 are detail views showing various operating positions of transmission segments employed in the recording preparation means of FIG. 10;

FIG. 14 is a side view showing a further portion of the recording preparation means of FIG. 18;

FIG. 15 is a timing diagram showing signals generated or occurring at each angular position of the rotatable drive shaft of the recording device, along with positions of certain parts of the recording device at those angular positions; and

FIG. 16 is a timing diagram showing signals occurring when a power failure condition occurs at the time the drive shaft of the recording device has rotated 5, when the removal of such power failure condition occurs at the time the drive shaft of the recording device has rotated 145, and when a power failure condition occurs at the time the drive shaft of the recording device as rotated 195.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring first to FIGS. 1A and 1B, a recording or printing device in which the control system in accordance with this invention may be utilized includes a recording means 10 (FIG. 1B) which may comprise a rotatable typewheel carrying a plurality of indicia and an associated hammer means. Associated with the recording means 10 is a recording preparation means or typewheel setting means ll for the purpose of setting the typewheel so that a selected indicium is in operative association with the hammer means. Accordingly, the hammer means, when operated will cause the selected indicium to be recorded on recording media or paper located between the typewheel and the hammer means. The recording device also includes a recording means actuating means 12 which is associated with the hammer means and is operable to cause the hammer means to effect a recording or non-recording operation demeans of FIGS. 18 and 7 in more pending upon the operation or not of a recording control means 13.

Power may be supplied to the recording device from an A.C. power source 14 (FIG. 1A) providing line voltages which may be subject to failures and fluctuations. The A.C. signals are applied on a plurality of leads 15 to an A.C. motor includedin the recording means actuating means 12, and to transformer and rectifier means such as 16, 17 and 18 which develop unregulated voltages at selected levels such as respective +13 volts, +5 volts and +24 volts. The rectifier 16 applies unregulated DC. voltage through the lead 19 to the +13 volt regulator 20. Similarly, the

rectifiers

17 and 18, respectively, apply unregulated D.C. voltages to a +5 volt regulator 21 and a +24 volt regulator 22. It is to be understood that the voltage regulators shown, as well as others not shown, are utilized to supply those voltage levels required in the various gates, flip-flops, memory circuits and other circuits utilized in the recording device, as well as in the electronic cash register system which the recording device is a part of.

In accordance with the present invention, the control system includes an A.C. power failure detector circuit 23 which is also connected to the power source 14 by means of the lead 15, and is supplied with a +5 volt regulated operating voltage by means of a lead 24 from the +5 volt regulator 21. The detector circuit 23 functions to normally develop a first control signal of 0 volts when power is being supplied thereto from the A.C. power source 14. But, when there occurs a loss of power, that is, a power failure condition occurs at the A.C. power source 14, the detector circuit 23 functions to sense such power failure condition and develops a second control signal of +5 volts which occurs approximately 20 milliseconds after the occurrence of such power failure condition. The first or second control signals are applied through a lead 25 to a first control circuit means or NAND gate 26 of circuit control means 27 (FIGS. 1A and 1B). The output of the NAND gate 26 constitutes a first timing control signal. The signal appearing on the lead 25 is herein designated as PFD (power fail detect).

The control system also includes a signal generator or first timing means 28 (FIG. 1A) for producing timing signals designated SPC, SMl-I and SBR respectively on output leads 29, 30, and 31. The signal generator 28 comprises a switch commutator (FIG. 6) which is associated with a drive shaft 149 (FIGS. 7 and 8) rotatably driven by the motor included in the recording means actuating means 12. The signals developed by the signal generator 28 are dependent upon the angular position of the drive shaft 149 during a cycle of operation of the recording device. The SPC signal appearing on the lead 29 constitutes a first timing signal which is applied to the NAND gate 26.

The circuit control means 27 further includes a bistable memory or latch circuit means 32 comprising

NAND gates

46 and 47, a second control circuit means comprising NAND gate 33, an amplifier 34, and a third control circuit means 35 comprising

NAND gates

36 and 37.

Also included in the control system, apart from the control means 27 thereof, is a further bistable memory or latch circuit means 38 comprising NAND gates 49 and 50 (FIG. 1A). The memory means 38 has applied thereto, by way of a lead 39, the signal output (SPC) of the signal generator 28. Such memory means 38 also has applied thereto, by way of the lead 31, the further signal output (SBR) of the signal generator 28. The signal generator 28 together with the memory means 38 comrpise a second timing means, and the signal designated PST appearing on the output lead 40 thereof constitutes a second timing signal which is applied to the NAND gate 33.

The control system includes further a DC. power recovery detector circuit 41 (FIG. 1A) which is connected to the

voltage regulators

20 and 21 respectively by means of the leads 42 and 43. The detector circuit 41 functions to normally develop a third control signal of +5 volts when the +13 volts and +5 volts outputs of the

regulators

20 and 21 are being supplied thereto, which third control signal will have a duration of approximately 50 milliseconds after a power failure condition occurs in the A.C. power source 14. When the A.C. power source 14 once again supplies proper operating voltages to the recording device following a power failure condition, the DC. power recovery detector 41 will respond to this power recovery condition and will develop a fourth control signal of volts which will have a duration of approximately 100 milliseconds after which time the third control signal will reappear. The third or fourth control signals are applied through

leads

44 and 45 to the memory means 32 and the

NAND gates

36 and 37 of the third control circuit means 35. I

Referring now to FIGS. 15 and 16 as well as to FIGS. 1A and 1B, the operation and further composition of the control system will be explained in detail. First will be explained the operation of the control system when the A.C. power source 14 provides proper operating voltages to the recording device. As set forth previously, the recording device is operable in a cycle having a recording preparation phase and a recording phase. The recording preparation phase is completed when the drive shaft 149 (FIGS. 7 and 8) driven by the motor of the recording means actuating means 12 has rotated 190, after which the recording phase is started. At the start of the recording preparation phase, the SMH signal (FIG. 16, line 1) is false (0 volts) until the drive shaft 149 has rotated and this false signal is applied by means of the lead 30 to a reset terminal of the NAND gate 46 of the memory means 32 aswell as to an input terminal of the NAND gate 33. With the memory means 32 in its reset state, an output signal, designated PFM (FIG. 16, line 6), of +5 volts appears on the output lead 48 which is connected to the NAND gate 33. When the drive shaft 149 has rotated 5, the SMH signal (FIG. 16, line 1) goes to +5 volts and remains at that voltage until the drive shaft 149 has rotated 330. This +5 volt signal has no effect on the memory means 32.

At the start of the recording preparation phase, until the drive shaft 149 has rotated the SPC or first timing signal (FIG. 16, line 3) is false (0 volts). This false signal is applied by means of the lead 39 to a reset terminal of the NAND gate 49 of the memory means 38 and ensures its resetting. With the memory means 38 in its reset state, the second timing signal PST (opposite in polarity to the signal PST, shown in FIG. 15, line 9, which signal appears at the output of the NAND gate 50) of +5 volts appears on the lead 40 which is connected to the NAND gate 33. When the drive shaft 149 has rotated 30, the SBR signal (FIG. 16, line 2 and FIG. 15, line 4 for the opposite polarity signal SBR) appearing on the output lead 31 of the signal generator goes to 0 volts and remains at that voltage until the drive shaft 149 has rotated 84. This 0 volts signal is applied to a set terminal of the NAND gate 50 of the memory means 38 causing it to be set which produces an output signal PST (opposite in polarity to the signal PST shown in FIG. 15, line 9) of 0 volts. Accordingly, when the drive shaft 149 is rotating between 5 and 30, the NAND gate 33 is being supplied with PFM, SMH and PST signals which are all of +5 volts. Normally, in absence of a power failure condition at the power source 14, the PFD signal output (FIG. 15, line 11) of the A.C. power failure detector 23 is at a false level of 0 volts. So between 5 and 30 rotation of the drive shaft 149, the NAND gate 33 will produce a 0 volts output signal, which is inverted by the amplifier 34 (FIG. 15, line 10). The output of the amplifier 34, designated PT C, constitutes a second timing control signal which is applied to the input terminals of the NAND gates 36 and'37 of the third control circuit means 35. The output signal of the DC, power recovery detector circuit 41, that is, the third control signal PRD (FIG. 16 line 8), is at a true level of +5 volts since there is an absence of a power failure at the A.C. power source 14, and this signal is also applied to input terminals of the

NAND gates

36 and 37 of the third control circuit means 35. Under this condition, between 5 and 30 shaft rotation, both of the

NAND gates

36 and 37 will develop a false level output signal of 0 volts, designated a recording control means operating signal which, in turn, is applied by means of the

leads

51 and 52 to the recording control means 13 to cause operation thereof. Operation of the recording control means 13 at this time will cause operation of data and

electro recording platens

208 and 209 respectively (FIG. 7), explained in more detail hereinafter, to cause the month and day and data of a descriptive or instructive nature respectively to be recorded on paper record material 191. When the drive shaft 149 has rotated 30, the SBR signal (FIG. 16, line 2) will change to 0 volts causing the memory means 38 to be set. With the memory means 38 in its set condition, the PST signal (opposite in polarity to the signal PST shown in FIG. 15, line 9) will be at 0 volts whereby the output of the NAND gate 33 will be at 5 volts and the PT C signal (FIG. 15, line 10) will be at 0 volts. The PST signal will remain at 0 volts until the drive shaft 149 has rotated 190 so that the PT C signal will be at 0 volts from between 30 and 190 of rotation of the drive shaft 149. Accordingly, the

NAND gates

36 and 37 will not be activated. Thus, the

NAND gates

36 and 37 will present, as outputs, recording control means inhibiting signals of +5 volts and the recording means 13 will not be operated during this time. It is when the drive shaft 149 of the recording device is rotating between 30 and 190 that the recording preparation or typewheel setting means 11 is operable to set the amount typewheels (such as the amount typewheels 194 of FIG. 7) of the recording means 10. When the drive shaft 149 has rotated 190 and the amount typewheels have been set, the SPC or first timing signal (FIG. 15, line 5 and FIG. 16, line 3) will go to 0 volts thus causing the resetting of the memory means 38. With the memory means 38 back in its reset condition, the PST or second timing signal (opposition polarity to the PST signal shown in FIG. 15, line 9) will change to 5 volts, the NAN D gate 33 will develop a 0 volts output signal and the PTC signal (FIG. 15, line 10) will be at 5 volts. Therefore, the

NAND gates

36 and 37 will develop recording control means operating signals of volts, which are applied over the

leads

51 and 52 to cause operation of the recording control means 13 (FIG. 1B). The recording control means 13, when operated, causes the recording means actuating means 12 to effect a subsequent operation.

Next will be explained the operation of the control system with a power failure condition at the power source 14 occurring when the drive shaft 149 of the recording device has rotated (FIG. 16, line 4). The AC. power failure detector circuit 23 will develop the second control signal PFD (FIG. 16, line 5) of 5 volts about 20 milliseconds after the power failure condition when the drive shaft 149 has rotated about 20. This second control signal PFD along with the SPC signal (FIG. 16, line 3), which goes to 5 volts at 10 rotation of the drive shaft 149, causes the NAND gate 26 to be activated thereby developing the first timing control signal of 0 volts. Such first timing control signal is applied to the memory means 32' causing the setting thereof. With the memory means 32 in its set condition, the PFM signal (FIG. 16, line 6) of 0 volts is applied by way of the lead 48 to the NAND gate 33 causing its activation. With the N AND gate 33 activated, the PT C or second timing control signal (FIG. 16, line 7) goes to 0 volts causing activation of the

NAND gates

36 and 37 which develop recording control means inhibiting signals of 5 volts on their output leads 51 and 52, which signals inhibit operation of the recording control means 13, that is, cause deenergization (FIG. 16, line 9) of solenoids 115 (FLC) and 116 (FFC) contained therein (see also FIG. 5). It will be noted that the DC. power recovery detector circuit 41 develops as an output the thirdcontrol signal PRD (FIG. 16, line 8) of 5 volts whenever it is supplied the +13 volts and +5 volts outputs of the voltage regulators and 21 and when there does not exist a power failure condition at the AC. power source 14. This third control signal PRD has a duration of 50 milliseconds after the occurrence of a power failure condition at the AC. power source 14, at which time there will occur a total loss of all operating voltages for the recording device.

Next will be explained the operation of the control system when there occurs a removal of the foregoing .power failure condition at the AC. power source 14,

that occurs, for example, when the drive shaft 149 has rotated 145 (FIG. 16, line 10) and before completion of the recording preparation phase at 190 rotation of the drive shaft 149. In this case, the DC. power recovery detector circuit 41 will be responsive to removal of the previous, voltage failure condition at the AC. power source 14 to develop the fourth control signal PRD (FIG. 16, line 14) of 0 volts, which signal will have a duration of about 100 milliseconds. This fourth control signal PRD is applied over the lead 45 to the

NAND gates

36 and 37 to cause their activation whereby 5 volts recording control means inhibiting signals are developed on the

leads

51 and 52, which signals inhibit operation of the recording control means 13. In addition, the fourth control signal PRD is applied to a set terminal of the NAND gate47 of the memory means 32 over the lead 44 ensuring the setting thereof and the development of the PFM signal (FIG. 16, line 12) of 0 volts which, in turn, causes activation of the NAND gate 33 and the development of a 0 volts PT C signal (FIG. 16, line 13). This action further ensures the activating of the

NAND gates

36 and 37 and the inhibition of the operation of the recording control means 13, whereby the recording means actuating means 12, whenoperated during the cycle recording phase, will not effect a recording operation.

Next will be explained the operation of the control system when there exists a power failure condition at the power source 14 that occurs when the drive shaft 149 of the recording device has rotated 195 (FIG. 16, line 16), for example (that is, after the recording preparation phase and after the recording preparation means 11 has been operated to set the amount typewheels to record desired information). When the drive shaft 149 of the recording device has rotated 190, the SPC (FIG. 16, .line 3) signal will change to 0 volts. Accordingly, the SPC signal will be effective to inhibit activation of the NAND gate 26. Hence, the first timing control signal of 0 volts will not be developed by such NAND gate and the memory means 32 will not be set even though the power failure detector circuit 23 will be responsive to such power failure condition. The DC. power recovery detector circuit 41, which in the absence of a power failure condition at the AC. power source 14 develops the third control signal of 5 volts, will continue to develop this third control signal PRD (FIG. 16, line 20) for a duration of 50 milliseconds after detection of the power failure condition. This third control signal PRD is applied over the lead 45 to the

NAND gates

36 and 37 which third control signal in combination with the PTC signal (FIG. 16, line 19) of 5 volts causes the

NAND gates

36 and 37 to develop recording control means operating signals of 0 volts on the

leads

51 and 52. Accordingly, the recording control means 13 will be operated so that when the recording means actuating means 12 is subsequently operated a recording operation will occur.

The NAND gate 36 of the third control circuit means 35 has either a PLF signal (FIG. 15, line 13) or a PSF signal applied to one of its input terminals by means of the lead 53. As will be described in more detail hereinafter with respect to FIGS. 7, 8 and 9, the PLF signal, which calls for a long feed operation, is at +5 volts during the time that the drive shaft 149 is rotating between 0 and 330. And, the PSF signal, which calls for a short feed operation, is at 0 volts during the foregoing time.

Referring now to FIG. 2, a typical NAND gate that may be utilized in the control system in accordance with the invention will be explained. A plurality of

input terminals

60 and 61 are coupled through the cathode to anode paths of

respective diodes

62 and 63 to a lead connection point.64 and, in turn, through

resistors

65 and 66 to a +5 volt terminal 67. The lead connection point 64 is also coupled to the base of an npn type transistor 68 having a collector coupled through the resistor 66 to the +5 volts terminal 67 and an emitter coupled through the anode to cathode path of a level shift diode 69 to the base of another npn type emitter-follower transistor 70. The emitter of the transistor 70 is coupled to ground potential and a resistor 71 is coupled between the base of the transistor 70 and ground potential. The collector of the transistor 70 is coupled through a resistor 72 to the +5 volt terminal 67. An output terminal 73 of the gate is coupled to the collector of the transistor 70. In operation, a false signal of 0 volts applied to either or both of the

input terminals

60 and 61 causes current to flow from the termitransistor 68 is at ground potential thereby biasing the transistor 68 to nonconduction. With transistor 68 nonconductive, the base of the transistor 70 is biased so that transistor 70 is also non-conductive and a volt or true signal is provided at the output terminal 73. When both of the input signals applied to the

terminals

60 and 61 are true or +5 volts, the

diodes

62 and 63 are biased out of conduction and a positive voltage is maintained at the base of the transistor 68 so that the transistor 68 is biased into conduction thereby supplying a turn-on current to the transistor 70. In this state, ground potential or a false signal level (0 volts) is provided at the output terminal 73.

The NAND gate of FIG. 2 functions as an and gate to develop a false output signal only when all of the input signals change from false levels to true levels. When the signals of all of the input terminals are normally maintained at true levels to provide a false output signal at the output terminal 73, the gate functions as an or gate in response to any or all of the input signals going to a false level todevelop a true output signal. When functioning as an inverter (amplifier 34 of FIG. 1) in response to a positive going input signal (that is with the output terminal normally at a true level), all

unused input terminals of the gate of FIG. 2 are cou- I pled to a +5 voltage and the input signal going true at the single active input terminal causes the output signal to go false, which is similar to the operation of the NAND gate when performing an"and function. Thus, depending on whether the gate of FIG. 2 normally has a true output signal or a false output signal, the symbols used in the FIG. 1 control system are respectively that of an and function (a gate symbol with a straight input edge) and of an or function (a gate symbol with a concave input edge). A small circle(s) at the input(s) to the gate symbol indicates that a false input signal activates the function. Conversely, the absence of a small circle indicates that the true input signal activates the function. A small circle at the symbol output indicates that the output terminal of the activatedfunction is false or 0 volts.

The bistable memory means or latch circuits 32 and 38 of FIG. 1 are formed by interconnecting NAND gates. The input leads to the

NAND gates

47 and 50 are set input leads and the input leadsto the

NAND gates

46 and 49 are reset input leads. The leads 40 and 48 are false output leads. The memory means 32 and 38 operate as follows. When either of the set input leads change to false levels, the memory means is set, and the output signals PFM and PST are false. When the reset input leads go to false levels, the memory means in reset, and the output signals PFM and PST are true.

' When both the set and reset input leads go to false levels, the output signals PFM and PST are at a true level. When both the set and reset input leads are at true levels, the memory means remains unchanged.

Referring now to FIG. 3, the AC. power failure detector circuit 23 includes the secondary winding 75 of a step-down transformer which lowers the AC. voltage of the power source 14 to +11 volts. This +11 volts AC. voltage is rectified by the rectifier circuit comprising 'the diodes 76 to 79. A capacitor 80, connected across the output of the rectifier circuit, is charged when the powersource 14 is supplying proper operating voltages. The cathodes of the diodes 76 and 77 and the positive plate of the capacitor are coupled through a resistor 81 to the base of an npn type transistor 82, the emitter of which is connected to ground potential. A resistor 83 is coupled from one end of the resistor 81 to ground potential, and another resistor 84 is coupled from the other end of the resistor 81 to ground 1 potential. The collector of the transistor 82 is coupled through a resistor 85 to a regulated +5 volt terminal 86. An output terminal 87 is coupled to the collector of the transistor 82. When there is absence of a power failure condition at the AC. power source 14, the capacitor 80 is charged and the base of the transistor 82 is biased so that the transistor 82 conducts and the output signal PFD at the output terminal 87 is false. When a power failure condition occurs at the power source 14, the voltage stored in the capacitor 80 keeps the transistor 82 conducting for a period of 20 milliseconds, after which time the transistor 82 ceases to conduct. At this time, the output signal PFD at the output terminal 87 goes to a true level of 5 volts and remains at that level for 30 additional milliseconds until the voltage regulator 21 fails to supply the +5 volts operating potential to the terminal 86.

Referring now to FIG. 4, the DC. power recovery detector circuit 41 includes two

npn type transistors

90 and 91, with the collector of the transistor 98 coupled to the base of the transistor 91. The collector of the transistor 90 is also coupled through a resistor 92 to a terminal 93 which is supplied with a +13 volts regulated voltage over the lead 94 (FIG. 1A), and is coupled to the base of the transistor 90 through a feedback capacitor 95. The base of the transistor 90 is coupled through the cathode to anode paths of respective

level shift diodes

96 and 97, through a variable resistor 98 and a resistor 99, to a terminal 100 which is supplied with a +5 volts regulated-voltage over the lead 101 (FIG. 1A). The base of the transistor 90 is also coupled through the cathode to anode paths of the

diodes

96 and 97, through the variable resistor 98, through the anode to cathode path of a diode 102, through a variable resistor 103 and through

resistors

104 and 105 to the +13 volts terminal 93. The base of the transistor 90 is also coupled through the cathode to anodepaths of the

diodes

96 and 97, through the variable resistor 98 to ground potential. The +13 volts terminal 93 is coupled through the cathode to anode path of a zener diode 106 (which is connected in parallel with the resistor 105), through the resistor 104, through the variable resistor 103 and through a resistor 107 to ground potential. A thermistor 108 is connected in shunt with the

resistors

103 and 104 and operates to vary the voltage supplied at the +13 volts terminal 93 in accordance with changes in the ambient temperature. Another thermistor 109 is connected in shunt with the variable resistor 98 and operates to provide temperature compensation for the transistor 90. The emitters of the

transistors

90 and 91 are coupled to ground potential. A resistor 110 is coupled between the cathode of the diode 96 and ground potential. The collector of the transistor 91 is coupled through a resistor 111 to the +5 volts terminal 100 and also directly to an output terminal 112.

In operation, when the recording device is connected to the AC. power source 14 (FIG. 1A) for operation thereof, or when there is a recovery from a power failure condition at the power source 14, the transistor 90 will remain in a nonconductive state until proper operating voltages are supplied to the

terminals

93 and 100 from their respective regulators 20 and 21 (FIG. 1A). But, current is applied to the base of the transistor 91 by way of the +13 volts terminal 93 and the resistor 92 so that the transistor 91 is immediately driven to its conductive state and a false output of volts appear on the output terminal 112. This false output persists for a period of about 100 milliseconds until the regulators 20 and 21 (FIG. 1A) provide proper operating voltages of +13 volts and volts respectively. When this occurs, the transistor 90 will be driven to its conductive state which, in turn, will cause the transistor 91 to be driven to its nonconductive state. At this time, a true output signal of +5 volts will appear on the output terminal 112. When there occurs a power failure condition at the power source 14 (FIG. 1A), the signal at the output terminal 112 will remain at +5 volts for a period of 50 milliseconds which corresponds to the time it takes for the voltage regulators and 21 (FIG. 1A) to cease providing proper operating voltages to the +13 volts and +5

volts terminals

93 and 100 respectively. The zener diode 106 functions to keep a voltage of about 6 volts between the ends of the resistor 105. The level shift diode 102 functions so that if the voltage applied to its cathode by way of the resistor 103 decreases, then current passes by way of the resistor 99, the diode 102 and the

resistors

103 and 107 to ground potential whichcauses the transistor 90 to go to its nonconductive state and transistor 91 to go to its conductive state.

' Referring now to FIG. 5, there is shown the circuit diagram of the

NAND gates

36 and 37 of the third control circuit means 35 of FIG. 1B, and the two solenoids 115 (FLC) and 116 (FFC) of

solenoid energizing circuits

117 and 118 included in the recording control means 13 of FIG. 1B. Since the NAND gate 36 and solenoid energizing circuit 117 is substantially the same as the NAND gate 37 and solenoid energizing circuit 118, only the former will be explained in detail. A plurality of input terminals 113, 119 and 120 are coupled through the cathode to anode paths of

respective diodes

114, 121 and 122 to a lead 123 which is coupled to the base of an npn type transistor 124. The lead 123 is also coupled through a resistor 125 to a +5 volts terminal 126. The collector of the transistor 124 is coupled through a resistor 127 to the terminal 126. The emitter of the transistor 124 is coupled by means of a lead 128 to the base of an npn type transistor 129, the emitter of which is coupled to ground potential. The lead 128 is also coupled through a resistor 130 to ground potential. The collector of the transistor 129 is coupledthrough a lead 131 to one end of the winding 132 of the solenoid 115, the other end of which is coupled to a +24 volts terminals 133. A diode 134 is connected in parallel with the winding 132so as to prevent destruction of the

transistors

124 and 129 dissipating the inductive spike which occurs when the solenoid 115 deenergizes. In operation, a false signal of 0 volts applied to any or all of the input terminals 1 13, 119 and 120 causes current to flow from the terminal 126 through the resistor 125 and through the corresponding diode or diodes so that the transistor 124 is maintained in a nonconductive state. With transistor 124 in a nonconductive state, the base of transistor 129 is biased so that transistor 129 is also nonconductive and current does not flow through the winding 132. When all of the input signals applied to the input terminals 113, 119

and are true, that is the PLF, the PTC and PRD sig nals are at +5 volts, the

diode

114, 121 and 122 are biased out of conduction and a positive voltage is maintained at the base of the transistor 124 so that that transistor is biased into conduction to supply a turn-on current for the transistor 129. With the transistor 129 conductive, current flows through the winding 132. As will be described in more detail hereinafter when FIGS. 7, 8 and 9 are described, the PLF signal (FIG. 15) which calls for a long feed operation, is at +5 volts or true during the time that the drive shaft 149 is rotating between 0 and 330. And, the PSF signal, which calls for a short feed operation, is at 0 volts or false during the foregoing time.

Referring now to FIG. 6, the signal generator 28 of FIG. 1A comprises a switch commutator 135 composed of ten individual stationary segments 136 through arranged in an outer are on a dielectric base (not shown), two individual

stationary segments

146 and 147 arranged in an intermediate are on the dielectric base, and an inner circular continuous segment 148 on the dielectric base. The recording device is driven by a motor (not shown), which is a part of the recording means actuating means 12 (FIG. 1B), and which is energized by the AC. power source 14 over the lead 15. The motor shaft is geared, and, upon energization of the motor, it rotates the first geared drive shaft 149 (FIGS. 7 and 8). The drive shaft 149, in turn, is coupled to a second geared drive shaft 150 (FIGS. 6

and 10) rotated through an idler gear shaft. Attached to one end and rotating with the drive shaft 150 is a wiper arm 151 carrying three

brush contacts

152, 153 and 154. As shown in'FIG. 6, the segment 136 extends in a are from 30 to 84 relative to the rotation of the drive shaft 150 from a start or home position designated as 155. The segments 137 to 145 extend at intervals of 8 with a clearance of 2 between them. The segment 136 is connected through a resistor 157 to a +5 volts terminal 158 and to the input of an inverter 159. The inverter 159 is coupled through another inverter 160 to an output terminal 161 at which the signal designated SBR appears (FIG. 16, line 2). The segment 148 is connected to ground potential. In operation, when the brush contact 154 is not contacting the segment 136, the potential at the +5 volts terminal 158 causes a true signal of +5 volts to appear at the output terminal 161. However, when the brush contact 154 makes contact with the segment 136, the potential at the +5 volts terminal 158 is coupled to ground potential by say of the brush contact 154 electrically connected to the brush-contact 152, which in turn is coupled through the segment 148 to ground potential. Accordingly, a false signal of 0 volts appears at the output terminal 161 (SBR). In a similar manner, signals, designated PS1-9, appearing on the output terminals 163 through 171 will be at a false level of 0 volts when the brush contact 154 makes contact with the segments 137 to 145 respectively. The signals PSI-9 are coupled to electronic comparators (not shown) included in the recording device. It will be apparent when FIGS. 10 through 14 are described in detail hereinafter, that when the character on the amount typewheel 194 corresponding to its associated transmission segment 271 coincides with the character stored in an electronic memory (not shown), then the electromagnet 296 of the solenoid block device 292 will be deenergized at the times shown in FIG. 15, line 8, and the printing of the selected character can be accomplished. The segment 146 is connected through a resistor 173 to a volt terminal 174 and to the input of an inverter 175. The inverter 175 is coupled through another inverter 176 to an output terminal 177 at which the signal SMH appears (FIG. 16, line 1). In this case, the input of the inverter 175 is placed at ground potential by its coupling to ground potential by way of the segment 146,

brush contacts

153 and 152, and segment 148. The segment 147 is connected through a resistor 179 to a +5 volt terminal 180 and to the input of an inverter 181. The inverter 181 is coupled to an output terminal 182 at which the signal SPC appears (FIG. 16, line 3). The input of the inverter 181 is placed at ground potential by its coupling to ground potential by way of the segment 147,

brush contacts

153 and 152, and segment 148.

Referring now to FIGS. 7, 8 and 9, there is shown in detail the recording means 10, the recording means actuating means 12 and a further portion of the recording control means 13. Referring first to FIG. 7, the recording means comprises a selectively operable dual hammer printing head 190 for printing data on paper material 191 located between the printing head 190 and a date typewheel 192, an electro type 193 and an amount typewheel 194. An ink ribbon 195 is located between the paper material 191 and the foregoing type devices. Although only one type device is shown, it is to be understood that the recording device in a cash register embodiment would be composed of a series of date typewheels 192 comprising month, day and year wheels, an electro type for printing data of a descriptive or instructive nature, and a series of amount typewheels 194 corresponding to the rows of amount keys provided on the cash register device.

The printing head 190 includes a crank 196 secured to a sleeve (not shown) free on a supported stud 197. Also secured to the sleeve is a hammer impression cam 198 which co-acts with a roller 199 supported in a hammer block 200. The hammer block 200 includes a trunnion stud 201 which is engagedby an amount impression yoke 202 pivoted on another trunnion stud 203., The hammer impression cam 198 has a surface which co-acts with a roller 204, mounted in a hammer block 205 which, in turn, has a trunnion stud 206 which engages a data impression yoke 207. The forward end of the date impression yoke 207 is pivotally supported by the stud 201 in the hammer block 200. The hammer block 205 carries a platen 208 which co-acts with the date typewheel 192, and it also carries a wider platen 209 which co-acts with the electro type 193. The hammer block 200 carries a platen 210 which co-acts with the amount typewheel 194 for printing the data set up thereon on the record material 191.

The recording means actuating means 12 includes a pitman 211, the upper end of which is pivotally connected to the crank 196. The lower end of the pitman 211 has an irregulator control slot 212 which cooperates with a stud 213 in a hammer operating arm 214 (FIG. 8). A spring 215 urges the pitman 211 in a counter-clockwise direction which in turn urges a sensing lever 216 (see also FIG. 9), which is a part of the recording control means 13, in a sensing or clockwise direction on its support stud 222 to position the pitman control slot 212 in relation to the stud 213. The hammer operating arm 14 is freely rotatable on a stud 217 and carries

rollers

218 and 219 which cooperate with a plate cam 220 secured to the drive shaft 149. As the hammer operating arm 214 rocks on the stud 217, the stud 213 is allowed to move around the stud 217. And so, the pitman 211, into whose slot 212 the stud 213 is fitted,'is caused to move, in turn causing the

plates

208, 209 and 210 to operate to effect a recording operation. The sensing lever 216 is pivoted on the stud 222 and has a lower left extension in the form of an ear 223 bent outwardly therefrom (FIGS. 7 and 9). The sensing lever 216 also has an upward central extension 225 provided with an arcuate slot 226 which cooperates with a stud 217 fixed in the lower end of the pitman 221, and further has an upward extension 228 to the left thereof provided with a projection 229 which cooperates with rollers 230 and 231 (FIG. 7) provided on a plate cam 232 secured to the drive shaft 149. Besides the sensing lever 216 and the cam 232, another part of the recording control means 13 is composed of the solenoids 233 and 234 (corresponding to

solenoids

116 and 115 respectively, FIG. 5) with their

respective armatures

235 and 236, and the latch levers 237 and 238 and springs 239 and 240. r

When the stud 213 of the hammer operating arm 214 is positioned at position A (FIG. 7) inside the slot 212 of the pitman 211, the pitman 211 will not be moved upward or downward during rocking of such arm 214. Consequently, a recording operation will not .be performed since the stud 213 performs an idle movement only within the pitman slot 212. But, when the stud 213 is at an intermediate position, that is, position B (FIG.

7), part of the movement of the stud 213 during arm 214 rocking will stay idle without affecting the movement of the pitman 211, while another part of the movement of the stud 213 will cause the pitman 211 to vertically move, thus allowing the recording of information represented on the amount typewheel 194. When the stud 213 is positioned at position C inside the slot 212 (FIG. 7), it will contact both the upper and lower sides of the slot 212 during movement thereof and thus allow the recording of information represented on the amount type-wheel 194, the data typewheel 192 and the electro-type 193 The sensing lever 216 is utilized to control the locating of the stud 213 either at position A, B or C within the pitman slot 212. The slot 226 in the sensing lever 216 accommodates'the stud 227 of the pitman 211. Consequently, when the slot 226 is moved in a horizontal direction, the stud 227 will follow such movement so that the relative position between the lower end of the pitman 211 and the stud'213 can be changed.- The pitman 211 is influenced by a spring 242 at all times in such a manner that it can move around an upper pivot point 241 (FIG. 7) in a clockwise direction. Accordingly, the sensing lever 216 is likewise influenced by such spring 242 in such a manner that it may rotate on the stud 222 in a clockwise direction by the engagement of the stud 227 in the slot 226 and by the force of the spring 242. The

solenoids

233 and 234 and associated latch levers 237 and 238 control the positioning of the stud 213 in one of the three foregoing positions A, B or C. The latch lever 237 is provided with a lower shoulder portion PA which links with the ear 223 of the sensing lever 216 and is adapted to pivot around the pin 243 which is connected to the frame (not shown) of the recording device. The armature 235 of the solenoid 233 is provided with an outer end 244 which links with an upper nose end 245 of the latch lever 237. The latch lever 237 is also provided with an upper shoulder portion PC. In a similar manner, the latch lever 238 is provided with a lower shoulder portion PB which links with the ear 223 of the sensing lever 216 and it is adapted to pivot about the pin 221 which is likewise connected to the frame (not shown) of the recording device. The armature 236 of the solenoid 234 is provided with an outer end 246 which links with the upper nose end 247 of the latch lever 238. As illustrated in FIG. 7, the latch levers 237 and 238 are positioned in the recording device in a parallel arrangement so that they act upon the car 223 of the sensing lever 216 in combination.

In operation, when the solenoid 233 is not energized (as shown in FIG. 7), the outer end 244 of the armature 235 will recede. The latch lever 237 is urged at all times by the force of the spring 240 so that, at such solenoid 233 deenergized time, it will rotate around pin 243 in a counterclockwise direction toward the left end of the sensing lever 216 and cause its shoulder portion PA to engage with the ear 223. However, if and when the solenoid 233 is energized, the outer end 244 of the arma ture 235 will cause the latch lever 237 to rotate in a clockwise direction against the urging of the spring 240. Consequently, the shoulder portion PA of the latch lever 237 will leave the left end or ear 223 of the sensing lever 216 and cause, by the force exerted by the pitman spring 242, the sensing lever 216 to rotate in a clockwise direction so that its ear 223 will engage the lower shoulder portion PB of the latch lever 238, and be retained at that position. As shown in FIG. 7, the solenoid 234 is also not energized, and so the outer end 246 of the armature 236 does not rotate the latch lever 238. But, if and when the solenoid 234 is energized, the outer end 246 of the armature 236 moves in a counterclockwise direction causing the latch lever 238 to rotate in a clockwise direction against the urging of the spring 239 so that the shoulder portion PB of the latch lever 238 is released from the ear 223 of the sensing lever 216. Accordingly, at such time the sensing lever 216 will continue rotation in a clockwise direction under the urging of the spring 242 until engaging with the upper shoulder portion PC of the latch lever 237. The cam 232 on the drive shaft 149 will return the sensing lever 216 from ear 223 contact with the upper shoulder portion PC to the lower shoulder portion PA of the latch lever 237., As shown in FIG. 9, there is provided the projection 229 on the sensing lever 216 which, when the cam 232 rotates in a counterclockwise direction, the rollers 230 and 231 will engage and urge downward to return the ear 223 of the sensing lever 216 from contact with the shoulder portion PC to contact with the shoulder portion PA.

From the foregoing description it is seen that when the shoulder portion PA of the latch lever 237 is in engagement with the ear 223 of the sensing lever 216, then the stud 213 on the hammer operating arm 214 will be in position A with respect to the pitman control slot 212. When the shoulder portion PB of the latch lever 238 is in engagement with the ear 223, then the stud 213 will be in position B, and when the shoulder portion PC of the latch lever 237 is in engagement with the ear 223, then the stud 213 will be in position C. As discussed previously, when the drive shaft 149 is caused to rotate 5 by means of the motor of the recording device, both of the solenoids 233 and 234 (corresponding to 1 16 and 115 of FIG. 5) will be energized under the control of recording control means operating signals appearing on the output leads 51 and 52 of the NAND gates 36 and 37 (FIG. 18). Accordingly, at such 5 time, the latch levers 237 and 238 will operate and have their lower shoulders PA and PB released from the ear 223 of the sensing lever 216 so that such ear 223 of the sensing lever 216 will engage the upper shoulder portion PC of the latch lever 237. Consequently, since the stud 213 of the hammer operating arm 214 is then positioned at position C (FIG. 7), the pitman 211 will be moved upwardly under the influence of the cam 220 so that the date and the electro data is recorded on the record material 191. After this recording is completed, the roller 230 on the cam 232 will urge the projection 229 of the sensing lever 216 downwardly so that the sensing lever 216 may return to a position where its ear 223 is in engagement with the lower shoulder portion PA of the latch lever 237. Then, when the drive shaft 149 rotates to 190, and the amount typewheel 194 has been set by the recording preparation means 11, the

solenoids

223 and 234 will again be energized to release the sensing lever 216 ear 223 from engagement with the lower latch shoulders PA and PB so that the stud 213 ofthe hammer operating arm 214 is again positioned at position C, and the pitman 211 will be moved downwardly under the influence of the cam 220 so that the amount data is recorded on the record 191. When the recording operation is completed, the roller 231 on the cam 232 will again urge the projection 229 of the sensing lever 216 downwardly so that the sensing lever 216 may return to the position where its ear 223 is again in engagement with the lower shoulder portion PA of the latch lever 237.

The foregoing description of the operation of the recording device corresponds to the previously mentioned printer long feed operation (PLF), wherein, during a cycle of operation of the recording device information on the date typewheel 192, the electro-type 193 and the amount typewheel 194 is recorded. Referring back to FIGS. 1A and 18, if a long feed operation is desired, a true signal of +5 volts will be present on the lead 53 during the time that the drive shaft 149 is rotating between 0 and 330, thereby providing an enabling signal to the NAND gate 36 to normally cause the solenoid 234 to be energized twice during each cycle of operation of the recording device. If a printer short feed operation (PSF) is desired, wherein only the information on the amount typewheel 194 is to be recorded, then a false signal of 0 volts will be present on the lead 53 during the time that the drive shaft 149 is rotating between 0 and 330, thereby providing an inhibiting signal to the NAND gate 36 to normally cause the solenoid 234 not to become energized during a cycle of operation of the recording device. Accordingly, when a short feed operation is selected, the solenoid 234 is not energized at all during the recording device cycle, while the solenoid 233 is normally energized twice, first between 5 and 30 and again between 190 and 330 of rotation of the drive shaft 149. During both of these periods, the stud 213 of the hammer operating arm 214 will be positioned at position B (FIG. 7). During the -30 period, the cam 220 will not cause a movement of the pitman 211 and the date and electro information will not be recorded. During the l-3 30 period, however, the cam 220 will cause the pitman 211 to be moved downwardly so that the amount data is recorded.

In further detail, if neither of the

solenoids

233 or 234 is energized during a cycle of operation of the recording device, the movement clockwise of the sensing lever 216 will be obstructed and the slot 212 in the pitman 211 will be maintained in position A of FIG. 7. While at such position, the stud 213 is free to oscillate back and forth in the clearance portion of the slot 212 during operation of the hammer operating arm 214 without imparting any up or down movement to the pitman 211 and consequently no printing movement will be imparted to the hammer blocks 200 and 205. In addition, no feeding movement will be imparted to the record material 191 with the hammer blocks 200 and 205 not operated. When only the solenoid 233 is energized, the sensing lever 216 will receive sufficient clockwise movement to rock the lower end of the pitman 211 sufficiently in a forward or counterclockwise direction to move an intermediate lower surface 248 of the slot 212 beneath the stud 213 that is, at position B of FIG. 7. With such position, the clockwise movement of the. hammer operating arm 214 to operate the platen 210 will cause the stud 213 to engage the surface 248 and shift the pitman 211 downwardly. Downward movement of the pitman 211 will rock the crank 196 clockwise causing the shifting of 'the hammer block 200 downwardly to cause the platen 210 to carry the record material 191 and the ink ribbon 195 into yielding contact with the amount typewheel 194. If both of the

solenoids

233 and 234 are energized, the sensing lever 216 is free to move full distance in the'clockwise direction, to shift the lower end of the pitman 211 full distance forwardly or counterclockwise for moving a rearward branch 249 of the slot 212 into engagement with the stud 213 (position C). When the pitman 211 is thus positioned, initial movement of the hammer operation arm 214 causes the stud 213 in cooperation with the branch 249 to first shift the pitman 211 upwardly, which movement rocks the crank 196 in a counterclockwise direction causing the shifting of the hammer block 205 downwardly to cause the

platens

208 and 209 to carry the record material 191 and the ink ribbon 195 into yielding engagement respectively with the date typewheel 192and the electro-type 193 to record the data thereon on the record material 191. Subsequent clockwise movement of the hammer operating arm 214 causes the stud 213 in cooperation with the branch 249 of the slot 212 to then shift the pitman 211 downwardly to cause printing movement to be imparted to'the hammer block 200 to record the data on the amount typewheel 194 upon the record material 191. A full sensing movement clockwise of the sensing lever 216 causes a long feed of the paper material 191 which is necessary when both of the hammer blocks 200 and 205 operate to print the date, the electro data and the total amount of the record material 191.

The mechanism for feeding the record material 191 includes a pressure roller 250 and a feed roller 251 having a pinion meshing with a gear 252 integral with a ratchet 253 free on a stud 254 (FIG. 7). The teeth of the ratchet 253 are yieldingly engaged by three springurged feed pawls255 (only one here shown) mounted on an extension of a segment 256 free on the stud 254 and having gear teeth which mesh with corresponding on the stud 260. The lever 259 carries a roller 261 on its lower left end (FIG. 7) which co-acts with the periphery of a plate cam (not shown) secured on the drive shaft 149 and performing one counterclockwise revolution each recording device operation.

The recording device is herein described as being utilized in a cash register environment and so is arranged for itemizing transactions which comprise several item entering operations and a final item total operation, during which latter operation the item total, the date and the data on the electro are recorded on the record material 191. A comparatively short feed of the material 191 is required in item entering operations and a comparatively long feed is required after the item total operation to feed the finished receipt or the like beyond the edge of a paper tearing blade. Likewise, in certain operations called for by the cash register device it is desirable that the record material not feed at all, as in such operations no recording is made thereon. The length of the record material feed, in accordance with the fore-going description, is controlled by the counterclockwise or take-up movement of the lever 257, this movement in turn being governed by the operation of the sensing lever 216 which prevents take-up movement of the lever 257 when no record material feed is required, permits a short take-up movement when a short record material feed is required, and permits full take-up movement when a long record material feed is required.

Referring now to FIGS. 10 through 14, there is shown in detail the recording preparation or typewheel setting means 11. A first horizontal shaft 270 is fitted underneath the frame of the recording or cash register device so as to freely rotate and a plurality of transmission sectors or segments 271 are attached to the shaft 270 so as to freely rotate therewith. While only one transmission segment 271 is shown in FIG. 10, it is to be understood that transmission segments for other recording mechanisms may be provided. The transmission segment 271 is connected to a drive gear 272 by means of

links

273 and 274, a horizontal shaft 275, and further links 276 and 277 (FIG. 10). As also seen in FIG. 10, the gear 272 drives another gear 269 which causes rotational setting of the amount typewheel 194. Hence, when the angular position of the transmission segment 271'is determined, the angular position or setting of the amount typewheel 194 will be also determined. Sector gears 278 and 279 are attached to the respective ends of the shaft 270, and companion sector gears 280 and 281 are operably associated therewith. The

gears

280 and 281 are attached to a second horizontal shaft 282 so as to freely rotate thereon under the influence of a plate cam 283 engaging

cam followers

284 and 285 on sector gear 280. The plate cam 283 is attached to the drive shaft having its drive gear 313 rotated by a motor (not shown). With such construction, the sector gears 27 8 and 279 are allowed to move in a reciprocating manner'to the left and right, as seen in FIG. 10, under the influence of the plate cam 283 As seen in FIGS. 1 1-13, the transmission segment 271 is provided with an arcuate slot 286. Two

rocker arms

287 and 288 are fixedly attached to the sector gears 278 and 279, respectively (FIG. 10), and a transmission shaft 289 extends between

such rocker arms

287, 288 and passes through the arcuate slot 286 of the transmission segment 271. Accordingly, the transmission segment 271 will move in a reciprocating manner, following the mo-

Claims

1. In a recording device coupled to a power source, wherein said recording device comprises recording means, recording preparation means for preparing said recording means for operation, recording means actuating means for operating said recording means, and recording control means for controlling said recording means actuating means; and wherein said recording device is operable in a cycle having at least two phases, one of said phases being a recording preparation phase, and the other being a recording phase occurring after the completion of said recording preparation phase; and wherein said recording means actuating means when operated during said recording phase causes a recording or non-recording operation of said recording device determined by operation or not of said recording control means during said recording phase; a control system for ensuring proper operation of said recording device during the cycling thereof comprising: first detecting means coupled to said power source responsive to a voltage failure condition; first timing means for developing a first timing signal occurring during said recording preparation phase; and circuit control means coupled to said first detecting means and said first timing means operable to inhibit operation of said recording control means upon occurrence of a voltage failure condition at said power source during said recording preparation phase so that said recording means actuating means when operated will effect a non-recording operation.

2. The invention as set forth in claim 1 wherein said recording device includes power supply means coupled to said power source, and said control system includes second detecting means coupled to said power supply means responsive to removal of said voltage failure condition during said recording preparation phase, said circuit control means being coupled to said second detecting means and being operable to inhibit operation of said recording control means upon removal of said voltage failure condition so that said recording means actuating means when operated will effect a non-recording operation.

3. The invention as set forth in claim 2 wherein said second detecting means is also responsive to a voltage failure condition occurring after the initiation of said recording phase, and said control system further includes: second timing means for developing a second timing signal occurring during said recording phase; said circuit control means being coupled to said second timing means and being operable to cause operation of said recording control means during said recording phase upon lack of a voltage failure condition at said power source during said recording preparation and recording phases or upon the occurrence of a voltage failure condition at said power source after initiation of said recording phase so that said recording means actuating means when operated will effect a recording operation.

4. The invention as set forth in claim 3 wherein said recording means includes a hammer means, and a typewheel carrying a plurality of indicia; and wherein said recording preparation means includes a typewheel setting means for setting said typewheel so that a selected indicium is in operative association with said hammer means.

5. The invention as set forth in claim 4 wherein said first detecting means is also responsive to a voltage presence condition to produce a first control signal and is responsive to said voltage failure condition to produce a second control signal; said circuit control means includes first control circuit means responsive to simultaneous occurrence of said second control signal and said first timing signal to develop a first timing control signal, bistable memory means coupled to said first control circuit means normally in one state but changeable to its other state in response to said first timing control signal, said bistable memory means when changed to its said other state being effective to inhibit operation of said recording control means.

6. The invention as set forth in claim 5 wherein said first detecting means is operable to produce said second control signal after a first predetermined time interval which has a first predetermined time duration if said voltage failure condition persists; said second detecting means is also responsive to a voltage presence condition at said power supply means as well as being responsive to a voltage failure condition at said power supply means to produce a third control signal occurring both during said voltage presence condition and for a second predetermined time duration after occurrence of said voltage failure condition, said second predetermined time duration being greater than said first predetermined time duration, said second detecting means being operable in response to removal of said voltage failure condition at said power supply means to produce a fourth control signal having a third predetermined time duration greater than said second predetermined time duration; and said circuit control means further includes second control circuit means coupled to said bistable memory means and said second timing means for developing a second timing control signal only when said bistable memory means is in said one state and said second timing signal is present; and third control circuit means coupled to said second control circuit means and to said second detecting means responsive to said fourth control signal or to the lack of said second timing control signal to cause said inhibited operation of said recording control means, and responsive to both said second timing control signal and said third control signal to cause said operation of said recording control means by means of a recording control means operating signal produced thereby.

7. The invention set forth in claim 6 wherein each of said first, second and third control circuit means includes a gate means for developing said first timing control signal, said second timing control signal and said recording control means operating signal respectively, and said bistable memory means includes a latch circuit.

8. The invention as set forth in claim 7 wherein said recording means actuating means includes: motor means coupled to said power source and energized thereby; first operating means driven by said motor means for operating said hammer means; and movable means to connect said hammer means to said first operating means; and wherein said movable means is normally out of co-acting relationship with said first operating means but movable into co-acting relationship therewith upon operation of said recording control means under control of said circuit control means so that further movement of said movable means by said first operating means will cause a recording operation.

9. The invention as set forth in claim 8 wherein said movable means includes a pitman having operating surfaces normally out of co-acting relationship with said first operating means.

10. The invention as set forth in claim 9 wherein said recording control means includes: a movable sensing lever having operating surfaces operatively connected to said pitman; and second operating means coupled to said circuit control means for controlling movement of said sensing lever to cause its operating surfaces to move said operating surfaces of said pitman into co-acting relationship with said first operating means.

11. The invention as set forth in claim 10 wherein said second operating means includes: movable latch member means for controlling the movement of said sensing lever; solenoid means for controlling movement of said latch member means; and an energizing circuit for energizing said solenoid means under control of said circuit control means.

12. The invention as set forth in claim 11 wherein said first operating means includes: a rotatable shaft driven by said motor means and carrying a cam member; and a movable arm driven by said cam member having a first projection thereon with which said operating surfaces of said pitman are moved into co-acting relationship; and said pitman has a second projection thereon cooperating with said operating surfaces of said movable sensing lever.