US3809927A - Delay timing circuit - Google Patents
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- US3809927A US3809927A US00239572A US23957272A US3809927A US 3809927 A US3809927 A US 3809927A US 00239572 A US00239572 A US 00239572A US 23957272 A US23957272 A US 23957272A US 3809927 A US3809927 A US 3809927A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
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- a timer apparatus includes a timer circuit utilizing the [52] U.S. CI. 307/293, 317/ 141 S, 328/131 charging and discharging of'a capacitor.
- t cuit omprises a capacitor adapted to charge in Field of Search 307/293, 10 LS; 3l5/82, he direction for cutting-off a transistor at the setting 315/77, 83; 317/141 S; 328/l29l3 time, a switch adapted to apply the voltage in the direction for discharging of said capacitor, and a transis- 1 References Cited tor adapted to be turned conductive after a given time UNITED STATES PATENTS from the commencement of discharging.
- Said timer 3,274,434 9/1966 Miller 315/82 has excellent temperature and voltage characteristics 3,287,608 11/1966 Pokrant 1 317/142 1 a t u p y g a Zener diode and is hardly 3,389,296 6/1968 0211111111.
- ... 315/82 affected by the DC current amplification factor of 3,40 .3 2 8 Ec 3l7/14
- the present invention relates to a timer device and more particularly to a timer device capable of determining a set time to be several seconds through dozens of minutes by utilizing semiconductor circuits.
- a thermal-responsive type (bimetal) timer for instance, a motor type timer, or an electronic (a semiconductor) type timer, etc
- a timer for an automobile which utilizes a DC. source'as its power source (such as a timer for a defogger, a timer for an automatic choke, a warning timer for seatbelts, 'an off-delay timer for headlights and a timer for turning out a headlight after a given time of period has passed since an automobile stops)
- the voltage of its power source varies, so that a motor type timer cannot be utilized and a thermal-responsive timer has been used in most cases.
- Such conventional thermal-responsive type timers are subject to the influence of the ambient temperature and therefore apt to be inaccurate in setting a predetermined time, and it this transistor is increased and it becomes necessary to provide with a transistor having such a large collector loss as can counterbalance therewith, which would raise the cost.
- the fact that the transistor for driving a relay passes slowly through the active region means that at first on the exciting coil of the relay is applied a full source voltage, then such voltage gradually decreases to an open-circuit voltage near the end of the set time. Therefore, when the transistor is in the active region, a sufficient exciting voltage is not applied thereto thus, even with only a slight vibration, the relay may possibly be opened, although the set predetermined time has not yet passed.
- the present invention has been made to overcome the above-mentioned disadvantages. lt is therefore an object of the present invention to provide a timer which has excellent temperature and voltage characteristics without employing such expensive semiconductor elements as a Zener diode or a field-effect transistor and which is not affected by the DC. current amplification factor of the transistors employed and which is the further has a disadvantage that a set time for a subsequent operation is by far shortened due to the thermal inertia in cases where sequential operation is effected.
- Another object of the present invention is to provide a timer which is adapted to expend no electric power when operates as a timer, due to the complete interruption of the circuits and loads from power sources, and to produce no erroneous operation due to external noise even with a high impedance circuit.
- a further object of the present invention is to provide a timer which employs no elements other than the fundamental circuit elements for voltage regulation and temperature compensation as a timer, and which is capable of, in its performance, being fully stable against the variation of power supply voltage or ambient temperature in normal use and which can be manufactured at reasonable cost.
- a timer device including a timer circuit utilizing the charging and discharging of a capacitor, comprising a timing capacitor adapted to charge in the direction for cutting-off a transistor at the time of setting; a switch adapted to apply a voltage in the direction for discharging the charged electric charge of said capacitor to cause such discharge; and said transistor adapted to be turned conductive after a predetermined period of time has passed from the commencement of discharging, thereby to determine a set time.
- H0. 1 is a circuit diagram of one preferred embodiment of the present invention.
- FIGS. 2 through 4 are circuit diagramsof modified embodiments in accordance with the present invention.
- E designates a DC. power source, SW a switch for setting and resetting, R, a charging resistor, one terminal of which is connected with a setting contact P of the setting-resetting switch SW and the other terminal of which is connected with a positive electrode or a timing capacitor C.
- R is a reone terminal of which resistor is connected with a +3 I power supply line and the other of which is connected with the junction of the negative electrode of said timing capacitor C and a base of a first stage transistor Tn.
- R is a collector resistor one terminal of which is connected with the +B power source line and the other terminal of which is connected with both a collector of the first stage transistor Tr, and a base of a second stage transistor Tr
- the emitters of the first and the second stage transistors Tr, andTr are connected to the negative terminal of the power source E.
- R is a base resistor, one terminal of which is connected with said contact P, of the setting-resetting switch SW and theother terminal of which connects with the base of the second stage transistor Tr Y is a relay for controlling a load current and includes a coil Y,, one terminal of which is connected with the +8 power supply line and the other terminal'of which connects with a collector of the second stage transistor Tr Relay y further includes a contact y, one terminal of which is connected with a positive terminal of the power supply E and the other terminal of which connects with the +B,power supply line.
- D is'a diode, for preventing a counter electro-motive force connected in parallel with the coil Y, of said relay Y.
- a setting contact P is connected with the positive terminal of the power supply E and a setting contact P5 connects with the +8 power supply line, respectively, while a resetting contact P, is connected with the base of the second stage transistor Trand another resetting contact P connects with the negative terminal of the power supply E, respectively.
- L is a load having a terminal connected with the negative terminal of the power supply and another terminal connected with the +B power supply line.
- V0 is the charging voltage of a timing capacitor C,.Vd the base-emitter forward voltage of the transistor Tr, and E the power supply voltage.
- the second stage transistor Tr is cut off, and the relay Y is made'open to interrupt the current to the load L, thereby terminating'one delay operation.
- the contact y: of the relay Y is opened andboth the load L and the timer circuit itself will be completely separated from the power supply E, as the movable contact 'P of the setting resetting switch SW stands in the neutral'position.
- a first stage transistor Tr with a base-emitter withstand voltage higher than the power supply voltage should be employed. Otherwise, a diode D with a withstand voltage higher than the power supply voltage should be connected in series with both the positive electrode of the timing capacitor C and the base of the first stage transistor Tr, as shown in FIG. 2, thereby to operate in a preferable condition regardless of the value of the constant a.
- FIG. 3 a circuit diagram of another embodiment of the present invention will be explained.
- the base of a third transistor Tr is connected with the collector of the first stage transistor Tr, shown in the circuit of FIG. 1, and the collector of said transistor Tr, is connected with the +8 power supply line and the emitter thereof is connected with the base of the second stage transistor Tr
- the maximum value of the timing resistor R allowed to be employed is at most 2 through 3 megohms, so that so long set time cannot be expected.
- the third transistor Tr is additionarily employed and the DC. current amplification factor of the second stage transistor Tr will be increased equivalently, thereby raising the base resistance R, (timing resistance) of the first stage transistor Tr,.
- a diode D is connected between the first stage transistor Tr, and the timing capacitor C, thereby enabling to function satisfactorily regardless of the value of the Y constant a.
- the timing resistor R of 100 megohm can be employed, thus enabling a timer of dozens of minutes of set time to be realized.
- the second stage transistor Tr rises to increase the loss of said transistor Tr
- the resistance of the collector resistor R of the first stage transistor Tr should beproperly selectednot to exceed the collector loss of the third transistor Tr
- the timing capacitor is charged up in the direction for cutting off the transistor, then the voltage is applied thereto in the direction for discharging the thus charged charge to commence discharging and after a given time, said transistor will be made'conductive to determine a set time.
- the present inventiori enables the constituent elements to be reduced as much as possible, allows conventional semiconductors of reasonable price to be employed, and allows the timer to be mass-produced, thus enablingthe cost to be lowered.
- a set time can be determined to be several seconds through dozens of minutes and an excellent voltage characteristic and temperature characteristic can be obtained.
- the predetermined set time is not affected by the DC current amplification factor of the transistor, the operation of the relay and the open-circuit voltage, fluctuation in quality of the products can be reduced and the yield can be improved.
- the present invention further has some advantages that when it is not used for timer operation, the timer circuit and the load. are interrupted from the power supply, so that the waste of electric power can be prevented and possible errorneous operation owing to noises can be well prevented.
- An off delay timing circuit for use in an automoa voltage divider and a timing capacitor coupled hereto;
- a setting switch connectible to'a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage divider and forenergizing said load;
- timing capacitor means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias
- timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging saidtiming capacitor gradually through the timing resistor to said power'source to define a timing interval;
- circuit means connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and .during said timing interval;
- said set contact means including first, second and third set contacts
- said circuit means including leads connectible from the second and third set contacts to said source and load respectively for energizing said load from said source upon connection of the second and third set contacts, and means connecting said first set contact to said voltage divider and to the base of said second transistor for charging said timing capacitor from said source through said voltage divider and energizing said second transistor from said source when said setting switch is in its set condition, said setting switch further including means for interconnectingsaid first, second and third set contacts when said setting switchis in its set position.
- load control means responsive to said second transistor for controlling energization of a load
- a setting switch connectible to a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage dividerand for energizing said load;
- timing resistor and means connectingsame'to said timing capacitor and responsive to switching of the setting switch-from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval;
- circuit means connected to said setting switch and load control means and'connectible to' said load and source for isolating and preventing current draw by'the remainder of the timing circuit and said load from said source other than'when said settingswitch is in its set condition and during said timing interval;
- the setting switch including means defining a set condition for applying energizing potential from said source through said voltage divider to charge said timing capacitor and to the base of the second transistor for turning same on and for independently providing operating potential from said source to the timing resistor, to the current carrying paths .of the first-and second transistors and to said load, said setting switch further including means defining a resetconditionifor shorting the base path through the second transistor to block conduction thereof and said setting switch further havng means defining-a neutral condition for eliminating both the set and reset connections therethrough.
- An off delay timing circuit for use in an automobile comprising:
- timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval
- circuit means connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and during said timing interval;
- timing capacitor means responsive to the set condition of said setting switch for connecting said voltage divider-across said power source, said timing capacitor being connected at one side to said voltage divider for charging therefrom, said timing capacitor being connected at the other side thereof to one end of said timing resistor and to the base of said first transistor, means connecting the free end of said timing resistor for energization by said power source during the set condition of said setting switch and during said time interval, whereby current flow through said timing resistor biases said first transistor conductive during the set condition of the setting sw-itch and the charged condition of said timing capacitor biases the base of the first transistor to nonconduction thereafter and to the end of the timing interval.
- circuit of claim 4 including a diode interposed between said timing capacitor and the base of said first transistor for preventing reverse current flow through the base-emitter connection junction of said first transistor.
- An off delay timing circuit for use in anautomobile comprising:
- load control means responsive to said second transistor'for controlling energization of a load
- a setting switch connectible to a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage divider and for energizing said load;
- timing capacitor means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias; a timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval;
- circuit means connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and during said timing interval;
- a third transistor and means coupling same in sequence between first and second transistors for enhancing the DC current amplification factor of the second transistor said third transistor being direct coupled through its base-emitter circuit between said first and second transistors and having the collector thereof connectible to the power source, said timing resistor and timing capacitor being connected to the base of said first transistor, whereby provision of said third transistor allows raising of the value of said timing resistor and a consequent increase in the timed interval.
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Abstract
A timer apparatus includes a timer circuit utilizing the charging and discharging of a capacitor. The timer circuit comprises a timing capacitor adapted to charge in the direction for cutting-off a transistor at the setting time, a switch adapted to apply the voltage in the direction for discharging of said capacitor, and a transistor adapted to be turned conductive after a given time from the commencement of discharging. Said timer has excellent temperature and voltage characteristics without employing a Zener diode and FET, is hardly affected by the D.C. current amplification factor of said transistor and the open-circuit voltage of a relay and can determine a set time to be several seconds through dozens of minutes.
Description
United States Patent 1191 Takagi et a1. May 7, 1974' [54] DELAY TIMING CIRCUIT 3,600,610 8/1971 Kelsch 307 293 1 1 Katsuyuki Magi, 91w; 3:352:22? 1133; 111;'?.::i::::.... ...::::"33%72ZZ Miwa Minokamo, both of Japan U 2,923,963 2/1960 Chesson etall... 307/293 x Assignee: Kaisha To ai NO'ITIS X 3,059,129 10/1962 Tottlngham 307/293 X se'sakusho Nlshlkasugal'gun 3,215,856 11/1965 M0561 et al... 307/293 Pref Japan 3,633,050 1/1972 Zavac 307/293 [22] Filed: Mar. 30, 1972 P E S l D M n J rimary xaminertan ey i er, r. [21] Appl' 239572 Attorney, Agent, orFirmwoodhams, Blanchard and Flynn [30] Foreign Application Priority Data Mar. 31, 1971 Japan 46-19153 ABSTRACT I A timer apparatus includes a timer circuit utilizing the [52] U.S. CI. 307/293, 317/ 141 S, 328/131 charging and discharging of'a capacitor. The timer cir- [51 1 Int. Cl. t cuit omprises a capacitor adapted to charge in Field of Search 307/293, 10 LS; 3l5/82, he direction for cutting-off a transistor at the setting 315/77, 83; 317/141 S; 328/l29l3 time, a switch adapted to apply the voltage in the direction for discharging of said capacitor, and a transis- 1 References Cited tor adapted to be turned conductive after a given time UNITED STATES PATENTS from the commencement of discharging. Said timer 3,274,434 9/1966 Miller 315/82 has excellent temperature and voltage characteristics 3,287,608 11/1966 Pokrant 1 317/142 1 a t u p y g a Zener diode and is hardly 3,389,296 6/1968 0211111111.... 315/82 affected by the DC current amplification factor of 3,40 .3 2 8 Ec 3l7/14| S j said transistor and-the open-circuit voltage of a relay Roberts t t and can determine a et to be everal econds 3,544,838 12/1970 Carruth et al. 315/83 through dozens of i V 3,546,527 12/1970 Chunn et al. 315/82 3,582,715 6/1971 Traina 307/293 6 Claims, 4 Drawing Figures DELAY TIMING CIRCUIT The present invention relates to a timer device and more particularly to a timer device capable of determining a set time to be several seconds through dozens of minutes by utilizing semiconductor circuits.
Various types of prior art timers are known; for instance, a thermal-responsive type (bimetal) timer, a motor type timer, or an electronic (a semiconductor) type timer, etc In a timer for an automobile which utilizes a DC. source'as its power source (such as a timer for a defogger, a timer for an automatic choke, a warning timer for seatbelts, 'an off-delay timer for headlights and a timer for turning out a headlight after a given time of period has passed since an automobile stops), the voltage of its power source varies, so that a motor type timer cannot be utilized and a thermal-responsive timer has been used in most cases. Such conventional thermal-responsive type timers are subject to the influence of the ambient temperature and therefore apt to be inaccurate in setting a predetermined time, and it this transistor is increased and it becomes necessary to provide with a transistor having such a large collector loss as can counterbalance therewith, which would raise the cost. The fact that the transistor for driving a relay passes slowly through the active region means that at first on the exciting coil of the relay is applied a full source voltage, then such voltage gradually decreases to an open-circuit voltage near the end of the set time. Therefore, when the transistor is in the active region, a sufficient exciting voltage is not applied thereto thus, even with only a slight vibration, the relay may possibly be opened, although the set predetermined time has not yet passed.-
The present invention has been made to overcome the above-mentioned disadvantages. lt is therefore an object of the present invention to provide a timer which has excellent temperature and voltage characteristics without employing such expensive semiconductor elements as a Zener diode or a field-effect transistor and which is not affected by the DC. current amplification factor of the transistors employed and which is the further has a disadvantage that a set time for a subsequent operation is by far shortened due to the thermal inertia in cases where sequential operation is effected.
In recent years, as the cost of the semiconductor with the trip level of a Schmidt circuit or the threshold voltage between the base and the emitter ofa transistor itself, or upon comparison of the charging voltage applied from a power source to a timing capacitor through a timing resistor, with the trip level of a Schmidt circuit or the threshold voltage between the base and the emitter of a transistor. However, the above-mentioned circuits are easily affected by the variation of the source voltage and therefore necessitate employment of a Zener diode to improve the voltage characteristic. Furthermore, where such a timer is constructed to have a relatively long set time, the variation of the trip level of a Schmidt circuit or the capacitor voltage in the vicinity of the threshold voltage ofa transistor ismade less severe, so that the circuit is not only apt to be affected by noise but is sensitive to variations in ambient temperature and source voltage, so as to be liable to produce an error in the set time. Further, in
some such circuit structures, wherein the transistor for driving relays passes slowly through the active region in response to the slack variation of the capacitor voltage,
' age of the relay or the DC. current amplification factor of a transistor not only has fluctuation in the measured value, but also varies in the value with variation in theenvironmental temperature, thereby increasing the temperature-dependency of the set time and reducing the accuracy thereof. Another disadvantage, due to the fact that the transistor for driving a relay passes slowly through the active region is that the collector loss of open-voltage of the relay and capable of obtaining a set time of several seconds through dozens of minutes.
Another object of the present invention is to provide a timer which is adapted to expend no electric power when operates as a timer, due to the complete interruption of the circuits and loads from power sources, and to produce no erroneous operation due to external noise even with a high impedance circuit.
A further object of the present invention is to provide a timer which employs no elements other than the fundamental circuit elements for voltage regulation and temperature compensation as a timer, and which is capable of, in its performance, being fully stable against the variation of power supply voltage or ambient temperature in normal use and which can be manufactured at reasonable cost.
'The above, as well as still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of several specific embodiments thereof, especially when taken in conjunction with the accompanying drawings, wherein:
' According to the present invention, there is provided a timer device including a timer circuit utilizing the charging and discharging of a capacitor, comprising a timing capacitor adapted to charge in the direction for cutting-off a transistor at the time of setting; a switch adapted to apply a voltage in the direction for discharging the charged electric charge of said capacitor to cause such discharge; and said transistor adapted to be turned conductive after a predetermined period of time has passed from the commencement of discharging, thereby to determine a set time.
H0. 1 is a circuit diagram of one preferred embodiment of the present invention; I
FIGS. 2 through 4 are circuit diagramsof modified embodiments in accordance with the present invention.
Referring now to the drawings, and more particularly to FIG. 1 thereof, there is illustrated a circuit of one embodiment. of the invention. E designates a DC. power source, SW a switch for setting and resetting, R, a charging resistor, one terminal of which is connected with a setting contact P of the setting-resetting switch SW and the other terminal of which is connected with a positive electrode or a timing capacitor C. R: is a reone terminal of which resistor is connected with a +3 I power supply line and the other of which is connected with the junction of the negative electrode of said timing capacitor C and a base of a first stage transistor Tn. R, is a collector resistor one terminal of which is connected with the +B power source line and the other terminal of which is connected with both a collector of the first stage transistor Tr, and a base of a second stage transistor Tr The emitters of the first and the second stage transistors Tr, andTr are connected to the negative terminal of the power source E. R .is a base resistor, one terminal of which is connected with said contact P, of the setting-resetting switch SW and theother terminal of which connects with the base of the second stage transistor Tr Y is a relay for controlling a load current and includes a coil Y,, one terminal of which is connected with the +8 power supply line and the other terminal'of which connects with a collector of the second stage transistor Tr Relay y further includes a contact y, one terminal of which is connected with a positive terminal of the power supply E and the other terminal of which connects with the +B,power supply line. D, is'a diode, for preventing a counter electro-motive force connected in parallel with the coil Y, of said relay Y. Concerning the setting-resetting switch SW, a setting contact P is connected with the positive terminal of the power supply E and a setting contact P5 connects with the +8 power supply line, respectively, while a resetting contact P, is connected with the base of the second stage transistor Trand another resetting contact P connects with the negative terminal of the power supply E, respectively. L is a load having a terminal connected with the negative terminal of the power supply and another terminal connected with the +B power supply line.
The operation of the above-mentioned circuit will be explained in detail as follows. When the movable contact PM the setting-resetting switch SW is turned to the setting side contacts P,, P and P,,, the positive terminal of the power supply E is connected with the.
. +B power supply line of said circuit. Therefore, the
feed to the load L is commenced and the charging current flows from the contact P, through the charging resistor R,, timing capacitor C and the base-emitter of the first stage transistor Tr, to charge the timing capacitor C it up to the following voltage.
where V0 is the charging voltage of a timing capacitor C,.Vd the base-emitter forward voltage of the transistor Tr, and E the power supply voltage.
Since there is determined and accordingly said transistor Tr, is made conductive to excite the coil Y, of the relay Y and close the contact y. Then, when the setting-resetting switch SW is released, the movable contact P of said switch SW is returned to a neutral position and the' switch side of the charging resistor R, is disconnected from the power supply E, so that the positive electrode side of the timing capacitor C ismaintained nearly at the earth potential. At the same time, the voltage at thebase of the first stage transistor Tr, becomes Vo and said transistor Tr, is cut off, while the second stage transistor Tr,
maintains the conductive condition by the current flowing through the collector resistor R even if no current flowsthrough the base resistor R thus maintaining the relay Y closed. I On the other hand, upon releasing the settingresetting switch SW, the base potential of the first stage second stage transistor Tr, through the base resistor R transistor Tr,, which is reversely biased to *Vo, increases towards the power supply voltage by the current supplied from the +8 power supply line through timing resistor R Thus, when thebase potential becomes thebase-emitter threshold voltage Vd of the transistor Tr,, said first stage transistor ,Tr, becomes conductive, and the collector of said transistor Tr, becomes nearly the earth potential. Resultantly, the second stage transistor Tr, is cut off, and the relay Y is made'open to interrupt the current to the load L, thereby terminating'one delay operation. When the timer operation comes to an end, the contact y: of the relay Y is opened andboth the load L and the timer circuit itself will be completely separated from the power supply E, as the movable contact 'P of the setting resetting switch SW stands in the neutral'position.
.After the setting-resetting switch SW has been thrown into the setting side, if it isrequired'for some reasons to reset before the set time has been passed, the movable contact P of the setting-resetting switch SW is thrown into the resetting side contacts P, and P to where. t
a R /R, +R b 12 /12, +R, +R, Vd, the base-emitter threshold voltage of the first stage transistor Tr, Vd the base-emittervoltage of the second stage transistor Tl'g in the conductive condition E power supply voltage When the temperature coefficient of the timing resistor R and the timing capacitor C is equal to zero, a
pression it will be seen that the set time will hardly be affected by the variation of the power supply voltage and the environmental temperature. In the worst case when the power supply voltage varies from to V, and the environmental temperature varies in all the domain between 30C through 70C, only 4% of difference-will be produced. Therefore, without employing such expensive semiconductor elements as a 'Zener diode for compensating the voltage characteristic, a thermistor for compensating the temperature characteristic and a semiconductor varistor, a very stable set time in practical use will be obtained and a timer with high accuracy will be provided. W v 7 It is usual that the conventional silicon transistor has a base-emitter reverse withstand voltage (reverse breakdown voltage) of 5 7V. In the circuit of the above-mentioned embodiment of the present invention, in case the power supply voltage is 12V, R, and R are so determined that the constant a=0.4, the-first stage transistor Tr, does not enter the Zener domain and functions satisfactorily when the base of said transistor Tr, is reversely biased immediately after setting. But in case the constant a is selected to be a value of nearly 1, two times or more of delaytimes will be obtained with the same values of the timing resistor R and timing capacitor C. Thus, in order to obtain a long delay time, in some cases it is more convenient to select the constant a to be a value of nearly 1, rather than to double the size of the timing capacitor C. Then, in order to select the constant a to be a value of nearly 1, a first stage transistor Tr, with a base-emitter withstand voltage higher than the power supply voltage should be employed. Otherwise, a diode D with a withstand voltage higher than the power supply voltage should be connected in series with both the positive electrode of the timing capacitor C and the base of the first stage transistor Tr, as shown in FIG. 2, thereby to operate in a preferable condition regardless of the value of the constant a.
' Referring to FIG. 3, a circuit diagram of another embodiment of the present invention will be explained. The base of a third transistor Tr, is connected with the collector of the first stage transistor Tr, shown in the circuit of FIG. 1, and the collector of said transistor Tr, is connected with the +8 power supply line and the emitter thereof is connected with the base of the second stage transistor Tr In the circuit of FIG. 1, in case the power supply voltage is 12V and the exciting current of the relay Y is I00 mA, the maximum value of the timing resistor R allowed to be employed is at most 2 through 3 megohms, so that so long set time cannot be expected. On the other hand, in the circuit of FIG. 3, the third transistor Tr, is additionarily employed and the DC. current amplification factor of the second stage transistor Tr will be increased equivalently, thereby raising the base resistance R, (timing resistance) of the first stage transistor Tr,.
In the circuit diagram of another embodiment in FIG. 4, a diode D is connected between the first stage transistor Tr, and the timing capacitor C, thereby enabling to function satisfactorily regardless of the value of the Y constant a.
By adding the third transistor Tr, as shown in FIGS. 3 and 4, in case the relay Y requiring the exciting current of mA as mentioned above is used, the timing resistor R of 100 megohm can be employed, thus enabling a timer of dozens of minutes of set time to be realized.
the second stage transistor Tr rises to increase the loss of said transistor Tr In the circuit of the present embodiment, as the current limiting resistoris not connected with the collector or the emitter of the third transistor Tr (for the purpose of lowering the cost as much as possible), there remains necessity that the resistance of the collector resistor R of the first stage transistor Tr, should beproperly selectednot to exceed the collector loss of the third transistor Tr In the present invention as mentioned above, the timing capacitor is charged up in the direction for cutting off the transistor, then the voltage is applied thereto in the direction for discharging the thus charged charge to commence discharging and after a given time, said transistor will be made'conductive to determine a set time. Owing to such a construction, the present inventiori enables the constituent elements to be reduced as much as possible, allows conventional semiconductors of reasonable price to be employed, and allows the timer to be mass-produced, thus enablingthe cost to be lowered. Further according to the present invention, with a simple structure of the circuit, a set time can be determined to be several seconds through dozens of minutes and an excellent voltage characteristic and temperature characteristic can be obtained. Moreover, as the predetermined set time is not affected by the DC current amplification factor of the transistor, the operation of the relay and the open-circuit voltage, fluctuation in quality of the products can be reduced and the yield can be improved. The present invention further has some advantages that when it is not used for timer operation, the timer circuit and the load. are interrupted from the power supply, so that the waste of electric power can be prevented and possible errorneous operation owing to noises can be well prevented.
While there have been described and illustrated several specific embodiments of the invention, it will be clear that variations in the details of the embodiments specifically illustrated and described may be made without departing from the true spirit and scope of the invention as defined in the appended claim.
What is claimed is:
1. An off delay timing circuit for use in an automoa voltage divider and a timing capacitor coupled hereto; i
a setting switch connectible to'a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage divider and forenergizing said load;
means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias;
a timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging saidtiming capacitor gradually through the timing resistor to said power'source to define a timing interval;
circuit means-connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and .during said timing interval;
said set contact means including first, second and third set contacts, said circuit means including leads connectible from the second and third set contacts to said source and load respectively for energizing said load from said source upon connection of the second and third set contacts, and means connecting said first set contact to said voltage divider and to the base of said second transistor for charging said timing capacitor from said source through said voltage divider and energizing said second transistor from said source when said setting switch is in its set condition, said setting switch further including means for interconnectingsaid first, second and third set contacts when said setting switchis in its set position. 1 v
2. The circuit of claim 1, including conductor mean connecting said third set contact in series with said load control means and second transistor for allowing current flow therethrough when the setting switch is in its set condition and also connecting said third set'contact in series with said first transistor, said third set contact also being connected to said timing capacitor through said timing resistor, said load control means having a contact closable upon energization thereof for energizing said third set contact from the power source even when said setting switch is not in its set position 3. An off delay timing circuit for use in an automobile, comprising:
first and second transistors of the same polarity and means connecting same in sequence for inverted operation with respect to each other;
load control means responsive to said second transistor for controlling energization of a load;
a voltage divider and a timing capacitor coupled thereto;
a setting switch connectible to a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage dividerand for energizing said load;
, means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias;
a timing resistor and means connectingsame'to said timing capacitor and responsive to switching of the setting switch-from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval; 1
circuit means connected to said setting switch and load control means and'connectible to' said load and source for isolating and preventing current draw by'the remainder of the timing circuit and said load from said source other than'when said settingswitch is in its set condition and during said timing interval;
the setting switch including means defining a set condition for applying energizing potential from said source through said voltage divider to charge said timing capacitor and to the base of the second transistor for turning same on and for independently providing operating potential from said source to the timing resistor, to the current carrying paths .of the first-and second transistors and to said load, said setting switch further including means defining a resetconditionifor shorting the base path through the second transistor to block conduction thereof and said setting switch further havng means defining-a neutral condition for eliminating both the set and reset connections therethrough. v
4. An off delay timing circuit for use in an automobile, comprising:
first and second transistors of the same polarity and means connecting same in sequence for inverted transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias; a v
a timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval;
circuit means connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and during said timing interval;
means responsive to the set condition of said setting switch for connecting said voltage divider-across said power source, said timing capacitor being connected at one side to said voltage divider for charging therefrom, said timing capacitor being connected at the other side thereof to one end of said timing resistor and to the base of said first transistor, means connecting the free end of said timing resistor for energization by said power source during the set condition of said setting switch and during said time interval, whereby current flow through said timing resistor biases said first transistor conductive during the set condition of the setting sw-itch and the charged condition of said timing capacitor biases the base of the first transistor to nonconduction thereafter and to the end of the timing interval.
5. The circuit of claim 4, including a diode interposed between said timing capacitor and the base of said first transistor for preventing reverse current flow through the base-emitter connection junction of said first transistor.
6. An off delay timing circuit for use in anautomobile, comprising:
first and second transistors of the same polarity and means connecting same in sequence for inverted operation with respect to each other;
load control means responsive to said second transistor'for controlling energization of a load;
a voltage divider and a timing capacitor coupled thereto;
a setting switch connectible to a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage divider and for energizing said load;
means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias; a timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval;
circuit means connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and during said timing interval;
a third transistor and means coupling same in sequence between first and second transistors for enhancing the DC current amplification factor of the second transistor, said third transistor being direct coupled through its base-emitter circuit between said first and second transistors and having the collector thereof connectible to the power source, said timing resistor and timing capacitor being connected to the base of said first transistor, whereby provision of said third transistor allows raising of the value of said timing resistor and a consequent increase in the timed interval.
Claims (6)
1. An off delay timing circuit for use in an automobile, comprising: first and second transistors of the same polarity and means connecting same in sequence for inverted operation with respect to each other; load control means responsive to said second transistor for controlling energization of a load; a voltage divider and a timing capacitor coupled hereto; a setting switch connectible to a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage divider and for energizing said load; means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias; a timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval; circuit means Connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and during said timing interval; said set contact means including first, second and third set contacts, said circuit means including leads connectible from the second and third set contacts to said source and load respectively for energizing said load from said source upon connection of the second and third set contacts, and means connecting said first set contact to said voltage divider and to the base of said second transistor for charging said timing capacitor from said source through said voltage divider and energizing said second transistor from said source when said setting switch is in its set condition, said setting switch further including means for interconnecting said first, second and third set contacts when said setting switch is in its set position.
2. The circuit of claim 1, including conductor means connecting said third set contact in series with said load control means and second transistor for allowing current flow therethrough when the setting switch is in its set condition and also connecting said third set contact in series with said first transistor, said third set contact also being connected to said timing capacitor through said timing resistor, said load control means having a contact closable upon energization thereof for energizing said third set contact from the power source even when said setting switch is not in its set position.
3. An off delay timing circuit for use in an automobile, comprising: first and second transistors of the same polarity and means connecting same in sequence for inverted operation with respect to each other; load control means responsive to said second transistor for controlling energization of a load; a voltage divider and a timing capacitor coupled thereto; a setting switch connectible to a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage divider and for energizing said load; means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias; a timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval; circuit means connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and during said timing interval; the setting switch including means defining a set condition for applying energizing potential from said source through said voltage divider to charge said timing capacitor and to the base of the second transistor for turning same on and for independently providing operating potential from said source to the timing resistor, to the current carrying paths of the first and second transistors and to said load, said setting switch further including means defining a reset condition for shorting the base path through the second transistor to block conduction thereof and said setting switch further havng means defining a neutral condition for eliminating both the set and reset connections therethrough.
4. An off delay timing circuit for use in an automobile, comprising: first and second transistors of the same polarity and means connecting same in sequence for inverted operation with respect to each other; load control means responsive to said second transistor for controlling energization of a load; a voltAge divider and a timing capacitor coupled thereto; a setting switch connectible to a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage divider and for energizing said load; means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias; a timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval; circuit means connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and during said timing interval; means responsive to the set condition of said setting switch for connecting said voltage divider across said power source, said timing capacitor being connected at one side to said voltage divider for charging therefrom, said timing capacitor being connected at the other side thereof to one end of said timing resistor and to the base of said first transistor, means connecting the free end of said timing resistor for energization by said power source during the set condition of said setting switch and during said time interval, whereby current flow through said timing resistor biases said first transistor conductive during the set condition of the setting switch and the charged condition of said timing capacitor biases the base of the first transistor to nonconduction thereafter and to the end of the timing interval.
5. The circuit of claim 4, including a diode interposed between said timing capacitor and the base of said first transistor for preventing reverse current flow through the base-emitter connection junction of said first transistor.
6. An off delay timing circuit for use in an automobile, comprising: first and second transistors of the same polarity and means connecting same in sequence for inverted operation with respect to each other; load control means responsive to said second transistor for controlling energization of a load; a voltage divider and a timing capacitor coupled thereto; a setting switch connectible to a power source and including set contact means actuable to a set condition for charging said timing capacitor through said voltage divider and for energizing said load; means connecting said timing capacitor to said first transistor for applying the resulting charge voltage on said capacitor to said first transistor as a reverse bias; a timing resistor and means connecting same to said timing capacitor and responsive to switching of the setting switch from said set condition for discharging said timing capacitor gradually through the timing resistor to said power source to define a timing interval; circuit means connected to said setting switch and load control means and connectible to said load and source for isolating and preventing current draw by the remainder of the timing circuit and said load from said source other than when said setting switch is in its set condition and during said timing interval; a third transistor and means coupling same in sequence between first and second transistors for enhancing the DC current amplification factor of the second transistor, said third transistor being direct coupled through its base-emitter circuit between said first and second transistors and having the collector thereof connectible to the power source, said timing resistor and timing capacitor being connected to the base of said first transistor, whereby provision of said third transistor allows raising of the value of said timing resistor and a consequent increase in the timed interval.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1915371 | 1971-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US3809927A true US3809927A (en) | 1974-05-07 |
Family
ID=11991467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US00239572A Expired - Lifetime US3809927A (en) | 1971-03-31 | 1972-03-30 | Delay timing circuit |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | US3809927A (en) |
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| US3973140A (en) * | 1974-01-29 | 1976-08-03 | The Lucas Electrical Company Limited | Control circuits for vehicle rear window heaters |
| US4833558A (en) * | 1986-04-25 | 1989-05-23 | Archive Corporation | Head positioning assembly |
| US4857757A (en) * | 1984-06-29 | 1989-08-15 | Omron Tateisi Electronics Co. | Drive circuit for a two layer laminated electrostriction element |
| USRE33661E (en) * | 1986-04-25 | 1991-08-13 | Archive Corporation | Head positioning assembly |
| US6573619B2 (en) * | 2001-02-05 | 2003-06-03 | Yi-Ho Chin | Controllable power-economizing extension sockets |
| CN104863677A (en) * | 2014-02-24 | 2015-08-26 | 珀金斯发动机有限公司 | Electrical Bypass Circuit |
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