US3787834A

US3787834A - Liquid crystal display system

Info

Publication number: US3787834A
Application number: US00319416A
Authority: US
Inventors: J Elliott
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1972-12-29
Filing date: 1972-12-29
Publication date: 1974-01-22
Anticipated expiration: 1991-01-22

Abstract

A system for displaying information on a large liquid crystal display unit, for example a 1,600 character unit. The unit is divided into separately addressed matrices of characters. A particular row in each matrix is addressed on a time-multiplex basis during each display cycle. During the succeeding cycle, the succeeding row in each matrix is addressed and so on. The multiplexing sequence uses the slow excitation time and slower de-excitation time of the liquid crystal element to advantage.

Description

Xi? 39787983 1- E ,3 United States P 3,787,834 Elliott Jan. 22, 1974 [54] LIQUID CRYSTAL DISPLAY SYSTEM 3,716,290 2/1973 Borel et al 315/169 TV 3,716,658 2/1973 Rackman [75] Invent 12 3 EH10, Hopewell 3,747,073 7/1973 Sharpless 340/324 M [73] Assignee: International Business Machines Primary Examiner-David L. Trafton Corp r Armonk, Attorney, Agent, or FirmThomas F. Galvin [22] Filed: Dec. 29, 1972 21 Appl. No.: 319,416 [57] ABSTRACT A system for displaying information on a large liquid [52] us Cl." 340/324 M 315/169 R 315/169 TV crystal display unit, for example a 1,600 character 350/160 LC unit. The unit 1s divided into separately addressed ma- [51 Int. Cl. G08b 5/36 "ices of characters A pamcular row m each mam) [58] Field of Search34O/324 M; 315/169 R 169 TV; addressed on a t1me-multiplex basis during each dis- 350/160 LC play cycle. During the succeeding cycle, the succeeding row in each matrix is addressed and so on. The

[56] References Cited multiplexing sequence uses the slow excitation time UNITED STATES. PATENTS and slower tie-excitation time of the liquid crystal element to advantage. 3,614,769 10/1971 Coleman et a1. 340/324 M 3,614,771 10/1971 Band et al. 340/324 M 16 Claims, 7 Drawing Figures SET 4 (8 X 40 ARRAY) 3787834 QR metro/3am PAlEmfnamzzrsm SHEEI 1 DF 4 PARALLEL T0 SERIAL CONVERTER Iaos CHAR.

SHIFT REGISTER I SET 1 (8 X 40 ARRAY) SHIFT REGISTER 5 FIG. I

DATA BIT OUT TO DISPLAY SHIFT REG.2D

l I r M -FF6 LOAD o SHIFT PARALLEL DATA IN FROM ROS T l y FIG.4

FIG.5

SHEEI 2 OF 4 FROM SHIFT REGISTER 20 105' 106' FIGZ 104'109' H6 116 120 FIG.2A

PATENTED JAN 2 2 I974 ACTIVATE SET 5 ROW DRIVER .LOAD SHIFT REG.5

ACTIVATE SET 4 ROW DRIVER LOAD SHIFT REC.4

ACTIVATE SET 5 ROW DRIVER LOAD SHIFT REC?) ACTIVATE SET 2 ROW DRIVER LOAD SHIFT REC.2

ACTIVATE SET I ROW DRIVER LOAD SHIFT REC. I

ADVANCE ROW SEL. COUNTER 34 I MH Z CLOCK 29 ADVANCE COUNTER 2B ADVANCE ROS ADDR. DECODE 4I LOAD P/S CONV. I8

LOAD SHIFT REC.I

ADVANCE CHARACTER SELECT COUNTER 3O ADVANCE SET SEL. COUNTER 52 ACTIVATE ROW I DRIVER 54 LDAD SHIFT REC.2

PIC-3.6

SHEET '4 "OF 4 TIME IMILLISECONDS) RowtTLj ROW 11] ROVI2UROWZ1] RowTLl ROIIISU ROWGU ROW? LjRows l I I I I I I I I e 17 1a 19 119 721 TIME (MICRO-SECONDS) 1 LIQUID CRYSTAL DISPLAY SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to systems for generating symbols on display devices having slow response times. In particular this invention relates to a display unit using a large number of liquid crystal display devices.

2. Description of the Prior Art As compared to other display technologies, such as the cathode ray tube, light emitting diodes and the gas panel, liquid crystal displays offer the advantages of low cost, low power and large character size. The raw material of the liquid crystal is very inexpensive and the packaging has posed few problems with todays technology. The power requirements of liquid crystal displays are in the microampere range whereas light emitting diodes use milliamperes and the cathode ray tube uses much more. However, up to the present time the commercial applications of liquid crystal displays have been confined to small display units such as watches and portable data terminals which require only a few individual characters. A principal obstacle to the development of larger arrays which would be competitive with the cathode ray tube, for example, is the requirement of individual drivers for each resolution element in the array. For example, a typical numeric display of digits, with a eight segments per digit, requires eighty connections to the segments and 80 semiconductor drivers. At the present state of the art this number of interconnects is prohibitive to the fabrication of a larger array and the requirement of one driver per segment substantially increases the cost of the array unit.

The obvious solution to this problem, which has occurred to others in this field, is for the development of a practical technique for multiplexing alarger array, thereby reducing the number of interconnections and the number of drivers. However, up to the present time a feasible multiplexing technique has not been discovered. Due to the slow excitation (rise) time and the even slower de-excitation (fall) time of the commercially available liquid crystal materials, the standard X-Y matrix addressing is ineffective. For example, a recent paper at a conference of the Society of Information Display by Stein and Kashnow entitled Recent Advances in Frequency Coincidence Matrix Address- SUMMARY OF THE INVENTION These and other objects are achieved by providing a liquid crystal display unit comprising a plurality of-matrices, each matrix being addressed by a separate buffer register. Digital information representative of the sym-' bols is stored sequentially in the buffer registers and a particular row of each matrix is sequentially addressed on a time-multiplex basis by its associated buffer register. Duringthe next display cycle, the buffer registers are sequentially reloaded and the next row in each matrix is similarly addressed. The entire display unit is addressed once during the de-excitation time of a liquid crystal element.

In general terms, if each matrix in the unit contains N rows, then during a single display cycle the ith row in each matrix is addressed on a time-multiplex basis, where l s i s N. During the next cycle the ith +1 row in each matrix is similarly addressed.

In the preferred embodiment the display unit is associated with a random access memory which has sufficient storage locations for storing information signals representative of all symbols to be displayed on the liquid crystal display unit. The storage unit might be controlled and accessed by a central processor of a computer system either directly or by means of a communications link. Each display element in the unit comprises 18 bar and dot segments for an alphanumeric display; other conventional character fonts could be used. A character generator, which is preferably a standard read-only storage (ROS) memory, contains digital information on predetermined segments of each character which can be displayed on the display unit. Upon receiving signals from the random access memory, the ROS generates the digital information representative of the characters to be displayed. The characters to be displayed on a particular row in each matrix are loaded from the ROS to a shift register unique to each matrix under the, control of a timing and control system. Under the direction of the control unit each shift register drives the liquid crystal characters on a timemultiplex basis in a particular row of each matrix. During the next display cycle, the shift registers are sequentially reloaded with characters'to be displayed in the next succeeding row in each matrix and the multiplexing continues.

The high speed of operation of the electronic elements such as the RAM, ROS, and shift registers as compared to the response of the liquid crystal devices allows a large number of characters to be addressed without any flicker.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram showing a system embodying the present invention.

FIGS. 2 and 2A are illustrations of the preferred liquid crystal segmented character shown in FIG. 1.

FIG. 3 is a detailed diagram of the timing and control circuit illustrated in FIG. 1.

FIG. 4 is a detailed diagram of the parallel-to-serialconverter shown in FIG. 1.

FIG. 5 is a circuit diagram of the row and column drivers which select the liquid crystal segment chosen for display.

FIG. 6 is a timing diagram showing the relationship among the timing and control signals generated by the timing and control circuit for controlling the display.

DESCRIPTION OF THE PREFERRED EMBODIMENT which is addressed in the display. The parallel digital signals from the character generator 16 are transmitted across cable 17 to a parallel to serial (P/S) converter 18 which transmits a bit at a time to shift registers 20. Each shift register is associated with a corresponding one of the five sets of liquid crystal display devices under control of a timing and control circuit 12.

As illustrated the display unit is a matrix of characters 11. One of the principal features of this invention is that the matrix is divided into a number of sets of smaller matrices, which are denoted as Set 1, Set 2, Set 3, Set 4 and Set 5. For simplicity and conciseness only sets 1 and sets 5 are illustrated. Each of the sets comprise an eight-by-forty matrix ofliquid crystal characters 11. The particular number of rows and columns which comprise each matrix set of characters is dependent on the excitation and de-excitation time of the particular liquid crystal material used, as well as the speed with which shift registers 20, RAM 14, ROS 16 and the other electronic circuits can operate. The development of these numbers will be described in more detail in a succeeding section of this specification.

Shift registers 20, which temporarily store digital information received from P/S converter 18 via connection 19, act as buffers for the data as well as a means for transmitting the digital information to the individual segments of each character in the associated matrix set. Integral with each shift register are column drivers which drives the electrodes of the characters to select the selected segments of each character. The selection of which particular shift register 20 is loaded by the P/S converter is made by the application of a pulse from the timing and control means through lines SR1, SR5, only one of which is operative to actuate its associated shift register at a given time.

Memory 14 may be any system which is capable of storing information received from an external source and reading out the stored information upon a signal from an external source. The best type of storage system for this purpose in modern technology is a random access memory (RAM) which is made up of semiconductor storage devices and associated read/write circuits. Such a memory is by now well-known in the field and a further description of its operation is deemed to be unnecessary at this stage. Those interested in a more complete description of a random access memory are referred to the article in Computer Design entitled A High Performance LSI System by Richard W. Bryant et aI., July 1970, pages 71-77. The number of required storage locations within the memory 14 is dependent on the number of characters within array 10. In the preferred embodiment there are five sets of eight-by-forty character matrices for a total of l,600 characters, each character comprised of IS segments.

Each character code in RAM 14 comprises from six to eight bits for aIph-numeric data and the size of the memory in the present system would be at least 9,600 hits. Thus, a commercially available memory of 12K bits would easily satisfy the requirements of the present display system.

Character generator 16 receives coded information stored at identified locations in memory 14 corresponding to particular locations in display unit 10. The data is transmitted along six lines in cable 15. The coded digital information in the RAM 14 is representative of a particular alphabetic or numeric character symbol which is to be displayed on one of the display devices 11. The coded digits address particular locations within character generator 16 which contain digital representations of each different character or symbol which may be displayed on each liquid crystal display device. For an l8 segment character, such as is comtemplated in the preferred embodiment of this invention, the character generator would transmit 18 bits, each of which is representative of a particular segment within the character. For this purpose, a read only storage (ROS) memory system is ideal. As is commonly known, the ROS is a memory which stores information permanently, that is, the information cannot be altered electronically once the memory has been fabricated. In the preferred embodiment of this invention each addressable sector of the ROS contains storage locations for 18 bits of information; each addressable sector represents a particular character or symbol which may be displayed in the display unit 10. The sectors of ROS 16 are individually addressable by six bits from RAM 14 and two bits from Timing and Control Unit 12. The number of bits from RAM 14 required for this purpose is, of course, dependent on the size of the ROS and the number of symbols which it is desired to generate. In an alphanumeric display unit such as is comtemplated by the present invention there are in excess of 40 characters and symbols which it might be desired to display. Hence, six address lines 15 are necessary. Commercially available ROS units are not fabricated with IS output lines. Most commonly, eight output lines are available. In this preset embodiment, six output lines 17 are used; and six of the IS binary representations of a character are generated by ROS 16 per cycle.

As previously mentioned, the six bit parallel output of ROS character generator 16 is connected to P/S generator 18 for transmission of a bit at a time to the shift registers 20. The details of converter 18 are discussed further with regard to FIG. 4.

Timing and control circuit 12 synchronizes the operation of the system by means of a cyclic clock and also controls the addressing of the particular characters, rows and sets which comprise display unit 10. Data fetching is accomplished via

cabling

24, 25 and 26 which addressing RAM 14, ROS 16 and P/S converter 18, respectively. RAM 14 contains sufficient storage locations for storing all of the information which would appear on display unit 10 at any given time. Normally, data from a central processor or other communications device (not shown) is loaded into the RAM until all of the data which are digital representations of the alphanumeric symbols to be displayed on unit 10 are contained within RAM 14. Under control of circuit 12, RAM 14 generates signals to ROS 16 representative of the symbol to appear at a particular character 11. ROS 16 then generates binary outputs for each segment within the character to form a symbol. These bits are converted to serial transmission in P/S converter 18 and transmitted to one of the shift registers 20. The selection of which particular shift register is to be loaded is under the control of circuit 12 via the shift lines denoted as SRl, SR5. The particular row of devices 11 which are to be excited by the information in the shift register is controlled via row driving lines R1, R2, R7, R8 from unit 12. The particular operation and multiplexing techniques of this invention will be discussed in greater detail in a succeeding section of this specification with regard to FIGS. 3 and 6.

Referring now to FIGS. 2 and 2A, there are shown front surfaces and side-sectional views, respectively, of

the segments which comprise the basic character element of each liquid crystal display device 11. Although other types of segmented characters could be used, the preferred character illustrated in FIG. 2 offers a great variety of possible symbols for a relatively few number of segments. The segments, each of which are denoted by numerals from 101 to 118, are preferably fabricated from tin oxide or some other transparent conductive material. The fabrication techniques are standard in the industry and usually consist of masking a plate of the material and etching away the material at undesired locations to form the individual segments. Each

segment

101, 102, 117, 118 has connected thereto a conductive wire or land which is unique to that segment. For example, wire 101' is connected to segment 101. As shown in the drawing, the segments are driven by means of signals from the shift register via cable 21. Each wire land contacts a particular segment of an associated character in each row of the set. Thus in the present embodiment, wire 101 contacting segment 101 of the first character in row 1 of set 1, for example, also forms ohmic contact with segment 101 in every other one of the eight characters in the first column of set 1. The same holds for the other segments and, in general, a single wire connection from a shift register makes electrical contact to eight associated segments in the same column of a set of devices.

For each eight by 40 device matrix, there are 720 wires in cable 21 (FIG. 1) from a Shift Register 20 to the character segmentsLWithin each shift register 20 are 720 register circuits and column drivers, one for each of the wires in cable 21. These circuits will be further discussed with regardto FIG. 5. v

As shown in FIG. 2A, all of the segments are formed on a relatively thinfilm of silicon dioxide 123 which, in turn, interfaces with a relatively thick sheet of glass 120. Both the glass and the silicon dioxide are transparent, as are the character segments. The liquid crystal material 122 is sandwiched between the individual segments and the oxide film 123 and a common electrode 124 which overlies another glass plate 121. When a character is addressed, the common electrode is driven by a voltage source from control circuit 12, and the segments which must be energized to form the selected symbol are driven by a separate voltage source in the shift register. The potential difference activates liquid crystal material 122. The particular liquid crystal material 122 which is used is relatively unimportant to the scope of the present invention. The number of characters and the size of the display unit depends on the excitation and de-excitation time of the material. However, a wide range of material compositions will perform quite well in this invention. One material which has been found suitable is a mixture on a 50 percent basis of EBBA and MBBA to which are added minute quantitles of a conductivity conforming additive (dopant) such as hexamethyl pyridinium bromide and a surface aligning agent such as paa-methoxy benzylidine paraamino phenol.

The size of the character is preferably 250 mils high by 180 mils wide. A complete 40 X 32 display is apspacing between the segments and the wires to prevent cross-talk, it has been found that two levelwiring arrangement is better than a single level. Thus in FIG. 2A,

wires

104', 109, 101, 105 and 106' are on the same level as the segments. On the other hand, wires 116, 110', 113' and 117' are on a second level on the surface of glass 120 and covered by oxide layer 123. This has been found to be an efficient method of providing adequate spacing between the leads which is easily accomplished using state of the art techniques familiar to the display industry. The wire lands themselves are typically copper or aluminum which are 1.50 mils wide on 2 mil spacing.

FIG. 3 is a detailed diagram showing the circuits of timing and control block 12 of FIG. 1. The timing and control system performs substantially all of the clock ing and synchronization which is required in the present invention to provide an operative liquid crystal display unit. Character select block 30, set select block 32 and row select block 34 are counters which sequentially address the memory 14 for generating information character-by-character for the corresponding rows and sets of the display unit 10. Set decoder 38 is responsive to the outputs of character select counter 30 via cable 61 to advance set select .counter 32 via line 64 when a full row of 40 characters has been transmitted through the system into the display unit. Set select counter 32 then advances to the same row in the next set. In a similar fashion, when counter 32 indicates via cable 62 to row decoder 40 that a corresponding row of 40 characters in each set have been addressed, then row select counter 34 is advanced via line 66 by one unit through row decoder 40 and the next row is selected in RAM 14.

Gating of RAM 14 through cable 24 for these purposes is accomplished by OR function blocks 31, 33 and 35 which are responsive to

counters

30, 32 and 34, respectively. RAM 14 is also responsive to signals along cable 60 from an T/O or CPU system (not shown) for addressing the RAM, as when data is being stored in RAM 14.

The addressing of ROS character generator 16 is accomplished through connections 25 by a two-bit address register 36. Address register 36 is provided because ROS 16 generates only six of the 18 segment bits at-a time, thereby requiring three coded signals from ROS Address Decoder 41 for each symbol. F Decoder 42 cooperates with decoder 41 to activate the inputs of P/S converter 18 to receive each six-bit byte from ROS 16. The gating of one bit of data from P/S converter 18 is accomplished during each cycle of clock 29 via line 70..

As previously mentioned, system synchronization is supplied by clock 29 which advances an 18-bit segment counter 28 one bit for each cycle. After each 18 cycles counter 28, in conjunction with a down level pulse from inverter 44, advances character select counter 30 through NAND gate 45. Segment counter 28 also provides addressing signals to ROS Address Decoder 4] and F Decoder 42 via cable 63.

The addressing and driving of the rows of characters in display unit 10 are accomplished by row drive control circuit 50 which functions as a means for selecting a particular single row in each set which are to be sequentially addressed. and for impressing an input voltage on the row at the common electrode of each character so thateach character responds to signals and the character segments received from the shift registers 20. A set of ring counters 51 is provided, one counter for each matrix set. The ring counters are responsive to signals from row decoder 40 via cable 67 to advance a single row, to the ith 1 row, when a particular ith row in each set has been driven. The outputs of the ring counters are connected to true/complement (T/C) generators 52 which are necessary for signaling row drivers 54 through cabling 53. The particular configuration of the row drivers will be discussed in greater detail with respect to FIG. 5.

The function and operation of ring counters and T/C generators are wellknown to those of skill in the art. The ring counter acts to provide a single set output from one of the leads only; and an impulse from cable 67 will advance the output one step. At the completion of eight cycles the first output is again set and the set state progresses one stage at a time. A T/C generator, otherwise known as a two-rail converter, generates a true and a complement output of a signal on separate lines.

The particular matrix set of display unit 10 which is to be addressed at any given instant is determined by Set Decoder 38 which activates one of five shift registers through AND gates 39 via cabling 65.

The operation of the timing and control unit illustrated in FIG. 3 will be more fully discussed in a later section of this specification in conjunction with the timing diagram of FIG. 6.

Parallel to serial converter 18 is a shift register with parallel data input from cable 17 from the character generator 16. The output from converter 18 is a single high-order bit. As shown in FIG. 4, parallel data from ROS I6 is loaded into the flip-flops of the shift register. The number of flip-flops depends on the number of parallel bits output from character generator 16. In the present embodiment, the digital representations of a character symbol are transmitted in six-bit bytes from generator 16 and six flip-flops are required in converter 18. The shift pulse from line 70 is received directly from the system clock and thereby transmitting a data bit to the selected display shift register during every clock cycle. The load pulse on line 72 which is received from F decoder 42 (FIG. 3), occurs once every six clock cycles.

Turning now to FIG. 5 there are shown the driving circuits which energize the liquid crystal segments of a character 11. Shift registers 20 include a shift circuit for each of the 720 character segments contained in a row of forty characters. Associated with each shift register circuit is a column driver 55 which is connected to a specific segment in one column, i.e., eight associated segments in the character of one column. Row driver block 54 of FIG. 3 is shown in FIG. 5 as comprising eight field-effect transistor pairs having a common drain output which is connected to the common electrode of the liquid crystal characters. Each column driver 55 is a similar circuit. The liquid crystal segment, which physically consists of two electrodes separated by the liquid crystal material, is electrically analagous to a R-C circuit connected across the segment electrode and the common electrode. A sufficient potential drop across the segment results in the excitation of the liquid crystal. I

It might be thought that a simpler driving scheme than the one shown in FIG. 5 could be used to obtain satisfactory results in exciting the segments. However, one of the big problems in trying to drive a large array of liquid crystal cells is the capacitive coupling from unselected cells to other unselected or selected column cells back to the selected row. Thus, when a column driver is selected, a potential is applied to all cells in that column and only that cell which is driven by a corresponding row driver should turn the display on. However, because each cell acts as a capacitor, a voltage appears across every cell in the selected column approximately equal to V X (N/N+2) where N is equal to the number of unselected columns. The larger the number of cells, the closer the value of voltage across every cell comes to be driving voltage. This tends to cause all of the columns, both selected and unselected. to turn on, causing lack of contrast within the array.

The circuit of FIG. 5 eliminates this problem by applying a voltage across the segment even when that segment is not selected. The voltage acts as a positive means for keeping the liquid crystal turned off. In the circuit a positive level on the true inputs B and D of a selected segment yields a potential difference of 30 volts across the liquid crystal, which is sufficient to turn the crystal on. With V 20 v and V l0 v, the selection of the true inputs B and D cause a potential difference across the segment of 30 v. With voltages V +l0v and V, 0v, the selection D of a particular column containing the segment, with the nonselection I? of its row yields a potential difference of only 10 volts across the crystal, which is insufficient for scattering. Similarly, the selection B of the row in which the crystal segment is located and the nonselection D of the corresponding column yields a potential difference of only 10 volts.

The selection of these relative values of voltages also has the advantageous effect of tending to improve the lifetime of the liquid crystal material. This is true because an unselected column a t Q,, will have opposite polarity voltages of l0v and -l lOv across segments in selected and unselected rows, respectively. This causes AC current, rather than DC, to flow during a refresh cycle; and it is known that AC driving significantly increases liquid crystal lifetimes.

OPERATION The operation of the inventive system will be more fully appreciated if note is taken of the timing diagram of FIG. 6 in conjunction with the circuit diagram of FIG. 3.

As shown in FIG. 6, the timing and control unit of FIG. 3 is synchronized by a l MHZ clock 29 which generates pulses at one microsecond intervals. Clock 29 advances segment counter 28, set decoder 38, row decoder 40 and P/S converter 18 in synchronism via connection 70. In addition, the clock signals are inverted in inverter 44 to synchronize the operation of character select counter 30, ROS address decoder 41 and F decoder 42 via connection 69.

For the beginning of the operation it is assumed that row 1 of set 1 of display unit 10 is to be loaded first by its associated shift register 1. Referring to the microsecond time scale in FIG. 6, with character select counter 30 addressing the location in RAM 14 reserved for the first character in the Display, RAM 14 addresses ROS 16 which generates the 18 bit representation of the symbol. P/S converter 18 generates one bit per clock cycle to load shift register 1 associated with set 1.

Clock 29 advances segment counter 28 during each clock cycle. Counter 28, in conjunction with the inverted pulses from inverter 44, causes a change in the ROS address by switching ROS Address Decoder 41 after each six clock .cycles. P/S Converter 18 receives six of the 18 bits from ROS 14 in response to an output from F Decoder 42 which operates one full cycle after ROS Address Decoder 41.

Segment counter 28 advances character select counter 30 after each 18 cycles to cause a new character location in RAM 14 to be addressed by counter 30. Forty characters of 18 segments each in row-1 of set 1 are transmitted to shift register 1 in 720 us. Set decoder 38 is then activated which advances set select counter 32. The locations in RAM 14 of the characters in row 1 of set 2 are then addressed. After a delay'of 2 us, the cycle begins again with the loading of shift register 2. At the same time, the row driver 54 drives the common segments via line R1 for set 1 for a period T =2.88 ms. to activate the display.

The millisecond time scale of FIG. 6 allows a broader view of the system operation. The shift registers associated with each set are loaded in sequence on a timemultiplex basis, each register being addressed and loaded for a period T =720us. Immediately after the loading of a particular shift register, the row driver for the selected row in the set is activated for the excitation period of the devices, T1. The other shift registers are loaded in sequence during T1. After each display cycle row select counter 34 is advanced; and the next succeeding row in each set is similarly energized as shown. In general, if there are N rows per matrix set, the ith row of each set is addressed on a time-multiplex basis during a given display cycle, where l s i s N; andv the ith 1 row of each set is addressed during the next succeeding display cycle.

The duration of the display cycle is an important factor in the design of the display unit, as it determines the number of matrix sets which can be accommodated. The cycle time is primarily a function of two physically unrelated factors: the loading time T of the shift registers and the excitation time T of the liquid crystal material. The duration of the display cycle must be at least as long as the total loading time of the shift registers, i.e., M'T,,, where M is the number of matrix sets in the display unit. ln-addition, the duration must be at least as long as the excitation time of the liquid crystal material plus the loading time of a single shift register, i.e., T T,,. A small increment of time must also be added for the access times of the ROS and P/S converter at the end of each display cycle. Generally, the shift register contributes to the delay by orders of magnitude more than the other electronic circuits.

The number of rows and sets which can be energized is dependent on the de-excitation time of the devices. These de-excitation times are commonly much greater than the excitation time of the devices. Wth the present liquid crystal devices the de-excitation times are in the order of 30 milliseconds; and a refresh rate of less than 30 milliseconds assures operation without significant flicker. In the present system the refresh period, T,, is approximately 29 milliseconds. The particular excitation and de-excitation times of liquid crystal devices will, of course, vary greatly and the display unit design would have to be changed accordingly. The number of rows which can be accommodated in a matrix set can be at most equal to:

Thus, the larger the de-excitation time, the more rows which can be used in each matrix.

The maximum number of segments which can be addressed in a given row can be computed by the equation:

where S is the total number of segments in a row and T is the response time of the shift register.

For the values in the present system, the number of segments S which can be addressed per row is 720. or 40 characters having 18 segments each.

While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in format and details may be made thereon without departing from the spirit and scope of the invention. For example, many types of liquid crystal materials could be used to advantage in the present display unit. In addition, the number of characters which can be displayed in a unit, as well as the particular numbers of rows and columns of characters can be varied widely within the scope of the present invention.

1 claim:

1. A system for information display comprising:

a display unit including a plurality of matrices of liquid crystal display devices;

a plurality of buffer register means, each unique to a single display matrix, for storing symbol representations of a complete row of symbols in each matrix;

means for transmitting symbol representations .of a complete row of symbols to each of 'said buffer register means in sequence on a time-multiplex basis during a display cycle;

means for activating a selected row of each matrix in the same said sequence; and

means for advancing said activating means to activate another selected row in each said matrix during a succeeding display cycle.

2. A system as in claim 1 wherein a single row of devices is excited during each display cycle.

3. A system as in claim 1 further comprising:

means connected to said transmitting means for storing information signals representative of all symbols to be displayed on all of said devices.

4. A system as in claim 3 wherein said transmitting means comprises:

character generator means responsive to said information storing means for generating binary representations of characters to be displayed on said display unit.

5. A system as in claim 4 wherein said transmitting means further comprises:

means connected to the output of said character generator means for transmitting said binary symbols in serial fashion to said shift register means.

6. A system as in claim 1 wherein the entire display unit is addressed within a duration at least equal to the de-excitation time of a liquid crystal device.

7. A system as in claim 1 wherein:

saiddisplay devices are segmented characters; and

each said buffer register means comprises a shift register having outputs for driving said segments.

8..A system as in claim 7 wherein:

the number of said outputs is equal to the number of segments in a single row of characters in a matrix; and

each said output is connected to a single segment in each row of the matrix.

9. A system for information display comprising:

a display unit including a plurality of matrices of display devices;

said devices being characterized by a relatively long excitation time and a longer de-excitation time;

means for transmitting symbol representations to said buffer register means;

control means connected to said buffer register means, said transmitting means and said devices, said control means comprising:

means for loading said symbol representations into said buffer register means in sequence on a timemultiplex basis during a display cycle;

row driver means for activating a selected row of each matrix for a duration at least equal to said excitation time in the same said sequence; and

row select means for advancing said row driver means to activate another selected row in each said matrix during a succeeding display cycle.

10. A system as in claim 9 further comprising:

11. A system as in claim 10 wherein said control means further comprises:

means comprises:

13. A system as in claim 12 wherein said transmitting means further comprises:

14. A system as in claim 9 wherein said display devices are liquid crystal-devices.

15. A system as in claim 14 wherein: said display devices are segmented characters; and

16. A system as in claim 15 wherein:

the number of outputs is equal to the number of segments in a single row of characters in a matrix; and

each said output is connected to a single segment in each row of the matrix.

Claims

2. A system as in claim 1 wherein a single row of devices is excited during each display cycle.
3. A system as in claim 1 further comprising: means connected to said transmitting means for storing information signals representative of all symbols to be displayed on all of said devices.
4. A system as in claim 3 wherein said transmitting means comprises: character generator means responsive to said information storing means for generating binary representations of characters to be displayed on said display unit.
5. A system as in claim 4 wherein said transmitting means further comprises: means connected to the output of said character generator means for transmitting said binary symbols in serial fashion to said shift register means.
6. A system as in claim 1 wherein the entire display unit is addressed within a duration at least equal to the de-excitation time of a liquId crystal device.
7. A system as in claim 1 wherein: said display devices are segmented characters; and each said buffer register means comprises a shift register having outputs for driving said segments.
8. A system as in claim 7 wherein: the number of said outputs is equal to the number of segments in a single row of characters in a matrix; and each said output is connected to a single segment in each row of the matrix.
9. A system for information display comprising: a display unit including a plurality of matrices of display devices; said devices being characterized by a relatively long excitation time and a longer de-excitation time; a plurality of buffer register means, each unique to a single display matrix, for storing symbol representations of a complete row of symbols in each matrix; means for transmitting symbol representations to said buffer register means; control means connected to said buffer register means, said transmitting means and said devices, said control means comprising: means for loading said symbol representations into said buffer register means in sequence on a time-multiplex basis during a display cycle; row driver means for activating a selected row of each matrix for a duration at least equal to said excitation time in the same said sequence; and row select means for advancing said row driver means to activate another selected row in each said matrix during a succeeding display cycle.
10. A system as in claim 9 further comprising: means connected to said transmitting means for storing information signals representative of all symbols to be displayed on all of said devices.
11. A system as in claim 10 wherein said control means further comprises: character select means for addressing said information storing means to cause representations of a character to be transmitted to said buffer register means; and set select means responsive to a signal from said character select means for selecting a succeeding matrix at the end of a row of characters and for signalling said row select means when the last matrix has been addressed.
12. A system as in claim 10 wherein said transmitting means comprises: character generator means responsive to said information storing means for generating binary representations of characters to be displayed on said display unit.
13. A system as in claim 12 wherein said transmitting means further comprises: means connected to the output of said character generator means for transmitting said binary symbols in serial fashion to said shift register means.
14. A system as in claim 9 wherein said display devices are liquid crystal devices.
15. A system as in claim 14 wherein: said display devices are segmented characters; and each said buffer register means comprises a shift register having outputs for driving said segments.
16. A system as in claim 15 wherein: the number of outputs is equal to the number of segments in a single row of characters in a matrix; and each said output is connected to a single segment in each row of the matrix.