US3768004A - Engine timing computer - Google Patents

Abstract

There is disclosed a method and apparatus for internal combustion engine timing based on measurement of the advance or retard of the firing of each spark plug with respect to a reference derived from the top dead center position of the piston for the number one cylinder. The engine timing is adjusted so that the average value of the advance or retard for all plugs equals a predetermined design value. A variable frequency oscillator is phase-locked by signals representing individual spark plug firing to operate at a frequency of 3,600 pulses per engine revolution. A reference related to the top dead center position of piston for the first cylinder is determined by sensing a notch in the engine damper or fan pulley, and is used to produce a series of pseudo damper pulses offset from the top dead center positions of the various pistons by 45 degrees by dividing the output of the variable frequency oscillator and selecting pulses to define the pseudo damper pulse interval based on the number of cylinders in the engine being timed. Timing measurement is achieved by counting the number of pulses between firing of a plug and the associated pseudo damper pulse over several complete engine operating cycles, averaging the result and removing the 45 degree offset. Digital display, printout, upper and lower limit computation and actual engine RPM measurements are also provided.

Description

' Elnited States Patent 91 Abnett et al.

[ ENGINE TIMING COMPUTER [75] Inventors: Albert C. Abnett, Westerville;

Robert A. Boley, Columbus, both of Ohio [73] Assignee: Autech, Inc., Columbus, Ohio [22] Filed: Jan. 20, 1972 [21] Appl. No.: 219,250

[52] 11.8. CI. 324/16 R, 73/118 [51] Int. Cl. F02p 17/00 [58] Fleld of Search [56] References Cited UNITED STATES PATENTS 3,454,871 7/1969 Nolting 324/16 3,474,667 10/1969 Fuchs 324/16 FOREIGN PATENTS OR APPLICATIONS 249,849 8/1969 U.S.S.R 324/16 Primary ExaminerMichael J. Lynch Attorney-Robert E. LeBlanc et al.

[57] ABSTRACT There is disclosed a method and apparatus for internal 1 Oct. 23, 1973 combustion engine timing based on measurement of the advance or retard of the firing of each spark plug with respect to a reference derived from the top dead center position of the piston for the number one cylinder. The engine timing is adjusted so that the average value of the advance or retard for all plugs equals a predetermined design value. A variable frequency oscillator is phase-locked by signals representing individual spark plug firing to operate at a frequency of 3,600 pulses per engine revolution. A reference related to the top dead center position of piston for the first cylinder is determined by sensing a notch in the engine damper or fan pulley, and is used to produce a series of pseudo damper pulses offset from the top dead center positions of the various pistons by 45 degrees by dividing the output of the variable frequency oscillator and selecting pulses to define the pseudo damper pulse interval based on the number of cylinders in the engine being timed. Timing measurement is achieved by counting the number of pulses between firing of a plug and the associated pseudo damper pulse over several complete engine operating cycles, averaging the result and removing the 45 degree offset. Digital display, printout, upper and lower limit computation and actual engine RPM measurements are also provided;

33 fill? Prsrhaliee United States Patent [191 Abnett et al.

[ Oct. 23, 1973 OATAPER 22 T0 PRINTER I00 P'CKUP DAMPER L l 34 36 56 SIGNAL I FAULT FAULT l4 PROCESSOR 39w DETECTION m 26 C'Rclm INDICATOR SPARK 24 42 PICKUP SPARK SIGNAL v00 28 PROcEssOR 4e PHASE DIVIDER a DETECTOR 40OA2OO/IROO L 4 i I GENERATOR E Msz L58 6O 4 6 HI 64 f 68 76 TOLERANCE AOv/RET sEOOENOTNO COUNT T m LOGIC LOGIC GENERATOR 92 TARGET 90 7B COUNT OENERATOR E70 1 AvERAOTNO MAIN v COUNTING OONPARlsON LOG'C LOGIC LOGIC t T J E as s CALIBRATION MN OOONT 94 l OENERATOR LIMIT RPM LOGIC i cOuNTER $82 I RPN LIMIT TIMINGANGLE 96 E DISPLAY LIMIT RPM so DISPLAY 98 DISPLAY i L84 H OuTPuT T A PRINTER UNIT FROM '00 FAULT 4 DETECTION CIRCUIT 34 PATENTED N 23 Ian 3.768.004 SHEET 10$ 8 DAMPER 22 TO PRINTER IOO PICKUP DAMPER l 34 J 36 5s g gg ggg TINT AM A I 39 DETECTION a 2s 2/ CIRCUIT INDICATOR ADv/RET SPARK Q24 4 END; 42 8 PICKUP SPARK 40 g SIGNAL I TACH v00 28 PROCESSOR N 38 Q 46 44 4 D PHASE 7 DIVIDER s DETECTOR .400/200/[800 W N 4 61 8f GENERATOR SELECT0R\62 L58 6O T4 6 8i 48 4 L w /68 TOLERANCE ADv/REI SEQUENCING COUNT LOGIC LDOIO GENERATOR r92 ADv/RET M TARGET eo 7 COUNT 72 GENERATOR I l I AvERAsIND MAIN PA COUNTING V COM LOGIC LOGIC LOGIC J g9 88 L L CALIBRATION v I 94 1 74/ COUNT GENERATOR LIMIT RPM LOGIC COUNTER p82 RPM LIMIT TIMING ANGLE m 96 SET E DISPLAY LIMIT RPM 80 DISPLAY DIsPLAY *P L84 OIITPIIT FIG. M PRINTER uNIT FROM PAIILT N DETEOTION CIRCUIT 34 minnow 23 ms 30% E i ww m 39w T D N 9-H n E? gm 3 .232 1 E080 2N m2: 9 1 $8M 28m J I 5 g r A? E o m FAA 05 I $538 a M239 Sm g m I? E m M383 8 Na m ET m 5 H s E 3 3 3m 82 u m H 1 g N 2% ma 3: oww f m at Na 88 A 3 Ems AZ; Q E so; 5 mm @M m b 8? am X N v Na Na v as 0 E ENGINE TIMING COMPUTER INTRODUCTION This invention relates to internal combustion engine timing, and more particularly to techniques and equipment for improving the accuracy of timing of engines such as automobile engines both in the assembly plant, and thereafter for purposes of routine maintenance.

Reference is made to a related patent application, Ser. No. 219,416 filed Jan. 20, 1972 entitled Engine Timing Computer, filed concurrently herewith in the name of Arthur R. Crawford et al, which application claims certain subject matter disclosed herein, and related to the subject matter claimed in this application.

BACKGROUND Briefly, by way of background, in a four-cycle engine of the type customarily employed in automobiles, each cylinder fires once for every two revolutions of the crankshaft. In most engines, a spark is provided for each cylinder slightly prior to the top dead center position for the piston on its compression stroke, although engines are occasionally designed to fire after the top dead center position.

Firing is controlled by a timing system. This includes a distributor having a rotating shaft coupled to the crankshaft by a 2:1 reduction gearing mechanism whereby the distributor shaft makes one complete rotation for every two crankshaft rotations. The distributor shaft carries a multi-lobe cam, (one lobe for each cylinder) which engages with a follower to operate a set of breaker points. These are shunted by a capacitor in a primary circuit of a spark coil connected to the battery. Opening of the points as the timing cam rotates provides rapid magnetic field changes in the secondary of the spark coil with resulting high voltage across the coil secondaries. The high voltage pulses are coupled to individual spark plugs by a rotating contact member carried by the distributor shaft and engaging with a series of fixed contacts in the distributor, each connected to one of the spark plugs.

Timing is normally adjusted in relation to the top dead center position of the number one piston by rotating a plate carrying the cam follower and breaker points in relation to the cam on the distributor shaft.

Accurate engine timing is extremely important because an improperly timed engine operates inefficiently and with less than optimum power and also, because timing errors increase the octane requirement of the fuel. Also of. increasing importance is the fact that an improperly timed engine produces high exhaust emissions and-consequent air pollution.

The normal procedure employed in engine timing utilizes a timing light which is a stroboscopic lamp fired by discharge of the number one spark plug. Firing of the lamp illuminates a pointer mounted on the engine in relation to a dial on the rotating damper pulley. The recurring momentary illumination of the pointer and dial indicates the relationship between the firing of the No. 1 cylinder and the top dead center position of its piston, ordinarily in terms of degrees before (or after) top dead center.

The foregoing system possesses several disadvantages. First, because of the positioning of the various measuring components, there can be substantial and unpredictable parallax in reading of the pointer and markings on the damper pulley, thereby rendering the measurement inaccurate. Moreover, the stroboscopic timing equipment itself possesses inherent inaccuracies, due to the dynamic nature of the operation, and the visual nature of the observations. Further, measurements have been made with reference to a single cylinder on the assumption that each cylinder actually fires in precisely fixed relationship to the No.1 cylinder. However, imperfections in the timing gears, the cam, and elsewhere in the timing mechanism can cause deviation of as much as plus or minus 3 degrees from the design values. Thus, if the cam surface for cylinder NO.l is inaccurate, the resulting offset may completely invalidate the timing reading. Even if the NO.l cylinder is adjusted to fire exactly as specified, for example, at 6 degrees before top dead center, adjustment of the timing for the N01 cylinder to achieve this ordinarily results in firing of the remaining cylinders anywhere between 3 and 9 degrees before top dead center. This is totally unacceptable, particularly in view of increasing demands for reudced exhaust emissions.

For the foregoing reasons, several other techniques have been proposed to improve the accuracy of the engine timing operation, mostly involving electronically measuring the time interval between the firing and the top deadcenter position of the associated cylinder. Equipment of this type can provide a more accurate measurement of the timing angle for a particular cylinder, but totally fails to overcome the problem noted above regarding imperfection in the timing mechanism and its effect on the relationship between the firing angles for thecylinders.

Evidently, in recognition of the foregoing, it has been proposed to measure the timing angle for each cylinder with respect to the top dead center position of its respective piston, and to adjust the distributor rotor until the average of all of the angles equals the design value as specified with respect to cylinder NO. I. The general concept of average timing appears to have excellent prospects as a means of improving engine efficiency and reducing exhaust emissions. However, the heretofore proposed implementation of the average timing concept known to applicant appears to be subject to several important disadvantages.

For example, average timing as heretofore proposed employs a fixed frequency reference oscillator and provides a measurement by counting the number of reference oscillator pulses between firing of each cylinder and a control signal representing the top dead center position for each cylinder. Since the frequency of the oscillator must bear a predetermined relation to the engine RPM at the time the measurement is made, means are provided to inhibit measurement unless the engine is running at the proper RPM. This presents difficulties since maintaining a constant engine RPM over even one revolution is almost impossible. While the variation in engine speed over a single revolution may not be great, nevertheless, even small changes ths substantial inaccuracy. twenty-eighth ths For example, if theRPM at the time of measurement is as little as 2 percent high, a timing error exceeding the required plus or minus 0.1 degree accuracy will occur. For this reason, successful aveeraging has been found to require measurement of timing angles over several engine revolutions, which does not appear practical with the prior equipment.

Another difficulty with the heretofore proposed average timing technique is the necessity for providing a pulse corresponding to the top dead center position for each cylinder. This is proposed to be accomplished in several way, for example a star wheel, or cam, or the like can be mounted on the front of the damper pulley, and an appropriate sensor mounted in fixed relationship on the engine. Alternatively, notches or the like could be cut directly in the damper pulley for interaction with a proximity sensor. Both of these techniques possess a significant economic disadvantage and in fact substantial resistance has been encountered in the industry. Placement of even a second notch on the damper pulley, i.e., for four-cylinder engine, is re garded as economically unattractive, and its use has been discouraged by the manufacturers.

A further problem with the previously proposed system is that under certain circumstances an engine designed to fire before top dead center may occasionally appear to fire after top dead center for a particular cylinder. The exact cause of such cross-over error is not clear but it is thought to be caused, for example, by a backfire, faulty plug, or other similar factors causing drastic transient changes in engine speed. Another possible cause may be inherent tracking imperfections in the measuring circuitry, though this may be more likely where, as described below, a constant number of pulses per engine revolution is employed. In any case, if logic circuitry designed to begin counting upon firing of the engine and to stop counting in response to the top dead center pulse is used under such circumstances, it will be appreciated that the count will begin with the engine firing but the top dead center pulse having already passed, the counting circuitry will continue to run until the next top dead center pulse. Even on an average basis, the resulting measurement would be so seriously affected as to be meaningless.

Yet an additional difficulty with the previously proposed device for average timing is its apparent inability to operate in the retard mode, as well as in the advance mode, without substantial inconvenience and possible unreliability. This presents a definite lack of flexibility.

BRIEF DESCRIPTION OF THE INVENTION The present invention seeks to avoid both the technical and economic problems with the heretofore proposed average timing techniques by employment of a system including a variable frequency oscillator for generating a fixed number of counting pulses per engine revolution, (preferably 3,600 so each pulse represents 0.1 degrees) and by averaging over several engine operating cycles, the number of pulses between the firing of each spark plug and the top dead center position for that cylinder, but based on a reference keyed to top dead center for the NO.l cylinder. Elaborating on the foregoing, by using a fixed number of pulses per revolution, the time scale for measurement is automatically expanded or contracted to conform to engine RPM. By making all measurements with reference to the top dead center position for the No.1 cylinder, the need for generating pulses correspnding to the top dead center position of the other cylinders is avoided and with it, the economic diasdvantages of providing more than one notch or other indicator.

To eliminate the need for actually counting with respect to the top dead center position of the first cylinder, there is provided means for generating a series of pseudo damper pulses. This operates to count the oscillator pulses, and to provide reference pulses at predetermined intervals in accordance with the number of cylinders in the engine being timed. For example, for a four-cy1inder engine, and with 3,600 counting pulses per revolution, the pseudo damper pulses would be spaced 1,800 counting pulses apart. correspondingly, pseudo damper pulses for six and eight-cylinder engines would occur at 1,200 and 900 pulse intervals, respectively.

Aside from the economic advantages mentioned above, employment of pseudo damper pulses has two additional advantages. First, it permits measurement of the position of a notch in the damper (or fan pulley) as a reference in arbitrary relationship to the top dead center position for the No.1 cylinder. Thus, if it proves to be convenient to position the proximity detector in such a manner that the notch passes the detector degrees before top dead center for the No.1 cylinder, location of the actual top dead center position may be accomplished simply by counting 1,000 pulses following the pickup output.

More importantly, since the reference position is arbitrary, a timing angle of 6 degrees before top dead center is equivalent to an angle of 16 degrees before a reference 10 degrees after the top dead center. This fact, and the fact that establishment of a reference is a simple matter of counting the desired number of pulses after the damper notch is sensed, completely avoids the possibility of a cross-over error.

Specifically, the reference for cylinder No. 1 is chosen to be 45 degrees before top dead center for timing an engine designed to fire after top dead center (retard mode) and at 45 degrees after top daed center for timing an engine designed to fire at or before top dead center (advance mode.)

The actual timing measurement is made by counting the number of variable frequency timing pulses between ignition of a cylinder and the associated pseudo damper pulse. This is accomplished by a counter activated either by the pseudo damper pulse for retarded firing or by the ignition pulse for advanced firing, and turned off by the ignition pulse for advanced firing.

The averaging operation is accomplished by maintaining a running count for the required number of ignitions. To reduce the required count capacity, the output of the reference clock is divided by the number of ignitions over which the average is taken before being coupled through the gating circuit to the counter.

The result is displayed digitally with the least significant figure being 0.1 degrees. The 45 degree offset mentioned above is subtracted out prior to display.

Additional features of the invention include means for accurately locating the damper reference notch means for providing upper and lower limit indications with respect to the target timing angle, engine RPM readout, and means to provide an indication when the RPM exceeds a set limit. The system also includes fault detection means for providing an indication of system inoperativeness and an output printer, by which a permanent record of the timing operation can be produced.

Accordingly, among the objects of this invention are the following:

10 provide improved techniques and apparatus for internal combustion engine tinfin g f To provide such techniques and apparatus utilizing average timing concepts but not subject to the disadvantages of heretofore proposed techniques;

To provide techniques and apparatus for average engine timing based on measurement of the angular interval between the ignition spark for each cylinder, and a reference angular position based on the top dead center position for the first cylinder;

To provide such average timing techniques and apparatus in which the average is taken over several com- 7 plete engine cycles to compensate for nonuniformities of engine speed;

To provide average timing equipment and techniques utilizing a variable frequency oscillator adapted to produce a constant number of pulses per engine revolution and means for counting the number of pulses between ignition for each cylinder and a reference angular position based on the top dead center position for cylinder No. 1;

To provide such a system in which the variable frequency oscillator is phase-locked with the engine ignition pulses;

To provide average engine timing techniques and apparatus as described above in which the reference angular position is established by generation of a series of pseudo damper pulses at predetermined angular interval in relation to top dead center for cylinder No. 1;

To provide such pseudo damper pulses by selecting ones of the output pulses of the variable frequency oscillator at fixed intervals determined by the number of cylinders in the engine with the first of said pulses being related to the top dead center position for the first cylinder;

To provide average timing techniques and equipment as described above in which the reference position for cylinder No. l is a predetermined number of degrees before or after top dead center for said cylinder;

To provide average techniques and apparatus as described above in which the reference position is determined by a marker rotatable with the engine crankshaft, and a fixed sensor positioned to provide an output signal in response to passage of the marker and in predetermined angular relation to the top dead center position for the first cylinder;

To provide internal combustion engine timing techniques and apparatus as described above in which the average engine timing is determined by establishing a predetermined number of counting intervals representing the desired multiple of the number of cylinders over which the avarage is to be taken, generating a series of measuring pulses, the number of such pulses per engine revolution being constant, dividing the series of measuring pulses by the number of counting intervals, establishing a series of measuring intervals between ignition for a particular cylinder and a reference based on the top dead center position for one of the cylinders, counting the number of divided counting pulses for a number of measuring intervals equal to said predetermined number and displaying the result as the average timing of said engine; and

To provide average timing techniques and apparatus as described above in which the reference position with respect to the one cylinder is established by producing a reference pulse in known angular relationship to the top dead center position for that cylinder, dividing the pulse train to produce a series of pseudo reference pulses per revolution equal in number to one-half the number of cylinders, and using the so generated pseudo reference pulses in defining the succession of counting intervals.

The exact nature of this invention as well as other objects and advantages thereof will become apparent from consideration of the following detailed description together with the drawings in which:

FIG. 1 is an overall block diagram showing the organization of a preferred embodiment of the invention;

FIGS. 2a-2i are waveform diagrams pertinent to the operation of certain portions of the system of FIG. 1;

FIGS. 3 through 6 show the circuit diagrams for the damper signal processor, the spark signal processor, the tachometer unit, and the phase locked loop shown in FIG. 1;

FIG. 7 is a circuit diagram of the pseudo pulse generator and digital delay units shown in FIG. 1;

FIG. 8 is a circuit diagram of the main counting logic, the advance-retard logic, the averaging logic, the RPM computing logic, and the timing angle and RPM display units;

FIG. 9 is a circuit diagram of the calibration and tolerance count generators, and the sequencing logic unit; and

FIG. 10 is a circuit diagram of the comparison and limit logic units, the RPM limit setting unit, and the limit display.

Referring now to FIG. 1, there is shown in blockdiagram form a preferred embodiment of the engine timing apparatus of this invention. The system, generally denoted at 12, may be regarded as comprised of four related sub-systems, namely a timing signal generating unit 14, a timing computer 16, an RPM' computer 18, and an RPM and timing limit computer 20. The timing signal generator, illustrated in the upper half of FIG. '1 is comprised of input signal processors 22 and 24 for the damper notch pickup 26 and the spark coil pickup 28, a phase-locked loop 30 for generating a variable frequency pulse train comprising 3,600 pulses per engine revolution, and a pseudo damper pulse generator 32 which operates to select desired ones of the 3,600 pulses per revolution and to provide these as synthetic damper notch pulses in proper time relationship tothe actual damper notch pulse provided by pickup 26.

Pickups 26 and 28 are constructed in any suitable fashion. Damper pickup 26 is preferably an eddy current or other magnetic field sensitive device while spark pickup 28 is either magnetic field or electric field sensitive (capacitive) as desired. The damper pickup operates as a proximity sensor to produce an output signal once per revolution of the damper as a notch cut in its periphery passes through the pickup field of view. Tothis end, there is advantageously provided a mounting fixture (not shown) on the engine to support the pickup in suitable relation to the damper so that the pickup senses the notch as the damper rotates. The mounting fixture itself may be of any suitable construction,- and does not constitute part of this invention as such. However, it will be realized that placement of the fixture will depend on availability of an accessible mounting space. Any suitable mounting position may be employed, as long as the exact relationship between passage of the damper notch through the pickup field of sensitivity and the top dead center position for one of the pistons (for example, piston No. l) is accurately known. In this connection, the system can readily accommodate any angular relationship between the position at which the damper notch is sensed and top dead center for the No. 1 piston. However, for simplicity, the following description assumes that the damper notch is sensed by pickup 26 exactly 135 degrees after piston No. 1 reaches its top dead center position. system adjustment to accommodate other positions is explained below.

Damper signal processor 22 converts the pickup output into a narrow pulse defining the center of the damper notch and thereby provides a precise reference for generation of a series of pseudo damper pulses from which timing measurement is actually made. The output of the damper signal processor is also coupled to a fault detection circuit 34 which operates an indicator 36 in the event of signal loss from the damper pickup.

Spark pickup 28 operates to provide a signal representing the magnetic field pattern associated with the spark coil output. In one preferred construction, the spark pickup is constructed to fit around the spark coil output wire, in the manner of a clip on type ammeter, but other constructions may also be employed, if desired.

Spark signal processor 24 responds to the pickup output to generate a pulse in precise time relationship with the opening of the distributor points. This signal is used directly by timing computer 16, and is also provided to a tachometer 38 which produces an analog signal representative of the frequency of the spark pickup output. Generation of the tachometer output is accomplished by integrating the series of pulses produced by spark signal processor 24. However, because a fourcylinder engine produces two spark pulses per revolution as compared to three spark pulses per revolution for a six-cylinder engine and four spark pulses per revolution of an eight-cylinder engine, tachometer 34 includes means to convert each of the incoming pulses from spark signal processor 24 into a pulse of different width in accordance with the number of cylinders in the engine. To this end, there is provided a threeposition switch 39 which activates timing circuitry hereinafter described such that the pulse width for a six-cylinder engine is two-thirds the pulse width for a four-cylinder engine, while the pulse width for an eightcylinder engine is one-half the pulse width for a fourcylinder engine.

The tachometer output is provided as a second input to fault detection circuit 34 which operates indicator 36 if the spark signal is lost. The output of tachometer also provides a control input for phase-locked loop 30. The latter comprises a summing unit 40, a voltagecontrolled oscillator (VCO) 42 and a feedback loop comprising a variable frequency divider 44 and a phase detector 46. Summing unit 40 controls the frequency of VCO 42 in accordance with the sum of two DC voltages, one produced by the output of tachometer 38. The latter signal provides an approximate or coarse frequency control for the VCO while the former, representing the phase difference between the VCO pulse train and the pulse train produced by the spark signal processor 24, represents the normal phase error signal by which fine control of the phase-locked loop is achieved.

The system is so arranged that when operating properly, the output of VCO 42 provides 3,600 pulses per engine revolution. The VCO output is therefore 900 times the spark frequency for an eight-cylinder engine, 1,200 times the spark signal frequency for a sixcylinder engine, and 1,800 times the spark frequency for a four-cylinder engine. A control switch 48, cooperating with divider 44, assures the proper frequency relationship between the two inputs to phase detector 46 for four, six, or eight-cylinder engines according to the position of the switch.

The output of VCO 42 is provided to timing computer 16 as hereinafter described, and also to the pseudo damper pulse generator 32. This comprises a sample pulse generating unit 50, a gating circuit 52, a digital delay unit 54 controlled by an advance-retard switch 56, a clock pulse generator 58, a counter 60, and a pulse rate selector 62, controlled by a switch 64.

Pseudo pulse generator 48 is described in detail below, but briefly stated, its function is to select particular ones of the 3,600 VCO pulses per engine revolution in accordance with the setting of a cylinder selection switch 64 and to delay the selected pulses for a predetermined count depending on whether the engine is to be timed with the spark plugs firing before or after the top dead center position of the piston (i.e. advance or retard operation, respectively.) The pulses are selected to provide the required two, three, or four pulses per engine revolution for a four-cylinder, six-cylinder, or eight-cylinder engine, respectively. Also, the selected pulses are adjusted in accordance with the previously noted degree spacing between the top dead center position of cylinder No. l and the position at which the damper notch is sensed, and to provide the 45 degree calibration offset which prevents cross-over error as previously described.

The averaging and timing computation functions are provided by timing computer subsystem 16. This includes an advance-retard logic unit 68, an averaging logic unit count generator a main counting logic unit 72 and a calibration countgenerator 74. These cooperate under the control of a sequencing logic unit 76 to provide a digital representation of the average of the angle between ignition and the top dead center position of the piston for each cylinder. Ignition is represented by the output of spark signal processor 24 while the associated top dead center position is keyed to the top dead center position of the No. 1 cylinder, with the succession of pseudo damper pulses being provided by the output of digital delay unit 54. The average is taken over 128 firings, i.e., 16 complete cycles for an eightcylinder engine. The angular internal is measured by counting the number of VCO pulses between the ignition pulse and the associated pseudo pulse. Since the VCO provides 3,600 pulses per engine revolution, each pulse counted represents 0.1 degrees.

As will be appreciated, for an engine timed in the advance mode, the spark signal precedes the associated pseudo damper signal, while in the retard mode, the pseudo damper signal occurs first. Advance-retard logic unit 68 operates to select which of the two pulses defines the beginning of each counting inverval in accordance with the position of an advance/retard selection switch 78.

During a succession of counting intervals, the number of VCO pulses is accumulated, and divided by the number of counting intervals to be employed in the averaging process. This is accomplished by averaging logic unit 70. The resulting average count is provided to main counting logic unit 72 which cooperates with calibration logic unit 74 to subtract 450 counts (i.e., representing 45 degree offset employed to prevent cross-over error),after which the result is visually displayed by means of timing angle display unit 84.

RPM and timing limit computer 20 is comprised of a comparison logic unit 88, target and tolerance count generators 90 and 92, a limit logic unit 94, and an RPM limit setter 96. Comparison logic unit 88 provides a measure of the difference between the actual average timing angle as indicated by the output of main counting logic unit 72, and a target timing angle as indicated by unit 90, and provides signals indicating whether the difference is within a preset tolerance range established by tolerance count generator 92, or above or below the range. Limit logic unit 94 utilizes these signals to operate display 98, and also provides a comparison between the actual RPM as indicated by counter 82, and a maximum RPM suitable for timing measurement as indicated by limit setter 96. A limit display 98 also provides an indication if the actual RMP exceeds the acceptable limit.

In addition, there is provided a printer unit 100, controlled by sequencing logic unit 76 by which a permanent record of the measured timing may be produced. The printout may include such reference data as the date, the machine number, etc., as well as the timing angle and the RPM at the time of measurement (actually, the average RPM over the measuring interval, as explained below). The latter data are provided by main counting logic 72, and RMP counter 82. Control signals are provided by sequencing logic 76, fault detection circuit 34 and limit logic 94. Signals from the latter prevent printer operation if incorrect data is sensed.

FIGS. 3 through 10, taken in conjunction with the waveform diagram shown in FIG. 2 illustrate in more detail the construction and operation of a preferred embodiment of the apparatus illustrated generally in FIG. 1.

Referring to FIG. 3 there is shown the construction of damper signal processor 22. The circuit comprises an integrated circuit differential amplifier 101 (such as Motorola type MC 741, or equivalent) having its inputs resistance coupled to damper pickup 26. The output of amplifier 101 at pin 6 is coupled to an automatic level control unit 102 comprised of a transistor Q1 and a detector circuit including diodes CR1 and CR2, capacitor C1 and resistor R1.

Transistor Q1 provides a current path for a differentiator circuit comprised of a capacitor C2 and resistors R2 and R3 which couples the output of amplifier 101 to the base of a transistor Q2, the collector of which is, in turn, RC coupled to the base of an output transistor Q3.

Referring now to FIG. 2, lines (a)(e), as well as FIG. 3, the damper notch 104 [FIG. 2, line (a)] may be regarded as a shallow rectangular cut-out having a leading edge 106 and a trailing edge 108. As notch 104 passes through the field of sensitivity of pickup 26, there is produced an output pulse such as illustrated in FIG. 2, line (b) having a positive-going leading edge 110 corresponding to the abrupt change in spacing between the pickup and the damper periphery as the lead ing edge 106 of the notch passes into the field of sensitivity of the pickup. As the leading edge passes the pickup, the output peaks, and returns toward zero, reaching the level at about the time that the center of the notch passes the pickup. Then, as the trailing edge of the notch approaches the pickup,its output continues negative, and reaches a minimum value at about the time that the trailing edge 108 passes the pickup. Thereafter, the output again becomes positivegoing, and returns to zero as the notch passes beyond the pickup.

The purpose of damper signal processor 22 is to convert the waveform shown in FIG. 2, line (a) to a narrow pulse such as shown in FIG. 2, line (c), as near as possible to the center of the damper notch.

Returning to FIG. 2, damper notch pickup 26 is coupled through amplifier 101 which inverts the pickup output, and at the same time converts it to a singleended signal referenced to ground. The result is shown in FIG. 2, line(d). As this signal goes negative, it is rectified and smoothed by detector circuit 102. The resulting time varying DC signal operates transistor Q1 which applies a negative bias level at the base of a tran sitor Q2 through resistors R2 and R3. Becuase of capacitor C2, the output of amplifier 101 is differentiated to produce a pulse shown in FIG. 2, line (e), superimposed on the depressed bias level for the base of transistor Q2.

As will be understood, the negative bias creates an input threshold for transistor Q2 which maintains the same nonconductive until the input pulses [FIG. 2 line (e)] becomes sufficiently positive. By adjusting the threshold level properly, the conduction period of transistor O2 is arrangedto occur very close to the zero crossing of the damper pickup output, i.e., at approximately the peak of the derivative waveform which occurs at the time thatthe center of the damper notch passes the pickup. 1

With transistor Q2 nonconducting, transistor Q3 conducts, whereby the normal level for the output signal is zero [see FIG. 2, line (c)]. When transistor Q2 conducts, transistor Q3 cuts off, thereby producing the sharp positive pulse at the center of the damper notch shown in FIG. 2(c).

Referring to FIG. 2(f), there is shown the waveform sensed by spark pickup 28 for each spark plug ignition. A cycle begins when the breaker points open producing a negative going transition indicated at 120. Thereaf ter, when the points close, a fairly complicated waveform characterizing the magnetic field resulting from the spark itself occurs. This is indicated at 122. Since the timing measurement is made with reference to the opening of the points, it will be appreciated that spark signal processor 24 must be responsive to the opening of the points, i.e. at 120, but preferably not tothe remainder of the waveform.

The circuitry required for accomplishing this result is shown in detail in FIG. 3. As illustrated, an input differential amplifier 124 such as one-half of a Motorola Type MC-l437, or the equivalent, is resistance coupled to spark pickup 28. Amplifier 124 operates to invert the polarity of the incoming spark signals, and at the same time to convert it to a singleended signal referenced to ground. The resulting output of amplifierl24, at pin 2 is shown in FIG. 2( g). The inverter spark signal is coupled to the negative input of a second differential amplifier 126 which may be the other half of the integrated circuit comprising amplifier 124. As illustrated, the coupling circuit includes a capacitor C2 and a voltage divider comprising a pair of like resistors R4 and R5, coupled between the negative power supply and ground.

With the R4-R5 voltage divider connected to the negative power supply, it may be seen that a negativeoffset or bias is applied to the negative input of amplifier 126. With the positive input at pin 8 grounded, the

gine.

negative bias at pin 9 tends to drive the amplifier output at pin 12 to a high level, but to prevent this, there is provided a feedback diode CR3 which clamps the output to approximately volts for all negative inputs.

From the AC standpoint, the RC coupling circuit operates to differentiate the spark waveform in FIG. 2( g) to produce a waveform such as shown in FIG. 2(h) including a sharp positive going spike 128 coincident with the opening of the points. It will, however, be noted that because of the negative offset produced by the voltage divider, only the portion of spike 128 exceeding the offset voltage reaches the input of amplifier 126 as a positive level.

When the input to pin 9 of amplifier 126 exceeds the bias threshold, the amplifier operates to produce a negative output, and remains operative until the input falls below the threshold. The result is a straight-sided negative pulse such as shown in FIG. 2(i), having a leading edge 130 coinciding with opening of the points.

The output of amplifier 126 is connected to the input of tachometer circuit 38, the construction of which is illustrated in FIG. 5. In essence, tachometer circuit 38 comprises a single shot multi-vibrator generally denoted at 132, having an adjustable operating period, and an integrator circuit 134 to produce a DC analog signal representative of the frequency of the ignition pulse train produced by spark signal processor 24.

Single shot 132 is comprised of a transistor Q4 and an amplifier 136, the latter comprising one-half of a Motorola Type MC-1437 integrated circuit, or the equivalent. A feedback path from the output of amplifier 136 at pin 12 is provided to the base of transistor Q4 over lead 138 through a pair or resistors R7 and R8.

Timing control for single shot 132 is provided by a timing capacitor C4 and a resistance circuit 140 including a series resistor R9 and three parallel resistors R10, R11, and R12 coupled in common to resistor R9, and to the fixed contacts of cylinder selection switch 36. The values of resistors R10 through R12 in relation to capacitor C4 and resistor R9 are so chosen that the sum of the pulse widths at the output of the single shot over one engine revolution is independent of the number of pulses. In other words, for a six-cylinder engine which produces three ignition pulses per revolution, the pulse width is two-thirds that for a four-cylinder engine which produces two ignition pulses per revolution. Correspondingly, for an eight-cylinder engine which produces four ignition pulses per revolution, the individual pulse width is one-half that for the four-cylinder en- The output of single shot 132 is provided as an input to phase detector 46 hereinafter described over lead 138, and also to an output circuit 141 comprising a transistor Q5, and associated circuitry. The collector of the transistor provides the spark output to timing computer subunit 16 (see FIG. 1) as described in detail below.

The output of single shot 132 also provides the input to VCO range integrator 134. The latter comprises a differential amplifier 142, preferably the second half of the integrated circuit comprising amplifier 136, provided with a feedback circuit including a capacitor C5 to integrate the pulse train output of single shot 132.

A shunt diode CR7 controls the maximum amplitude of the ingegrator input while a series diode CR6 blocks the passage of any positive signals. The output at pin 2 is therefore a DC level representative of the engine speed. Because the pulse width variation depending on the number of cylinders as explained above, the integration performed by circuit 134 is independent of the number of ignition pulses per engine revolution.

The output of amplifier 142 at pin 2 is coupled through an RC filter circuit 144 as the VCO range control signal for phase-locked loop 30, illustrated in detail in FIG. 6. As shown, the input from tachometer circuit 38 is provided to an integrated circuit amplifier 146 comprising summing circuit 40 (see FIG. 1). The input at pin 9 serves as a summing junction between the VCO range signal provided by a resistor R13 and by the output of phase detector 46 hereinafter described provided through a resistor R14. The output of amplifier 146 is connected to the control input of the voltage controlled oscillator which preferably is comprised of a commercially available integrated circuit unit such as the Signetics Type NE-556V, or its equivalent. The output at pin 3, having a frequency proportional to the amplitude of the control input at pin 5, is provided through an output amplifier comprising a transistor 06, which in turn feeds a pair of output circuits comprising further transistors Q7 and Q8. The output of transistor Q7 provides the VCO output signal to the timing computer subsystem hereinafter described while transistor Q8 provides the input for divider 44 in the phaselocked loop feedback circuit.

As previously noted, the output of VCO 42 is controlled such that its output frequency varies with engine speed to produce exactly 3,600 pulses per engine revolution. As shown in FIG. 1, frequency control by means of phase detector 46 requires comparison of the output of spark signal processor 24 with the output of VCO 42. Thus, it is necessary to reduce the frequency of the VCO output to correspond to that of the spark signal processor. Since the spark signal processor produces two, three, and four spark pulses per engine revolution for a four, six, and eight-cylinder engine respectively, and the VCO output is 3,600 pulses per revolution, it will be appreciated that divider unit 44 must divide the VCO output by 1,800 for a four-cylinder engine, by 1,200 for a six-cylinder engine, and by 900 for an eightcylinder engine.

The foregoing result is accomplished by employment of digital dividers and associated combinational logic including a divide by 300 unit 148 connected in parallel to a divide by six unit 150 and a divide by four unit 152. Each of the latter may be constructed in conventional fashion of commercially available ingegrated circuit counters. For example, divider 148 may be constructed of a series combination of two decade counters such as Texas Instruments Type 7490 and a divide by 12 counter such as Texas Instruments Type 7492 wired to provide a divide by three function. Similarly, divider 150 may be a Texas Instruments Type 7492 counter wired to provide both a divide by six and divide by three functions. Divider 154 may be a Texas Instruments Type 7493 four bit binary counter wired to provide the divide by four function.

Considering dividers 148 and 152 as connected in series, it may be seen that the output of divider 152 effectively divides the output of VCO 42 by 1,200. Similarly, considering dividers 148 and 150 as connected in series, the divide by six output of divider 150 effectively divides the VCO output by 1,800 while the divide by three output divides the VCO output by 900.

Selection of the proper one of the outputs of dividers 150 and 152 is accomplished by an AND gate 154 connected to the output of divider 152, and two additional AND gates 156 and 158 connected to the divide by six" and divide by three outputs respectively of divider unit 150. The outputs of all of AND gates 154, 156, and 158 are connected to a NOR gate 159 to provide the output of the divider unit as a whole.

Control inputs for AND gates 154, 156, and 158 are provided respectively through three inverters 160, 162, and 164 by switch control circuit 166 comprising three resistors R16, R15, and R17 connected respectively to the inputs of inverters 160 through 164 and in common to the positive power supply. The inputs of each of in verters 160 through 164 are also connected to the fixed contacts of selection switch 48. The moving contact is grounded thereby providing a low level input to the selected one of inverters 160 through 164 and high inputs to the other two inverters. Since the outputs of the two unselected inverters are low, the corresponding ones of AND gates 154 through 158 are inhibited while the AND gate associated with the selected one of inverters 160 through 164 is activated. Thus, depending on the position of switch 48, divider 44 provides at the output of OR gate 159 a signal at two pulses per revolution for a four-cylinder engine (3,600 divided by 1,800), three pulses per revolution for a six-cylinder engine (3,600 divided by 1,200) and four pulses per engine revolution (3,600 divided by 900) for an eight-cylinder engine.

The output of divider 44 is provided over lead 168 as one input to the phase detector unit 46 through an input transistor Q10, the other input being provided through a transistor Q9 from single shot 132 in tachometer 38 previously described. In essence, phase detector unit 46 comprises a pair of variable frequency single shot multi-vibrators 170 and 172, each arranged to convert the incoming pulses (at two, three or four pulses per engine revolution) into a square wave at the input frequency. An analog phase detector circuit 174 compares the phases of the resulting square waves.

Considering first the variable period single shot 170 associated with the spark signal input at transistor Q9, the two amplification stages are provided by a transistor Q11 and an integrated circuit differential amplifier 176. Feedback from'the pin 2 output of amplifier 176 is provided over lead 178 and resistors R18 and R19 to the base of transistor Q11. Timing control is provided by a capacitor C6 and a charge control transistor Ql3 operated by a diode-RC biasing control circuit 180 which compares the duration of the on and off portions of the single shot output cycle and adjusts the charging time for capacitor C6 to maintain the two portions equal. v

The above-described function is accomplished by a pair of polarized integrator circuits 182 and 184 coupled to the collector of single shot transistor Q11 by a resistor R20. Due to opposite polarization of diodes CR12 and CR13, integrator 182 responds only to one portion of the single shot cycle while integrator 184 responds only to the other portion. At the end of a cycle, a difference in the integrated signal levels indicates that the two portions of the single shot operating cycle are not of equal duration.

This difference, if any, is measured between a pair of resistors R21 and R22. The signal at the junction point is fed back over lead 186 to the base of transistor Q13. The latter also receives as a bias reference, the output As will be appreciated, potentiometer R23 is set to produce a square wave output at some frequency trigger signal with zero feedback over lead 186. Thus, for.

other trigger frequencies, the bias on lead 186 varies the current through transistor Q13, and thus the charging current for capacitor C6, to maintain the active period of the single shot equal to half the period of the triggering pulses. The result, therefore, is a squarewave signal at pin 2 of amplifier 176 whose frequency is equal to the pulse rate of the incoming signal from tachometer 38.

The second single shot circuit 172 is comprised of a transistor Q12 and an integrated circuit amplifier 188 forming the other half of the integrated circuit comprising amplifier 176, connected by a feedback path 190. Single shot 172 is associated with the divider output provided over lead 168 through transistor Q10. Timing control for single shot 172 is provided by capacitor C7 and a charging current control transistor Q14 operated by a pair of diode- RC feedback circuits 192 and 194 like circuits 182 and 184. These monitor the waveforms at the collector of transistor Q12 and provide a signal on lead 196 representative of the difference between the two portions of the single shot cycle. A reference potentiometer R24 functions in the same manner as potentiometer R23. Changes in the bias level on lead 196 varies the charging current for capacitor C7 through transistor Q14 to maintain the single shot as a squarewave.

The outputs of single shots and 172 are provided to the phase detection circuit 174. This comprises transistors Q15 and Q16, and a differential amplifier 198 which provides an output at pin 2 in a form of a DC signal representing the phase difference between the outputs of the single shots. The phase difference signal is provided over lead 200 through a potentiometer R25 and previously mentioned resistor R14 to the summing junction input of amplifier 146. Thus, it may be seen that the output frequency of VCO 42 is controlled by the sum of the VCO range signal provided by tachometer 34 and the signal representing the phase difference between the oscillator output and the spark pulse signal generated by single shot 132. The aforementioned arrangement is particularly advantageous since ,it allows establishing a coarse adjustment for the VCO related directly to the engine RPM, and a fine adjustment based on the phase difference between the oscillator output and the incoming spark pulses.

The VCO output is provided by previously men-- tioned transistor 07 over lead 202 to the input of pseudo pulse generator 48, illustrated in detail, along with digital delay unit 54, in FIG. 7.

Before proceeding with the structural description, however, it is worthwhile to recall the functional requirements for the pseudo pulse generator and associated digital delay unit. To eliminate the possibility of cross-over error as described above, the timing system herein described measures the timing angle with respect to a reference 45 degrees before the top dead center position of the associated cylinder for an engine operating in the retard mode, and 45 degrees after the top dead center position of the associated cylinder for an engine operating in the advance mode.. Signals representing each of these angular positions are to be generated with reference to the single actual pulse produced by the damper pulse sensor at a position 135 degrees after the top dead center position for the cylinder No. 1.

Considering first the operation of a four-cylinder engine in the retard mode, the first pseudo damper pulse must appear 45 degrees before the top dead center position for cylinder No. l and 180 degrees thereafter, i.e., at 225 degrees after top dead center for cylinder No. 1. This provides pseudo damper pulses for two of the four cylinders; the remaining pseudo damper pulses are to be generated at the same angular positions during the next revolution.

correspondingly, for a six-cylinder engine operating in the retard mode, pseudo damper pulses are required 45 degrees before top dead center for cylinder No. 1, and at 120 degree intervals thereafter, i.e., at 75 and 195 degrees after top dead center for cylinder No. 1. Finally, for an eight-cylinder engine, four pseudo damper pulses per revolution must be provided at 45 degress before top dead center for cylinder No. l, and at successive 90 degree intervals, i.e., at 45, 135, 225, and 315 degrees before top deadcenter for cylinder No. 1.

Because the single reference pulse is available only at 135 degrees after top dead center, it may be seen that pseudo damper pulses may readily be referenced to 135 degrees after top dead center for cylinder No. 1, rather than to the top dead center position. The required pseudo damper pulse angles for retard operation, taking into account the 45 degree offset to avoid cross-over erros, are listed below in TABLE ONE. The second column gives the angles with reference to top dead center, while the third column gives the angles with reference to the damper notch.

*135" after TDC. No. 1.

TABLE ONE: PSEUDO PULSES FOR RETARD TIMING Considering now the situation for operation in the advance mode, it will be appreciated that avoidance of cross-over error for a timing angle preceding the top dead center position requires the appearance of the pseudo pulse 45 degrees after top dead center. Thus, for a four-cylinder engine, the pseudo damper pulses must appear at 45 and 225 degrees after top dead center for cylinder No. 1, or at 90 and 270 degrees with reference to the 135 degrees offset between the sensing of the damper notch and top dead center for cylinder No. 1. Corresponding analysis shows that with respect to the top dead center position for cylinder No. 1, pseudo damper pulses for a six-cylinder engine must appear at 45, 165, and 282 degrees, or at 30, 150, and 270 degrees with reference to the damper notch. For an eight-cylinder engine, with reference to top dead center position for cylinder No. l, damper pulses are required at 45, 135, 225 and 315 degrees, corresponding to 0, 90, 180, and 270 degrees with reference to the damper notch. The foregoing results are summarized in TABLE II below.

No. of Advance Mode: Advance Mode: Cylinder (Ref. TDC No. 1) (Ref. Damper Notch) i 135 after TDC. No. 1

TABLE TWO: PSEUDO PULSES FOR ADVANCE TIMING Comparing TABLES I and II, it may be seen that in each case, a pseudo damper pulse for retard mode timing appears 90 degrees before the corresponding pseudo damper pulse for advanced mode timing. (This fact may also be appreciated from recognition that avoidance of cross-over error requires positioning the pseudo damper pulse 45 degrees before top dead center for retard timing and 45 degrees after top dead center for advance timing, producing a net 90 degree offset.) Because of this, and in viewof the availability of the reference pulse at 135 degrees, it is found convenient to generate the pseudo damper pulses in relation to the damper notch according to the angular positions set forth in the right hand column of TABLE I and to provide the corresponding pseudo pulses for advance timing by delaying each of the retard mode pseudo damper pulses 90 degrees, i.e., at the angular positions set forth in the right hand column of TABLE II.

The circuitry used to accomplish these functions is illustrated in FIG. 7. The pseudo pulse generating unit 32 includes counter 60 comprised of a four-decade binary coded decimal counter unit 204 constructed of integrated circuit units of any conventional or desired type. Counter 204 receives as its count input, the output of a single shot 58 comprising the clock pulse generator referred to in FIG. 1. The latter receives as its input, the VCO output signal described above in connection with FIG. 6. A reset input for counter 204 is provided by another single shot 206 receiving as its input, the damper signal provided by the output of transistor Q3 (see FIG. 3.) As will be appreciated, the VCO output constitutes a train of 3,600 pulses per engine revolution while the damper signal is pulse appearing once per revolution. Thus, counter 204 reaches to a 1 count of 3,600 in binary coded decimal form before being reset for each engine revolution.

The BCD outputs of counter 204 for the two least significant decades are provided in binary coded decimal form to a one-counter interval generator- 208, while the outputs for the two most significant decades are provided respectively to a pair of BCD to 10- line decoders 210 and 212. One-count interval generator 208-comprises an AND gate 214 coupled directly to the output for the least significant bit (0,1 degree) of the first decade, while the outputs for the remaining bits of the first decade are coupled through respective inverters 216, 218, and 220. Similarly, all four bits comprising the second decade are coupled to AND gate 214 through inverters, two of which are shown at 222 and 224. Assuming counter 204 provides its outputs in a positive logic format, the inputs to AND gate 214 are all high only during the first count of every two decades, i.e., every 100 counts.

BCD to 10- line converters 210 and 212 are preferably constructed of commercially available integrated circuit units such as Texas Instruments Type 7442. Such units provide ten outputs in response to a BCD input. The output corresponding to the input code is low; all the other outputs are high.

Decoder 210 is associated with the third decade of counter 204, and thus switches states every one hundred counts. Correspondingly, decoder 212 is associated with the fourth decade of counter 204 and thus switches states only every one thousand counts. However, the available outputs from third decade decoder 210, only the 000, 600, 700, 800, and 900 count outputs are required. From fourth decade decoder 212, only the 0000, 1000, 2000, and 3000 count outputs are required.

Each of the above-mentioned outputs is provided through a respective one of inverters 226(a) through 226(i) to convert the signals to positive logic. Thus, the outputs of inverters 226(a) (i) are high between the various counts set forth below in TABLE III.

Inverter 226(b) 600-699,l60O-l699,et 226(c) 700-799,l700-l799,etc. 226(d) R-899,l800-l899,etc. 226(e) 900-999,l900-l999,etc.

226(g) 1000-1999 226(h) 2000-2999 226(i) 300-3599 *Typical; repeats every I000 Counter resets at 3600 TABLE III The outputs of inverters 226(a) (i) are connected to various ones of six AND gates 228-238 comprising part of pulse selector 62. AND gates 228-238 function to collect required ones of the hundred count signals and the thousand count signals to form six different 100 count intervals. In particular, the outputs of inverters 226(a) and (f) are coupled to AND gate 228 to produce a high output during counts 0-99. The outputs of inverters 226(d) and 226(g) are coupled to AND gate 230 to produce a high output for counts 1,800-1,899. The outputs of inverters 226(e) and (f) are provided to AND gate 232 to produce a high output for the counts 900-999. The outputs of inverters 226(b) and 226(f) are produced to AND gate 234 to produce a high output for the counts 600-699. The outputs of inverters 226(c) and (h) are provided to AND gate 236 to produce a high output for counts 2,700-2,70l. Finally, the outputs of inverters 226(a) and 226(i) are coupled to AND gate 238 to produce a high output for counts 3 ,000-3,099.

The outputs of AND gates 228 and 230 are coupled to the inputs of an OR gate 240. AND gates 228 and 230 are also coupled as'inputs to another OR gate 242, along with the outputs of AND gates 232 and 236. A third OR gate 244 receives as itsinputs, the outputs, of AND gates 230, 234, and 238. OR gate 240 thus operates counts 0-99 and 1,800-1,899, while OR gate 242 operates for counts 0-99, 900-999, 1,800-1,899, and 2,700-2,799. OR gate 244 operates for the counts of 600-699, 1,800-1,899, and 3,000-3,099.

The outputs of OR gates 240, 242, and 244 are connected respectively as inputs to three AND gates 246, 248, and 250. Second inputs for each AND gate 246 through 250 are provided through three inverters 252, 254, and and 256, the inputs of which are connected to the positive power supply through three resistors 258, 260, 262, respectively. Each resistor is also connected to the fixed contacts of three-position switch 64 which has its moving contact grounded. As will be understood, resistors 258, 260, and 262 maintain the inputs to inverters 252 through 256 at a high level except for the inverter attached to the grounded switch contact. Thus, the outputs of two of the inverters are low while the output of the selected inverter is high to activate the associated AND gate. Thus, with switch 64 in the four-cylinder position, AND gate 246 is conditioned, with switch 64 in the six-cylinder position, AND gate 248 is conditioned and with switch 64 in the eightcylinder, position, AND gate 250 is conditioned.

The third inputs to each of AND gates 246 through 250 are provided in common over lead 264 by the output of AND gate 214. As previously described, AND gate 214 operates to provide a high level output for a single count interval at the beginning of every counts. Thus, AND gate 246 operates only at counts 0 and 1,800, AND gate 248 operates only at counts 0, 900, 1,800, and 2,700, while AND gate 250 operates only at counts 600, 1,800 and 3,000.

Recalling that a cycle for counter 240 begins upon receipt of a damper signal (at which time the counter is reset through single shot 206) and that each count pulse represents 0.1 degree after the damper pulse, it may be seen that the pseudo pulses for a four-cylinder engine occur-at 0 degrees and degrees after the damper pulse. Similarly, for an eight-cylinder engine, the pseudo damper pulses occur at 0, 90, 180, and 270 degrees after the damper pulse. For a six-cylinder engine, the pseudo damper pulses occur at 60, I80 and 300 degrees after the damper pulse.

The outputs of AND gates 246-250 are coupled through an OR gate 266 to one input of AND gate 52 shown in FIGS. 1 and 7. The other input for AND gate 52 is provided by a sample pulse generator 50 comprised of a single shot 270 triggered by the VCO output on lead 202 through an inverter 268.

The output of AND gate 52 provides the input for digital delay unit 54. This is essentially a three-decade coded decimal counter 272 and associated decoding and steering logic. Counter 272' operates under control of the VCO clock pulses provided through clock generator single shot 58 over lead 298. The counter thus maintains a BCD count corresponding to lOths, units, and 10s of degrees.

The BCD outputs of counter 272, in order of increasing significance, are connected to respective BCD to 10 line decoders 274, 276 and. 278; Decoders 274, 276, and 278 are constructed identically to . previouslydescribed decoders 210 and 212, and provide a low level at the output corresponding to the BCD value of the input. Only selected ones of the 10 available outputs are used, namely, the zeroand one-tenths outputs of decoder 274, the zero-units output of decoder. 276, and the nine-tens output of decoder 278.

The aforementioned decoder outputs are connected through respective inverters 280(a)-280(e) as inputs to a pair of AND gates 282 and 284. Inverters 280(b), 280(c), and 280(d) are connected as inputs to AND gate 282, while the outputs of inverters 280(a), 280(c), and 280(e) are connected to AND gate 284. The control input for AND gate 284 is provided directly over a lead 286, while the same signal, coupled through an inverter 288, provides the control input for AND gate 282.

' Lead 286fis connected to advance-retard unit 56 (also shown in FIG. 1) which comprises a resistor R26 coupled to the positive power supply, to lead 286, and

to one of the fixed contacts of a two-position switch 288, the other contact of which is open, and the moving contact of which is grounded. The connected contact of switch 288 represents the retard mode of operation. Thus, with the switch in the retard position, the signal on lead 286 is low, inhibiting AND gate 284, and activating AND gate 282. Correspondingly, with switch 288 in the advance position, lead 286 is high, conditioning AND gate 284 and inhibiting AND gate 282.

From the above description of the interconnection between decoders 274-278, inverters 280, and AND gates 282 and 284, it may be seen that for retard mode timing, AND gate 282 operates to provide a high input to OR gate 290 only when the count contained in decade counter 272 is 001, i.e., the minimum possible delay. For advance mode timing, AND gate 284 provides a high input to OR gate 290 only when counter 272 is at a count of 900, i.e., a delay of 90 degrees.

Operation of counter 272 is controlled by the pseudo pulse output of OR gate 266 coupled through AND gate 52. The output of AND gate 52 is connected to the set input of a set-reset flip-flop 292, the reset input to which is provided through an AND gate 294. The latter receives as its inputs the pseudo damper signal output of OR gate 290 and the sample pulse signal produced by single shot 270. The zero output of flip-flop 292 is coupled over lead 296 to the reset input of counter 272.

' For a counter 272 constructed of three seriesconnecte'd Texas Instruments type SN-7490 decade units, the counter advances on a negative to positive transition of the clock signal, while a high level at the reset input returns all of the outputs to zero. Thus, as long as flip-flop 292 is reset, its zero output is high and counter 272 is held at a count of zero.

Upon arrival at an output from pseudo pulse generator 32, AND gate 52 operates and sets flip-flop 292. The zero output of the flip-flop then goes low,freeing counter 272 to advance in response to the clock pulses on lead 298. Decoders 274-278, inverters 280, and AND gate 282 provide an output through OR gate 290 after a single advance of counter 272 for retard operation, while decoders 274-278, inverters 280, and AND gate 284 provide an output through OR gate 290 after 900 counts (i.e., 90 degrees) for advance mode operation. In either case, the output of OR gate 290 actuates AND gate 294 and resets flip-flop 292, thereby terminating the operation of counter 272. Since each pseudo pulse reactivates the counter by setting flip-flop 292, the result is a series of pulses delayed with respect to the output of the pseudo pulse generator, either by I count or 900 counts for retard or advance mode operation, respectively.

One further point may be noted. Referring to Tables 1 and 2 above, it may be seen that for an eight-cylinder engine, the advance and retard mode pseudo damper pulses coincide. Thus, delay of the pseudo pulse generator outputs for advance timing of an eight-cylinder engine is not actually pg,45 Actuation of the delay unit is therefore inhibited for an eight-cylinder engine by means of a diode CR14 connected to the junction between lead 286 and resistor R26 and to the eightcylinder position of selector switch 64 by means of lead 300. With switch 64 in the eight-cylinder position, lead 300 is grounded, which overrides the operation of advance-retard switch 288 and assures the presence of a low signal level on lead 286.

Turning to FIG. 8, there is illustrated the important functional aspects of advance-retard logic unit 68, averaging logic unit 70, main counting logic unit 72, advance-retard switch 78, timing angle display unit 80, RPM counter unit 82, and RPM display unit 84.

As previously explained, timing is measured by counting the number of VCO pulses (each of which corresponds to 0.1 degree) between a spark pulse and the pseudo damper pulse for the associated cylinder. For retard timing, the pseudo pulse initiates the counting interval and the spark pulse terminates the counting interval. Conversely, for advance timing, the spark pulse initiates the counting interval and the pseudo pulse terminates the counting interval.

As illustrated in FIG. 8, the counting interval is defined by a set-reset cycle flip-flop 302 formed of a pair of cross-coupled NOR gates 304 and 306. F lip-flop 302 is set through a NAND gate 308 and reset through another NAND gate 310. The inputs to NAND gate 308 are provided by a further pair of NAND gates 312 and 314, while the inputs to NAND gate 310 are provided by a pair of NAND gates 316 and 318. The spark pulse from spark signal processer 24 provides one input to NAND gates 314 and 316, while the pseudo damper pulse signal from digital delay unit 54 provides an input to NAND gates 312 and 318. Control inputs for NAND gates 312 and 316 are provided over lead 320; this signal is high when the system is operating in the retard mode. A separate control signal is provides over lead 322 for NAND gates 314 and 318; this signal is high when the system is operating in the advance mode.

The signal levels on leads 320 and 322 are controlled by advarlce-retard unit 78. This comprises a pair of inverters 324 and 326, the outputs of which are respectively connected to leads 320 and 322 and the inputs of which are connected to the positive power supply through separate resistors R27 and R28. Also connected to the inputs of inverters 324 and 326, respectively, are the fixed retard and advance contacts of a two-position switch 328, the moving contact of which is grounded. When switch 328 is in the retard position, the output of inverter 324 is high, conditioning NAND gates 312 and 316. Conversely, with switch 328 in the advance position, the signal on lead 322 is high, conditioning NAND gates 314 and 318.

NAND gates 308 and 310 operate as OR gates with inverted inputs, i.e., provide a high output if either input is low. Thus, for retard mode operation, flip-flop 302 is set through NAND gates 308 and 312 by the pseudo damper pulse and is reset through NAND gates 310 and 316 by the next spark pulse. For advance operation, flip-flop 302 is set through NAND gates 308 and 314 by the spark .pulse and is reset through NAND gates 310 and 318 by the succeeding pseudo damper pulse.

The one output of cycle flip-flop 302 is connected over lead 330 to a further pair of NAND gates 332 and 334, control inputs for which are provided respectively over leads 322 and 320. NAND gates 332 and 334 are coupled to another NAND gate 336 which acts as an OR gate with inverted inputs and thus provides a high input to a further NAND gate 338 whenever cycle flipflop 302 is set.

The other input to NAND gate 338 is provided over lead 340 by the VCO output signal from phase locked loop 30. The output of NAND gate 338 is coupled to the advance input of a divide by 128 counter 342

Claims (33)

1. In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, said means for establishing said timing interval comprising a logic circuit having a first input receiving said reference pulses, and a second input receiving said ignition pulses; selection means for establishing retard and advance modes of operation; said logic circuit being responsive to selection of the advance mode to initiate a timing interval in response to an ignition pulse, and to terminate said timing interval in response to the next reference pulse, said logic means being further responsive to selection of the retard mode of operation to initiate a timing interval in response to a reference pulse, and to terminate said timing interval in response to the next ignition pulse, said logic circuit including a set-reset flipflop; means responsive to selection of the advance mode of operation for coupling said ignition pulses to the set input of said flip-flop, and the reference pulses to the reset input of said flip-flop, and further being responsive to selection of the retard mode for coupling the reference pulses to the set input of said flip-flop, and the ignition pulses to the reset input of said flip-flop; said logic further including means for coupling one output of said flip-flop to said gating means to actuate the same when said flip-flop is set.

2. A timing computer as defined in claim 1 wherein said control counting means comprises a counter, and means for operating said counter in response to transition of said flip-flop from the set to the reset condition.

3. In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said said storage means, said control means including calibrating means responsive to passage of a predetermined number of timing intervals to reduce the count stored in said main counter by a number corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston.

4. A timing computer as defined in claim 3 further including a calibration counter, means responsive to said control signal to establish a calibration interval; gating means coupling said master pulse train to the input of said calibration counter, said gating means being operative during said calibration interval to pass said master pulses to said calibration counter; means for reducing the count in said main counter in synchronism with the operation of said calibration counter; means responsive to a predetermined count in said calibration counter to terminate said calibration interval; means responsive to termination of said calibration interval to reset said calibration counter, whereby the count in said main counter is reduced by said predetermined number.

5. A timing computer as defined in claim 4 further including means responsive to establishment of said calibration interval to inhibit the establishment of further timing intervals until said calibration interval is completed.

6. In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means to counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, said control counting means comprising a second counter; means responsive to occurrence of a timing interval to increase the count in said second counter; means responsive to said second counter reaching a predetermined count indicating occurrence of the corresponding number of counting intervals for said main counter to generate said control signal; means responsive to said control signal and to said master pulse train to generate a second control signal a predetermined number of master pulses thereafter, and to generate a third control signal a predetermined number of master pulses after said second control signal; means for coupling said second control signal to actuate said angle readout storage means; and Means responsive to said third control signal for resetting said main counter.

7. A timing computer as defined in claim 6 wherein said means to generate said second and third control signals comprises a third counter, means for coupling said master pulse train to operate said third counter, and means responsive to said first control signal to reset said third counter.

8. A timing computer as defined in claim 7 wherein said means coupling said master pulse train to said third counter comprises a frequency divider having a counter base sufficiently large that the complete operating cycle of said third counter is shorter than the operating cycle for said second counter.

9. A timing computer as defined in claim 7 further including calibration means responsive to said control signal to reduce the count stored in said main counter by a number corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston.

10. A timing computer as defined in claim 9 wherein said calibration means comprises a fourth counter; means responsive to said control signal to establish a calibration interval; gating means coupling said master pulse train to the input of said fourth counter, said gating means being operative during said calibration interval to pass said master pulse train to said fourth counter; means for reducing the count in said main counter in synchronism with the operation of said fourth counter; means responsive to a predetermined count in said fourth counter to terminate said calibration interval; and means responsive to termination of said calibration interval to reset said fourth counter.

11. A timing computer as defined in claim 10 further including means responsive to establishment of said calibration interval to prevent the establishment of further timing intervals for said main counter, and to inhibit operation of said third counter until said calibration interval has been terminated.

12. A timing computer as defined in claim 11 wherein said third counter is operative to generate said second control signal a predetermined number of counts after operation thereof is permitted to resume after termination of said calibration interval.

13. In an engine timing apparatus for internal combustion engines, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; a timing computer, said timing computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an ignition pulse and a reference pulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; control means to operate said main counter for a predetermined interval and thereafter to actuate said angle readout means and to reset said main counter, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of at least one timing interval to generate a control signal, means responsive to generation of Said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means, and further including engine speed computing means; limit logic to establish a maximum acceptable engine speed; means responsive to the sensing of an engine speed exceeding the preset limit to generate a limit signal; and means responsive to said limit signal to disable said timing angle readout unit.

14. A timing computer as defined in claim 13 wherein said engine speed computing means comprises a counter, means coupling said master pulse train to operate said counter; engine speed readout means comprising means for storing a count contained in said engine speed counter, and visual display means for said stored count; clock means for producing a periodic signal defining an engine speed computation interval; means responsive to the end of a computation cycle to generate a further control signal; means responsive to said first control signal for operating said storage means to store the count then contained in said engine speed counter; further means responsive to said further control signal to generate an additional control signal a predetermined time thereafter; and means responsive to said additional control signal to reset said engine speed counter.

15. A timing computer as defined in claim 14 wherein said coupling means comprises a frequency divider, the counting base of said divider and the duration of said computing interval being so selected in relation to the number of master pulses per engine revolution that the count contained in said speed counter at the end of the computation interval is equal to the average engine speed in RPM during the computing interval.

16. A timing computer as defined in claim 14 wherein said limit logic comprises first circuit means coupled to said engine speed counter, a plurality of set-reset flip-flops, said first circuit means being operative to set said flip-flops in a predetermined order as the count in said speed counter increases by predetermined increments whereby, at the end of said computation interval one or more flip-flops are set indicating the number of incremental advances of said engine speed counter during said computation interval; latching means having individual latch circuits connected to the outputs of respective ones of said flip-flops; said latch circuits being responsive to said further control signal to store respective signals indicative of the states of the associated flip-flop at that moment; means responsive to said additional control signals to reset said flip-flops; sensing means responsive to a particular signal level stored in a latch circuit indicating that the associated flip-flop has been set; limit selection means for connecting said sensing means to the output of a particular one of said latch circuits thereby selecting the engine speed range at or above which said sensing means is operative to generate said limit signal.

17. A timing computer as defined in claim 13 wherein said limit logic comprises multistate means coupled to said engine speed computer, and operative to assume a predetermined one of its states in correspondence to the computed RPM falling within one of a succession of incremental ranges; limit selection means for establishing one of said states as corresponding to an excessive engine speed; means for sensing when said selected state has been reached, and operative thereupon to generate said limit signal for inhibiting said angle readout.

18. A timing computer as defined in claim 13 further including angle range computation means comprising means for selecting target and tolerance values for the timing angle; means for comparing the count in said main counter with the range established by said target and tolerance values, and logic means to generate a first signal indicative that said acTual count exceeds the maximum acceptable value, a second signal indicating that said actual count is within the selected tolerance range, and a third signal indicating that said count is below said lower tolerance limits.

19. A timing computer as defined in claim 18 wherein said angle range computing means comprises first and second computation counters; means to enter a count in said first and second counters corresponding to the selected target angle; means to increase the count in said first counter by a count equal to the selected tolerance, means to decrease the count in the second counter by a number of counts corresponding to the selected tolerance; a first comparator coupled to said main counter and to said first computation counter; a second comparator coupled to said main counter and to said second computation counter; and logic means coupled to said first and second comparators to provide said first indication if the count in said main counter exceeds that in the first computation counter, to provide said second indication if the count in said main counter is less than or equal to the count in said first computation counter and is greater than or equal to the count in said second computation counter, and said third indication if the count in said main counter is less than that in second computation counter.

20. A timing computer as defined in claim 19 further including means to preset said main counter and said first and second computation counters to a reference count such that the total count in said second computation counter, including said reference count plus the difference between said target count and said tolerance count, does not fall below zero.

21. An averaging computer for an internal combustion engine timing apparatus, said apparatus having means to generate a pulse coincident with each ignition of the engine being timed, means to generate a master pulse train having a constant number of pulses per engine revolution, each pulse representing a fraction of said engine revolution, and means to generate a succession of reference pulses establishing a predetermined angular position away from top dead center of each piston, measured in relation to rotation of the engine crankshaft, there being one reference pulse for each piston ignition over each cycle of ignition firings; said averaging computer comprising: means for establishing a timing interval between an ignition pulse and an associated reference pulse, said timing interval establishing means comprising means for producing a train of timing pulses with each timing pulse being defined by an igntion pulse and referencepulse; gating means receiving said master pulse train, and being operative during said timing interval to provide said master pulse train at the output thereof; a main counter; means coupling the output of said gating means to the input of said main counter, said coupling means comprising frequency division means having a division base N; a timing angle readout unit including data storage means coupled to the output of said main counter, and means for providing a visual display of the data contained in said storage means; and control means for said averaging computer, said control means comprising means for counting the number of timing intervals, means coupled to the output of said counting means and responsive to passage of a total of N timing intervals to generate a control signal, means responsive to generation of said control signal for actuating said storage means to store the count contained in said main counter at that time, and further means responsive to generation of said control signal for resetting said main counter after the data therein has been transferred to said storage means; said number N being in excess of the number of cyclinders in the engine being timed; whereby the count transferred to said storage means represents the average number of fractional parts of an engine revolution contained in the previously measured N timing intervals.

22. A timiNg computer as defined in claim 21 wherein said number N is an integral multiple of the number of cylinders in the engine being timed.

23. A timing computer as defined in claim 21 wherein said control means includes calibrating means responsive to passage of a predetermined number of timing interals to reduce the count stored in said main counter by a number corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston.

24. A timing computer as defined in claim 21 further including engine speed computing means; limit logic to establish a maximum acceptable engine speed; means responsive to the sensing of an engine speed exceeding the preset limit to generate a limit signal; and means responsive to said limit signal to disable said timing angle readout unit.

25. A timing computer as defined in claim 24 wherein said limit logic comprises multistate means coupled to said engine speed computer, and operative to assume a predetermined one of its states in correspondence to the computed RPM falling within one of a succession of incremental ranges; limit selection means for establishing one of said states as corresponding to an excessive engine speed; means for sensing when said selected state has been reached, and operative thereupon to generate said limit signal for inhibiting said angle readout.

26. A timing computer as defined in claim 21 further including angle range computation means comprising means for selecting target and tolerance values for the timing angle; means for comparing the count in said main counter with the range established by said target and tolerance values, and logic means to generate a first signal indicative that said actual count exceeds the maximum acceptable value, a second signal indicating that said actual count is within the selected tolerance range, and a third signal indicating that said count is below said lower tolerance limits.

27. A timing computer as defined in claim 21 wherein said means for establishing said timing interval comprises selection means for establishing retard and advance modes of operation; a set-reset flip-flop; logic means responsive to selection of the advance mode of operation for coupling the ignition pulses to the set input of said flip-flop, and the reference pulses to the reset input of said flip-flop, said logic means further being responsive to selection of the retard mode for coupling the reference pulse to the set input of said flip-flop, and the ignition pulses to the reset input of said flip-flop; means for coupling one output of said flip-flop to said gating means to actuate the same when said flip-flop is set.

28. A timing computer as defined in claim 27 wherein said interval counting means comprises an N-bit counter; means responsive to transition of said set-reset flip-flop to its reset condition to increase the count in said N-bit counter by one bit; means responsive to said interval counter reaching a count of N to generate said control signal; a third counter, means for coupling said master pulse train to operate said third counter; means coupled to said third counter, and responsive to particular count states thereof to generate second and third control signals at predetermined intervals after said first control signal; means for coupling said second control signal to actuate said angle readout storage means; means responsive to said third control signal for resetting said main counter, and means responsive to said first control signal to reset said third counter.

29. A timing computer as defined in claim 28 further including calibration means responsive to said first control signal, said calibration means comprising a fourth counter; means responsive to said first control signal to establish a calibration interval; gating means coupling said master pulse train to the input of said fourth counter, said gating means being operative during said calibration interval to pass said master pulse train to said fourth counter; means for reducing the count in said main counter in synchronism with the operation of said fourth counter; means responsive to a predetermined count in said fourth counter corresponding to the angular position of said reference pulses in relation to top dead center for the associated piston to terminate said calibration interval; means responsive to termination of said calibration interval to reset said fourth counter, and means responsive to establishment of said calibration interval to prevent operation of said set-reset flip-flop, thereby preventing establishment of intervals for said main counter during said calibration interval, and further means to prevent operation of said third counter during said calibration interval.

30. A timing computer as defined in claim 21 further including engine speed computing means comprising an engine speed counter; frequency division means coupling said master pulse train to operate said engine speed counter; engine speed readout means comprising means for storing a count contained in said engine speed counter, and visual display means for said stored count; clock means for producing a periodic signal defining an engine speed computation interval; means responsive to the end of a computation cycle to generate a further control signal; means responsive to said further control signal for operating said storage means to store the count then contained in said engine speed counter; means responsive to said further control signal to generate an additional control signal a predetermined time thereafter; and means responsive to said additional control signal to reset said engine speed counter, the counting base of said frequency divider and the duration of said computing interval being so selected in relation to the number of master pulses per engine revolution that the count contained in said speed counter at the end of the computation interval is equal to the average engine speed in RPM during the computing interval.

31. A timing computer as defined in claim 30 further including a limit logic for establishing a maximum acceptable engine speed, comprising first circuit means coupled to said engine speed counter, a plurality of set-reset flip-flops, said first circuit means being operative to set said flip-flops in a predetermined order as the count in said speed counter increases by predetermined increments whereby, at the end of said computation interval one or more flip-flops are set indicating the number of incremental advances of said engine speed counter during said computation interval; latching means having individual latch circuits connected to the outputs of respective ones of said flip-flops; said latch circuits being responsive to said further control signal to store respective signals indicative of the state of the associated flip-flop at that moment; means responsive to said additional control signals to reset said flip-flops; sensing means responsive to a particular signal level stored in a latch circuit indicating that the associated flip-flop has been set to generate a limit signal; selection means for connecting said sensing means to the output of a particular one of said latch circuits thereby selecting the engine speed range at or above which said sensing means is operative to generate said limit signal; and means responsive to said limit signal to disable said timing angle readout unit.

32. A timing computer as defined in claim 21 further including angle range computing means comprising first and second computation counters; means to enter a count in said first and second counters corresponding to a selected target timing angle; means to increase the count in said first counter by a count equal to a selected tolerance angle; means to decrease the count in the second counter by a number of counts corresponding to the selected tolerance; a first comparator coupled to said main counter and to said first computator counter; a second comparator coupled to said main counter and to said second compuation counter; and lOgic means coupled to said first and second comparators to provide a first indication if the count in said main counter exceeds that in the first computation counter, to provide a second indication if the count in said main counter is less than or equal to the count in said first computation counter and is greater than or equal to the count in said second computation counter, and a third indication if the count in said main counter is less than that in second computation counter.

33. A timing computer as defined in claim 32 further including means to preset said main counter and said first and second computation counters to a reference count such that the total count in said second computation counter, including said reference count plus the difference between said target count and said tolerance count, does not fall below zero.

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