US3746799A

US3746799A - Method and apparatus for encoding and decoding analog signals

Info

Publication number: US3746799A
Application number: US00183835A
Authority: US
Inventors: F Gentges
Original assignee: US Department of Navy
Current assignee: US Department of Navy
Priority date: 1971-09-27
Filing date: 1971-09-27
Publication date: 1973-07-17
Anticipated expiration: 1990-07-17
Also published as: CA976089A

Abstract

A method and apparatus for encoding and decoding clear signals of an analog nature, the amplitudes of which represent information. The method employs a key which controls the coding of the signals, a module shift and the coding of the moduloshift, the modulo shift being transmitted by time multiplex or on a separate channel from that of the encoded signal.

Description

il'nited States Patent [191 Gentges [451 July 17, 1973 METHOD AND APPARATUS FOR ENCODING AND DECODING ANALOG SIGNALS [75] Inventor: Frank H. Gentges, Temple Hills, Md.

[73] Assignee: The United States of America as represented by the Secretary of the Navy, Washington, D.C.

[22] Filed: Sept. 27, 1971 [2]] Appl. No.: 183,835

[52] CI. 178/22, l79/1.5 R [51] Int. Cl. H041 9/02 [58] Field of Search 178/22; 179/15 R;

[56] References Cited UNITED STATES PATENTS 3,507,980 4/1970 Rugaber et a1 I79/l.5 R

e A/D CONVERTER I ADDER KEY 2 SHIFT A/D CONVERT ER 1 3,291,908 12/1966 Ehrat 178/22 3,180,927 4/1965 Heppe et al.. 179/].5 R 3,427,399 2/1969 Ehrat 178/22 FOREIGN PATENTS 0R APPLICATIONS 929,251 4/1961 Great Britain l79/l.5 R

Primary Examiner-Benjamin A. Borchelt Assistant Erar r zinep-H. A. Birmie l V l Attorney- R. S. Sciascia, Arthur L. Brannmg et al.

[57] ABSTRACT A method and apparatus for encoding and decoding clear signals of an analog nature, the amplitudes of which represent information. The :method employs a key which controls the coding of the signals, a module shift and the coding of the modulo-shift, the modulo shift being transmitted by time multiplex or on a separate channel from that of the encoded signal.

9 Claims, 5 Drawing Figures FF lt --m ADDER CARRY MODULO SHIFT PATENTEB i 7 B73 SNEEFBBFS All C2 INVENTOR FRANK H. GENTGES ATTORNEY i PATENTEB SPEU 5 BF 5 $55? "GEE INVENTOR FRANK H. GENTGES ATTORNEY METHOD AND APPARATUS FOR ENCODING AND DECODING ANALOG SIGNALS STATEMENT OF GOVERNMENT INTEREST The invention described herein may be manufactured and used by or for the Government of the United States of America for government purposes without the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION Presently used cryptographic equipment is based upon a technique described by Vernam. With this technique the data to be enciphered is combined with an enciphering key, the resultant being ciphertext. To decode the ciphertext an identical key to that used for enciphering is generated and the data is derived from the ciphertext. With this technique it is necessary that the data be in the form of binary bits. If the data is in some other form, then some means for converting it to binary bits is necessary. Likewise, on the receiving end, some means is needed for converting the binary bits back to the original form of the data.

Vernam described a system using punched tape such as used with teleprinter equipment. In his system one tape containing the message was combined with another tape which served as the key. A special tape reader is used which advances both tapes together as the bits for each character are read the same number of bits of key for enchiphering are also read. The combining is done as follows:

1. If the key bit is a zero, the corresponding data bit I is sent as is.

2. If the key bit is a one, the corresponding data bit is sent inverted, i.e., data l, cipher 0,; data 0, cipher 1. This type of combining is mathematically called module two addition and the logic function is realized with an exclusive OR gate. This may be shown in a logic table as:

Date 0 0 l 1 Key 0 l 0 1 Output 0 l l 0 (Ciphertext) The same logic function is used to recover data from ciphertext.

Ciphertext 0 Key 0 Output 0 (Data) From this, the following table can be constructed to show that indeed for all cases of key and data, proper data is recovered on the receiving end Send Received Data Key Ciphertext Data 1 l 0 l l 0 l l 0 l l 0 0 0 0 O and thus logically asumed deduce a large block of the key. The key should have properties to make this information useless. The first is that given any arbitrarily large block of key no further bits on either side can be logically deduced. This prevents being able to enter the ciphertext at one point and obtaining further data by reconstructing additional key. The second property is that given any arbitrarily large block of key, all other blocks of the same length of any combinations of ones and zeros would appear equally probable. This prevents being able to assume a message and then by looking at the key necessary to generate the ciphertext de termine how probable the assumed message is. There are two basic techniques used for generating key of this type. The first is to sample a random process. For example, this could be a noise source or a nuclear event. The second is to devise an interconnection of digital logic that will appear noise-like and meet all the criteria. One advantage of this approach is that several of these computing devices can be built and changing the key only involves changes to the computing logic wiring rather than the transporting the entire quantity of new key bits between the transmitting and receiving end. It has the disadvantage that for a finite computing system that the criteria can only be approached rather than met. Considerable work has been done to design computing systems which meet the criteria as closely as possible with minimum computing complexity. As a result, these computing systems strive to make the breaking of the code impractical while maintaining reasonable cost.

N ON-DIGITAL DATA If the data to be enciphered is not digital, it is necessary to convert it to digital form so this technque can be used. The enciphered output is digital and this requires that the communication link be a digital one. In the case of signals which were digital in origin the enciphering imposes no additional hardship in transmission since they require digital transmission without enciphering. For analog signals, however, enciphering can impose serious transmission problems. In many of these cases, the transmission of the non-digital signal is trivial compared to the transmission of the equivalent digital signal.

VOICE One example of this is encrypted voice. First, the voice is digitized, then encrypted, and then the digital data is transmitted. On the receiving end, the digital stream of data is recovered, deciphered, and then the digital is converted back to voice. Where wide bandwidths are available such as with UHF radio, or short length telephone lines the available bit rate is high enough so the conversion from voice to digital and digital to voice is relatively simple. However, the transmission bandwidth required is at least 6 times that of the original speech. It is possible, then to trade bandwidth for equipment complexity. For communication links where the additional bandwidth becomes costly it becomes necessary from an economic point of view to increase equipment complexity and cost to realize greater savings in the communications link. This may be approached in two ways. First, the device that converts the digital data to form for transmission through the communication link can be optimized to give more bits per unit bandwidth. There are certain fundamental limitations to how much can be done in this area. About the best that can be done is to reduce the 6 to 1 down to 2 to l.

The second approach is to process the speech in some way so that the bit rate is reduced. This is normally done with a vocoder. The major problem is that the speech on the receiving end sounds unnatural and synthetic. In general, the higher the bit rate with a vocoder, the more natural it will sound and the less complex it will be. As a result a number of tradeoffs can be made between vocoder complexity and data transmission equipment complexity. No balance, however, re duces the complexity of the voice to digital converter, the data transmission equipment, and reduces the bandwidth all at the same time.

FACSIMILE & TELEVISION With facsimile and television the same basic problems as encountered with voice apply. The bandwidth required for the digital is much greater than that for the equivalent analog. For a 4.5 MHz bandwidth color television signal, the digital bit rate is 40 Meg'abits/second.

As with voice there are techniques for reducing the bit rate. The simplest and the only one being used to any extent is to eliminate shades and colors. This produces black or white with no grays. This operates satisfactorily for written or printed line copy but it is not suitable for pictures. Present facsimile equipment, when operated in this mode, maintains about the same resolution while requiring the same bandwidth as that for unsecure facsimile with gray scale. Thus it can be seen, that for non-digital signals, considerable effort may be needed above and beyond the actual encrypting process. It would be desirable, if possible, to find some type of newtechnique which would lend itself more readily to these non-digital signals.

CRITERIA FOR THE TECHNIQUE Any new technique should meet a basic set of criteria in order for it to be useful. These criteria are security and communicability. First, the technique should reduce the intelligence to a low enough level on the cipher output that it will be impossible to break the ciphering. Second, the nature of the signal on the cipher side should be such that it will be transmitable over identical facilities to that used for the enciphered signal and medium distortions encountered in the transmission should affect the signal on the deciphered receive end the same as for the unenciphered. In order for the technique to be widely applicable we shall restrict the device which uses the technique to a black box which accepts a varying voltage on the input and produces a varying voltage on the input and on the cipher output. The varying voltage on the input shall be restricted between and +E and bandwidth of 0 Hz to f}. The cipher output shall be a varying voltage between 0 and e and a bandwidth of 0 to f,,. The cipher output voltage e, =f(e t) where fis the ciphering function. Having established the two basic criteria and restricting to the above, additional criteria can be defined.

SECURITY For security the following criteria may be established:

Criteria 1. At any time t, and for any e e, shall have equal probability of being any voltage from 0 to Criteria 2. For any aribitrary time increment greater than l/f from an origianl e,,, a new s shall have equal probaility of being any value from 0 to E Criteria 3. Given any waveform of any arbitrary length, restricted in amplitude from 0 to E the probability of its occurrence will be equal to that of all other waveforms of the same length that are restricted to have frequency components between 0 and f,,. Criteria 1 establishes that the cipher output voltage is independent of the input voltage when observed only from the cipher output. For example, the cipher would appear to be changing in a random fashion when the input were at a steady e voltage. It would also appear random when the input were at 0 volts or at any other voltage.

Criteria 2 establishes that when observing incremental changes in that cipher no information can be gained above the input.

Criteria 3 establishes that with an observed cipher, it is not possible to establish higher probability of one input over another.

Criteria 2 and 3 are explicitly implied in Criteria 1. They are listed for sake of clarity.

COMMUNICABILITY For communicability the following criteria may be established:

Criteria 4. If in the communication link the cipher signal is perturbed by some amount e,,, the deciphered output should be perturbed by no more than +e,,.

ANALOG CIPHER COMBINER Consider the following ciphering function:

omar lma: kmar ma: and e being a ciphering key let e, e, e mE,,,

Then the deciphering function will be:

e e,, e mE where both e are the same Let e be a randomly varying voltage varying between 0 and E with all voltages in that range equiprobable and bandlimited between 0 and f Hz. Let the term modulo shift refer to m I. No modulo shift will refer to m 1.

For e, the deciphered output, it may be observed that it is equal to e, when the communication media for e, is not bandlimited nor dispersive. For the case where =f =f,,, and the communication media is also bandlimited to fl, and meets Nyquists first criteria then e e, when a shift into or out of modulo has not occurred. If a sampling process is introduced where e, is sampled at a rate 2 2f,,, then e, sampled at a delay time later equal to the communication delay, it will be observed that e, at t+ At will equal e at time t. This is true even with modulo shifting.

For any value of e, from O to E it may be observed that all values for e, from O to E are equiprobable. This is best illustrated with a set of transfer curves. For various values of e, see FIG. 1.

The receive end must determine if it should use m O or m 1. This may be done in two ways, by inference or by direct transmission.

INF ERENCE DIRECT TRANSMISSION The modulo shift command can also be transmitted separately and since it is a signal that carries information, it should be enciphered. Since it is a two state signal it can be enciphered. It can either be transmitted through a separate channel in the medium or time multiplexed with the data. Either way additional bandwidth of at least f,, is required (assuming an m-ary technique with m greater than 2 is not used), with the resulting total bandwidth of at least 2f,,. Thus the invention trades bandwidth for signal to noise while the inference method trades signal to noise for bandwidth.

TRANSMISSION ERRORS Because errors in modulo shift and errors in the data have different effects they will be considered separately.

ADDITIVE ERRORS IN DATA If the received signal is perturbed by an amount e by the transmission media the output e, will be perturbed by the amount e,,. This can be shown by Thus if 2,, is a constant D.C. level offset, the received signal e, will have the same offset. If e,, is noise, then 2, will have the same noise, and there will be no increase in signal to noise ratio over the unenciphered system.

MULTIPLICATION ERRORS IN DATA If the transmission system gain is not unity, but instead is l k where k is the deviation from the unity gain, then e, as received will be e' as shown by;

Since e,, is a randomly varying voltage, e,,.l( is a randomly varying voltage on the output and will appear as noise with a peak to peak amplitude of E K.

MODULO SHIFT ERRORS Modulo shift errors occur when either a modulo shift is interpreted as no shift or no modulo shift is inter preted as a shift. Referring back to equations (1) and (2) it may be stated that modulo shift errors cause m O to be deciphered by m 1 instead of m 0 and m l deciphered by m 0 instead! of m l. The error in e, would be: 1

from Equation (1) NO MODULO SHIFT e, e, e and substituting in equation 2 ma: 1+ k k ma: and substituting l 1: ma: k mar Thus, for either modulo shift error, e, is in error by an amount equal to E the sign of which is dependent on which error occurred. If modulo shift commands are derived from inference, perturbation in the transmission medium can cause them to be in error. For no modulo shift the perturbation necessary will be and assume e,, e;,, the transition point, for the modulo shift condition, then e, e,,.

and for modulo shift Thus, if the perturbation is either: greater than or equal to the voltage difference between the two extremes of e, (0 and E and e, then a modulo shift error may occur (depending on the sign of e,,). D.C. errors in s will reduce the level of e, on one end that would cause a shift error while increasing on the other end. Therefore, the inference method can be used if the following restrictions are applied while still not as desirable as direct transmission.

mar rr max) where e is the maximum positive perturbation and l maa:

is the maximum negative perturbation.

AFFECT OF TIME DISPERSION Time dispersive affects in the communication medium will have the affect of adding e s from other points in time to the main 2,. Since all other e s are random in level, they will add together to form a e, which is random. Thus the affect of dispersion is to add noise to the final e,.

AFFECT or NONLINEARITY Nonlinearities in the system will create some error between the e, sent and the 2,, received. This difference can be considered as an e,,. Since e varies randomly, these nonlinearities will introduce e s varying randomly. The net effect will be additional noise in e,'.

SOURCE OF KEY One method of generating key is to load a register with random binary bits. Then converting, by 2" weighting, these bits into an analog key. These bits could be from the same type of source as is used for the Vernam system. If the binary key satisfies the criteria provided an infinite length of bits is used for each analog level. If a finite number of bitsis used and a dither noise injected whose peak to peak level is about equal to the voltage value of the least significant bit, then the same output would be obtained as with the infinite register. e, would have a noise equal to the dither noise since presumably, it is not reproduced at the receiving end. The least significant bit can be made arbitrarily small in value to reduce the dither noise to a level that will not degrade the performance of the system.

There is a very real need for the dither. Consider an unfriendly entity observes the output and notes that it varies between and E And then he notes at a time when e, is at a constant level for a number of frame periods that e, is always in integral multiples and E the maximum positive excursion of es is 2' times this multple. Then if he takes each e,,, and subtracts it from the previous e,,, and divides it by the next lower integral step he can make the following premise: the change in e, between the two periods is equal to this residue plus or minus some integral step. For small voltage changes in e, this integral step could be small and the waveform reconstructed by trial and error.

COMMUNICATION MEDIUM CONSIDERATIONS Until now, the medium has been assumed to have response to zero cycles, and it can be shown that circuits without D.C. response have a form of additive error. Communications circuits in general do not have this type of response. Most circuits also do not have an accurate gain so they suffer from multiplicative errors. Therefore, the baseband cipher will require some form of modulation demodulation with a carrier to overcome these problems. FM has the advantage that gain changes in the communication circuit do not cause multiplicative errors on the output. It also can provide D.C. response without a great deal of effort.

Considerable work has been done in telemetry with FM carrier transmission of signals with D.C. components. These signals are often quantities that must be transmitted accurately and the equipment they use has been designed to be quite accurate. The accuracy is often as good as 1 percent. When used with this ciphering technique, e would equal 1 percent of E This would give a deciphered output accuracy of one percent or a signal to noise ratio of 40 db if it is assumed that the cipher and decipher process has no error.

It appears that FM would be the best technique to use for this ciphering system. It should be noted that the FM equipment used in telemetry is highly versatile. As a result it is much more complex and expensive than that needed for a specific communication requirement using this ciphering system and cost comparisons cannot be made.

SUMMARY OF THE INVENTION The invention includes method and apparatus for enciphering analog signals including a modulo shift. The encoded signal and encoded moduloshift may be transmitted by either time multiplex or separate channels. The received encoded signal is then decoded to its original analog or digital signal. One implementation employs analog weighting of the signal and modulo shift and the separate transmission of the two signals. A second implementation employs binary weighting of the signal and a moduloshift and transmission by time multiplex.

STATEMENT OF OBJECTS OF THE INVENTION One object of the invention is to provide an improved method of coding and decoding analog signals.

Another object is an improved analog implementation of a coding and decoding system.

A further object is an improved binary implementation of a coding and decoding system.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows transfer curves for e,,.

FIG. 2 shows apparatus for two channel binary.

FIG. 3 shows apparatus for two channel analog.

FIG. 4 shows apparatus for time division multiplex binary.

FIG. 5 shows apparatus for time division multiplex analog.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 2', which shows a two channel implementation with binary weighting, the input signal e, is A to D converted in converter 10, the binary output of which is connected a first input of binary full adder 12 which includes the flip flop shown. An encrypting key, a six bit binary word, is added in adder 12 to the binary output of converter 10. The encrypted output of the adder 12 is connected to a six stage shift register 14 having the stages summed through operational amplifier 16. The shift register 14, summing network and operational amplifier l6 convert the adder output back to an analog signal whose value may vary from 0 to 63. The last carry output of the adder determines the moduloshift and is modulo two added to the last bit of key to determine the encrypted modulo shift signal by Exclusive-ORing the carry and key bits in exclusive OR gate 17. The last change of the output of gate 17 is stored in flip-flop 18 to be sampled to some time after the input signal e, and the key have been added. Adder 12 thought a full adder can only add up to 63 or 6 bits of information. Therefore should the key and e, when added be greater than 63 the carry is not added to register 14 but it is lost and thereby provides the modulo shift. And thus the last carry bit and the last bit of key determines the encrypted modulo shift e The modulo shift e and the encrypted output of operational amplifier 16 e are then separately transmitted to a receiver where the signals are deciphered.

In the receiver the received e is A to D converted in converter 20 and fed to an adder 22. The received e,,,, is gated through exclusive OR gate 24 by the conjugate of the key. e and the most significant bit of the key thereby recover the original carry bit which may have been lost due to the overflow of adder 12. This original carry bit is stored as the most significant bit (here 2") the shift register 26. In adder 22 the enciphered e, is added to the conjugate of the key thereby effectively subtracting the key from the enciphered e,,, which is fed into shift register 26. This supplies the 2 through 2 bits of the word or number stored in shift register 26. The most significant bit, 2, is supplied by exclusive OR gate 24 which has removed the encrypting key from the original carry bit. Thus the input e, is represented in binary in shift register 26. This binary number is D to A converted by a summing network and operational amplifier 28. The output of operational amplifier 28 is sampled by gate 30 which is part of a sample and hold circuit 32. The output is sampled by gate 30 at a time after the receipt of the modulo shift. Thus, the output a, is an analog signal proportional to input e Summarizing the operation of FIG. 2, the input signal e, is A to D converted. A key is added to e the result is modulo shifted if necessary. The modulo shift indication is encrypted as e,,,,. The encrypted input signal is D to A converted (e,,) and transmitted separately along with e which indicates the state of the modulo shift. e, and e,,., are received. e is A to D converted; and key is subtracted supplying the least significant bits of the original word or number. e,,,, is deciphered using the last bit of key supplying the most significant bit of the original word or number which is D to A converted. It is of course recognized that at the end of each complete transition of a word or number all components must be reset or cleared before the next data is entered.

In FIGS. 3 and S the key is the encrypting key plus a modulo shift bit in the most significant plate to encrypt the modulo shift.

FIG. 3 shows a two channel analog embodiment of the invention. The key is fed into seven bit shift register 34 the first six ouputs of which are summed with a dither voltage and added to the input signal in analog adder 36. Neglecting the dither voltage which is left in the final output 2, signal and would appear as a noise type signal, the output of adder 36 is (e, e which is fed to analog adder 38 and also to comparator 40 which closes gate 42 when e, e E (i.e., I -(e 2,.) I E,,,,,, I The closing of gate 42 applies +E to adder 38 the output of which will be e, e minus E should there be a modulo shift indicated by comparator 40. The output of comparator is encrypted by the most significant bit of the key (the 2 bit of shift register 34) by exclusive OR gate 43. This encrypted signal e is stored in flip-flop 44 for transmission when a sample pulse is supplied to gate 46 of the sample and hold circuit 48. The sample pulse should be supplied at some time after the last bit of key is supplied to register 34. The sample and hold circuit 48 holds the encrypted signal e, for transmission.

In the receiver portion the key is fed into shift register 50 and as in the transmitter portion the first six bits of key are summed and then fed to an inverter 52 the output of which is e which is summed in analog adder 54. The most significant bit of the key is fed to exclusive OR gate 56, to decipher e the output of which determines whether +E,, should be added to 2 Thus it is seen that the output of analog adder 54 is a voltage representative of e, at a time after when a change in moduloshift has been detected, of course the key being added,; during this time the sample and hold circuit samples the output of 54 and we have a final output e FIG. 4 is an embodiment of the invention which employs time multiplexing and binary enciphering. This embodiment is very similar to that of FIG. 2 but is adapted for time multiplex. The input signal is applied to A to D converter 60. The binary output of converter 60 is then added to the key in adder 62. As in FIG. 2 the key a six bit word and e, has a value between zero and 63. The output of the adder 62 will be a value between zero and 63 plus a one or zero carry bit when the addition is complete. The least significant bits of the output are entered in shift register 64 and D to A converted by the summing network and operational amplifier 66. Thus an analog value of e between zero and 63 is presented to gate 68 of sample and hold circuit 70.

The carry output of the adder 62 is encrypted by the last bit of key in exclusive OR gate 72 and presented to gate 74 of sample and hold circuit 70. The

gates

68 and 74 are then operated sequentially with 68 operating first; and e,,/e,,,,, is transmitted by time multiplex in a single frame.

In the receiver the transmitted e /e are received, and applied to A to D converter 76 and sampling comparator 78. As the received frame signal comprises e an analog signal may vary from 0 to 63, followed by e,,,,, which is either one or zero. These two signals must be separated. This is done by pulsing the A to D converter to sample only during the first half of a received signal frame. Thus only e is sampled and A to D converted. The output of converter 76 is coupled to adder 80 as is the conjugate of the key. Adder 80 effectively subtracts the key from the converted e, and this output is fed into the first six positions of shift register 82. Sampling comparator 78 is pulsed to sample e,,,,, which is either an analog one or zero and gives a binary output of one or zero which is fed to exclusive OR gate 84. Where e is deciphered by the conjugate of the key. The resulting moduloshift signal is: then entered in the most significant position of register 82. It should be noted that the last stage of registers 82 and 26 (of FIG. 2) are controlled by the modulo shift signal and not by changes of state of the previous stage, i.e., the last stage is in essence a separate stage. The contents of the shift register 82 are now D to A converted by the summing resistors and operation amplifier 86 and presented to gate 88 of sample and hold circuit 90 where the deciphered output e; is sampled at some time after e is sampled; and before the system is cleared for the next bit of data.

Referring now to FIG. 5 which is an analog embodiment similar to FIG. 3 using time multiplex, e, is summed with the seven bit key (six bits key plus one for modulo shift) from shift register in analog adder 102 the output of which is (e, e,-, the dither voltage (which will not be further mentioned). Comparator 104 determines the need for a modulo shift if -(e, e --E Should e, e E then gate 106 closes and allows +E to be added to (e, e,.) in analog adder which effectively subtracts +E,, from e, e to provide a modulo shift. The output of 108 is presnted to gate 110 of sample and hold circuit 112. The most significant bit of the key is used to encipher the modulo shift output of comparator 104 in exclusive OR gate 114. The output of exclusive OR gate 114. The output of exclusive OR gate 114 is presented to gate 133 of sample and hold circuit 134. The output of which is connected to gate 116 of example and hold circuit 112. Gates 110 and 116 are operated sequentially with gate 110 being operated first to sample e for transmission and then gate 116 being operated to sample the encrypted modulo shift e for transmission in the same frame. On reception of the signal at the receiver gate 1 18 of sample and hold circuit 120 opens to allow sampling of e,, and then gate 122 opens the sample supply e,, to exclusive OR gate 124. The modulo shift is deciphered in exclusive OR gate 124, by the most significant bit of the key, which is in shift register 126; and fed to gate 128. Gate 128 supplies +E (modulo shift) to be added if exclusive OR gate 124 output is a one. Key e from shift register 126 is also supplied to inverter 130. Analog adder 132 effectively subtracts e from e and adds in the modulo shift if required and an output is presented at gate 138 of sample and hold circuit 137 which is proportional to e The output of sample and hold circuit 137 being e Gate 138 is opened to sample just after gate 122 has been operated, i.e., during the time e,,., is present.

Thus'it is seen that what is disclosed is a'system for encrypting an analog signal by adding a key, moduloshifting the result, if necessary, encrypting the modulo shift signal and transmitting both the encrypted analog and modulo shift signals.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

What is claimed and desired to be secured by letters 7 patent of the United States is:

1. Apparatus for encoding and decoding analog signals comprising:

adding means for adding a pseudo random binary key to a first signal to produce a second signal and for producing a third signal indicating whether module addition has occured; in said adding means said first signal being representative of an analog input signal;

encoding means coupled to said adding means for encoding said third signal to produce a fourth signal;

transmitting means coupled to said adding means and encoding means for transmitting said second and fourth signals;

receiving means for separably receiving said second and fourth signals;

decoding means coupled to said receiving means for decoding said fourth signal to reproduce said third signal;

subtracting means coupled to said receiving means and said decoding means for subtracting said key from said second signal and adding said third signal resulting in a signal being representative of said first signal.

2. The apparatus defined in claim 1 including:

an A/D converting means for converting said analog input signal to a digital signal, said digital signal being said first signal;

said A/D converting means being connected to said adding means, said adding means including a digital adder;

said encoding means further being coupled to said key and;

said subtracting means including a digital adder.

3. The apparatus defined in claim 2 wherein:

said encoding means includes an exclusive OR gate for encoding said third signal with said key.

4. The apparatus defined in claim 1 including:

a first A/D converting means coupled to said adding means for converting said binary key to an analog key to be added to said first signal;

said encoding means further being coupled to a portion of said binary key;

a second A/D converting means coupled to said subtracting means for converting said binary key to an analog key to be subtracted from said second signal.

5. The apparatus defined in claim 4 wherein:

said encoding means includes an exclusive OR gate or encoding said third signal with said portion of said binary key.

6. The apparatus defined in claim 1 wherein:

said transmitting means and said receiving means comprise time division multiplex transmitter and receiver for time division multiplex transmitting and receiving said second and fourth signal.

7. The apparatus defined in claim 1 wherein:

said transmitting means having two separate channels a first channel which transmits said second signal and a second channel which transmits said fourth signal;

said receiving means similarly having two separate channels for receiving said second and fourth signals.

8. A method of encoding and decoding analog signals comprising:

adding a pseudo random binary key to a first signal to produce a second signal said first signal being an analog input signal converted to binary form;

producing a third signal representative of whether a modulo shift in a shift register was indicated after said adding step;

encoding said third signal to produce a fourth signal;

separably transmitting said second and fourth signals; receiving said second and fourth signals;

decoding said fourth signal to reproduce said third signal;

subtracting said key from said second signal and;

adding said third signal to said second signal to reproduce a signal representative of said first signal.

9. The method defined in claim 8 wherein:

said step of encoding includes exclusive ORing said third signal with said key.

Claims

1. Apparatus for encoding and decoding analog signals comprising: adding means for adding a pseudo random binary key to a first signal to produce a second signal and for producing a third signal indicating whether module addition has occured; in said adding means said first signal being representative of an analog input signal; encoding means coupled to said adding means for encoding said third signal to produce a fourth signal; transmitting means coupled to said adding means and encoding means for transmitting said second and fourth signals; receiving means for separably receiving said second and fourth signals; decoding means coupled to said receiving means for decoding said fourth signal to reproduce said third signal; subtracting means coupled to said receiving means and said decoding means for subtracting said key from said second signal and adding said third signal resulting in a signal being representative of said first signal.

2. The apparatus defined in claim 1 including: an A/D converting means for converting said analog input signal to a digital signal, said digital signal being said first signal; said A/D converting means being connected to said adding means, said adding means including a digital adder; said encoding means further being coupled to said key and; said subtracting means including a digital adder.

3. The apparatus defined in claim 2 wherein: said encoding means includes an exclusive OR gate for encoding said third signal with said key.

4. The apparatus defined in claim 1 including: a first A/D converting means coupled to said adding means for converting said binary key to an analog key to be added to said first signal; said encoding means further being coupled to a portion of said binary key; a second A/D converting means coupled to said subtracting means for converting said binary key to an analog key to be subtracted from said second signal.

5. The apparatus defined in claim 4 wherein: said encoding means includes an exclusive OR gate or encoding said third signal with said portion of said binary key.

6. The apparatus defined in claim 1 wherein: said transmitting means and said receiving means comprise time division multiplex transmitter and receiver for time division multiplex transmitting and receiving said second and fourth signal.

7. The apparatus defined in claim 1 wherein: said transmitting means having two separate channels a first channel which transmits said second signal and a second channel which transmits said fourth signal; said receiving means similarly having two separate channels for receiving said second and fourth signals.

8. A method of encoding and decoding analog signals comprisIng: adding a pseudo random binary key to a first signal to produce a second signal said first signal being an analog input signal converted to binary form; producing a third signal representative of whether a modulo shift in a shift register was indicated after said adding step; encoding said third signal to produce a fourth signal; separably transmitting said second and fourth signals; receiving said second and fourth signals; decoding said fourth signal to reproduce said third signal; subtracting said key from said second signal and; adding said third signal to said second signal to reproduce a signal representative of said first signal.

9. The method defined in claim 8 wherein: said step of encoding includes exclusive ORing said third signal with said key.