US3735383A - Display apparatus utilizing cathode ray tubes - Google Patents

Display apparatus utilizing cathode ray tubes Download PDF

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US3735383A
US3735383A US00109129A US3735383DA US3735383A US 3735383 A US3735383 A US 3735383A US 00109129 A US00109129 A US 00109129A US 3735383D A US3735383D A US 3735383DA US 3735383 A US3735383 A US 3735383A
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electrode
register
patterns
memories
displayed
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K Naka
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Noritake Itron Corp
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Ise Electronics Corp
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/20Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using multi-beam tubes

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  • an address register for storing the 8 "340/324 positions on the screen at which selected patterns are to be displayed a memory for Storing the information [58] Fleld of Search ..340/324 lg,l?;2;l2A;)6 regarding the patterns to be displayed, means respon sive to the outputs from the address register and the memory for selectively driving the plurality of memo- [56] References Cited ties and means for supplying deflection current to the UNITED STATES PATENTS deflection coil of the cathode ray tube in synchronism with the outputs from the plurality of memories.
  • SHEET 0F 7 X1 X2 X [4 Isle X1 INVENTOR KATUSHI NAKA BY WFHR @OA, Wag swam A roriNEYs PATENTED 3. 7 35 383 sum 5 ur 7 )hlhlalalslslh INVENTOR KATUSHI NAKA BY W WORNE PATENTED ZZ HH sum 6 [1F 7 INVENTOR YKATUSHI NAKA BY W, k g
  • This invention relates to apparatus for displaying information regarding, letters, digits, symbols and the like which are stored being stored in a memory of an electronic computer, for example, and more particularly display apparatus utilizing a cathode ray tube employing a dot matrix.
  • a special cathode ray tube called the beam forming type wherein a letter electrode stamped with letters, digits or symbols is disposed in front of an electron gun and a potential is applied to a deflection electrode disposed in front of the letter electrode on the side of the cathode electrode to select a desired letter, digit or symbol to cause one portion of the letter electrode to pass electrons and remaining portions of the letter electrode to block the electrons. Electrons passed through the letter electrode display the desired letter, digit or symbol on the desired portion of the fluorescent screen of the cathode ray tube.
  • dispersion of the electron beam causes poor resolution of lines of the pattern.
  • a second prior apparatus is called the dot system according to which a single electron beam is driven to successively scan a letter'electrode longitudinally or transversely and when the beam reaches the desired point of the letter electrode the intensity of the beam is increased to cause the corresponding point on the screen to luminesce. Portions not wanted to luminesce are applied with a brightness eliminating signal.
  • This elimination signal is used to select the memory of the letter and the like comprising a group of circuits for displaying the selected letter and the like on a screen by dots.
  • this second type of the apparatus utilizing scanning lines, in order to display a large number of letters and the like, it is necessary to greatly reduce the scanning period thus complicating the apparatus.
  • the periods of the signals applied to various components are short, it is impossible to display stably the letters and the like.
  • a third apparatus is termed the segment synthesis system.
  • This system is similar to the dot system described above except that portions between dots are not eliminated but are displayed as a segment of a continuous bright line to display letters and the like.
  • vertical, horizontal and inclined segments are stored in a memory and the codes of the stored segments separated from a definite reference point are read out and the read out codes are applied to a deflection coil through a digital-analogue converter to display letters and the like.
  • the operation of this apparatus is unstable because the periods of the vertical and horizontal deflection signals are short. F urther, stability of the apparatus is degraded due to aging because the read out codes are converted into analogue quantities for displaying letters and the like.
  • a fourth apparatus utilizes the Lissajous pattern wherein waveforms of continuous functions are applied to both vertical and horizontal deflection coils to display letters and the like with Lissajous patterns. More particularly, the phase relation between the time function of the function wave and the higher harmonic components obtained by subjecting the time function to the Fourier transformation is calculated so as to cause only portions necessary to display letters and the like to luminesce.
  • letters displayed by this apparatus are well defined and clear it is necessary to provide a function wave generator for each letter so that the apparatus becomes complicated. Again the operation of the apparatus is unstable because letters and the like are also displayed by analogue quantities.
  • a fifth apparatus utilizes a special cathode ray tube provided with seven electron beams.
  • the seven dots displayed on the screen by seven electron beams are comprised by bright dots selected by a matrix electrode disposed in the cathode ray tube and eliminated dots. Since these seven dots are sequentially deflected by deflection coils, the patterns of letters and the like are displayed by the dots under the. control of a signal supplied from an external letter memory. With this apparatus, however, a letter can not be formed unless the beams are deflected.
  • Another object of this invention is to provide a novel display cathode ray tube wherein selected ones of a plurality of letters, digits, symbols and like patterns can be displayed on the display screen of the cathode ray tube without the necessity of deflecting the electron beam to form the letter, digit, symbol or pattern.
  • a further object of this invention is to provide a new and improved display apparatus which can display clearly and stably different types of letters.
  • Still another object of this invention is to provide a display apparatus capable of displaying letters of different types with a simplified circuit construction without the necessity of utilizing any digital-analogue converter.
  • Yet another object of this invention is to provide a novel display apparatus capable of displaying a large number of letters, digits and symbols of different type.
  • More specific object of this invention is to provide an improved display apparatus of compact design suitable for use in desk type electronic computers.
  • a display apparatus comprising a cathode ray tube including a cathode electrode, a matrix electrode, a display screen, and a deflection coil disposed between the matrix electrode and the display screen a plurality of discrete memories connected to the matrix electrode, the memories being provided for different groups of patterns of the letters, digits and symbols tobe displayed on the screen address memory means for storing the positions on the screen at which the selected patterns of the letters, digits and symbols are to be displayed information memory means for storing the information regarding the patterns to be displayed means responsive to the outputs from the address memory means and the information memory means for selectively driving the plurality of memories for the groups of patterns, and means for supplying deflection signals to the deflection coil in synchronism with the outputs from the plurality of memories.
  • FIG. 1 shows a block diagram showing the basic construction of the novel display apparatus utilizing the cathode ray tube embodying this invention
  • FIGS. 20 and 2b are waveforms to explain the operation of respective blocks shown in FIG. 1
  • FIGS. 3, 4 and 5 are connection diagrams showing examples of memories of symbols of alphabets, digits, and katakanas (Japanese alphabets shown in FIG. 1
  • FIG. 6 shows one example of an electrical connection of a gate circuit shown in FIG. 1;
  • FIGS. 70, 7b and 70 show the patterns displayed on the screen of the cathode ray tube, and the correspondence between the positions of the patterns, and the addresses of the sub-memory
  • FIG. 8 shows a truth table showing the state of address symbols memorized in a register
  • FIG. 9 shows a construction of a dot matrix electrode utilized in the cathode ray tube shown in FIG. 1 and
  • FIG. 10 is an enlarged view of one example of the pattern displayed on the display screen of the cathode ray tube.
  • FIG. 1 showing a general block diagram of a display apparatus utilizing the novel cathode ray tube
  • the output from a memory 1 is coupled to a sub-memory, whose output is coupled to a register 3.
  • the major portion of the outputs from register 3 is coupled to a decoder 4 which in turn is connected to a gate circuit 5 via conductors D D D,,.
  • the remaining portion of the outputs from register 3 is directly coupled to gate circuit 5 through conductors g g, and g;,.
  • a portion of the output from gate circuit 5 is coupled to an alphabet symbol memory 6 over conductors A A A,, another portion to a digit symbol memory 7 over conductors N N N, whereas the remaining portion to a katakana symbol memory 8 over conductors K K K,,.
  • the outputs from these memories 6, 7 and 8 are supplied to a dot matrix electrode portion 19b of a cathode ray tube 18.
  • a clock pulse generator 13 is connected to a counter 12.
  • a portion of the output from counter 12 is coupled to alphabet symbol memory 6, digit symbol memory 7 and Katakana symbol memory 8, another poru'on of the output from counter 12 is supplied to an address register 10 whereas the remaining portion is fed to a X-axis stepped wave synthesizer 15.
  • the output from the address counter 10 is coupled to a read out control 11, the output thereof being coupled to the sub-memory 2.
  • a portion of the output from the X-axis stepped wave synthesizer 15 is supplied to the deflection coil 17 of the cathode ray tube 18 and another portion of the output from X-axis stepped wave synthesizer is coupled to a Y-axis stepped wave synthesizer 16 also comprising a deflection circuit of the cathode ray tube. Hence the output from the synthesizer 16 is also connected to the deflection coil 17.
  • a start-stop control 9 To the inputs of a start-stop control 9 are supplied a start signal and a stop signal generated by an external source such as an electronic computer, not shown, and the outputs from the start-stop control are supplied to X-axis stepped wave synthesizer l5, Y-axis stepped wave synthesizer, address register 10 and counter 12, respectively.
  • FIGS. 2a and 2b show output waveforms helpful to explain the operation of various components shown in FIG. 1, wherein the abscissas represent the time and the ordinates the voltage or current, t t t show various times at which more than one waveform varies.
  • a reference numeral 22 represents the waveform of the output voltage of the clock pulse gen erator 13
  • reference numerals 23 to 28 show output waveforms of counter 12
  • 29 the output from the X axis stepped wave synthesizer 15, that is the waveform of the current flowing through deflection coil 17.
  • waveform 30 shows on a different time basis the same waveform as that shown by 29 in FIG.
  • waveforms 30 and 31 are not limited to the illustrated examples and that the number of steps of these waves varies dependent upon the number of arrays of the letter or digit symbols to be displayed on the screen of the cathode ray tube 18.
  • T T on the time axis t of FIG. 2b represents the times at which one or both of waveforms 30 and 31 vary.
  • FIGS. 3, 4 and 5 show typical connection diagrams of the alphabet symbol memory 6, the digit symbol memory 7 and the katakana symbol memory 8, respectively shown in FIG. 1.
  • y, through y respectively corresponding to waveforms 24 through 28 shown in FIG. 24, represent the same conductors.
  • conductors x through x shown in FIGS. 3 to 5 represent the same conductors and are connected to the dot matrix electrode 19b of cathode ray tube 18.
  • Conductors A A3 A correspond to conductors A A A A respectively shown in FIGS. 1 and 6.
  • conductors N N N N, shown in FIG. 4 correspond, respectively to conductors N N N N N,
  • conductors K K K K shown in FIG. 5 correspond to conductors K K K K, respectively, shown in FIGS. 1 and 6.
  • resisters 32, 33, 34, 35 and 36 are connected to corresponding one of conductors y y y y, and y while the other ends of these resisters are connected to corresponding one of conductors 47, 48, 49, 50 and 51.
  • conductor 47 is connected to the positive poles of diodes 73, 74, 75, 76 and 77, the negative poles thereof being connected to conductors 68, 69, 70, 71 and 72, respectively.
  • conductor 48 is connected to the positive poles of diodes 79 and 89, the negative poles thereof being connected to conductors 67 and 70, respectively.
  • Conductor 49 is connected to the positive poles of diodes 78 and 87, the negative poles thereof being connected to conductors 66 and 70, respectively.
  • conductor 50 is connected to conductors 67 and 70, respectively through diodes 80 and 86 and conductor 51 is connected to conductors 68, 69, 70, 71 and 72, respectively through diodes 81, 82, 83, 84 and 85.
  • the other ends of these conductors 66 through 72 are connected to conductors 1:, through at, respectively through diodes 59 through 65.
  • conductors 66 through 72 are connected to the positive poles of diodes through 58, respectively, the negative poles of these diodes being commonly connected to the output conductor A, of the gate circuit 5.
  • Such a combination of diodes means that an information of a letter A is stored. Elements associated with another conductors A to A are also similarly connected. Thus, the combination of diodes associated with conductor A stores the information of a letter B and that associated with conductor A stores the information of letter C.
  • combinations of diodes storing informations of digits 1, 2, 3 are associated with output conductors N N N respectively, of gate circuit 5.
  • combinations of diodes storing informations of katalcana symbols a, e, u are associated with output conductors K K K,,, respectively of gate circuit 5.
  • FIG. 6 shows a typical connection diagram of the gate circuit 5 shown in FIG. 1, as shown the output conductors A A A, A, are connected to the positive poles of diodes 89, 90, 91, 92, 93, 94, and 95, respectively.
  • the number of diodes is equal to the number of conductors A A A A,,, for the sake of simplicity, the number of the diodes is shown reduced.
  • the negative poles of these diodes 89, 90, 91, 92, 93, 94 and 95 are commonly connected to a conductor 131, hereinafter called g, conductor.
  • Conductors A A A A are also connected to positive poles of diodes 96 through 102, respectively, the nega tive poles of these conductors being connected to conductors 135 through 141, respectively, hereinafter called G line, G line G, line, respectively.
  • N N N N are similarly connected.
  • these conductors are connected to a conductor 132 (hereinafter called g line) through diodes 103 through 109.
  • conductors N through N are connected to conductors G through G, respectively, through diodes 110 to 116 inclusive.
  • Output conductors K K K K, of gate circuit 5 are similarly connected. More particularly, these conductors are connected to a conductor (herein termed g line respectively through diodes 117 through 123. These conductors K, through K, are also connected to conductors G through G respectively through diodes 124 to 1341) inclusive.
  • FIGS. 7a, 7b and 70 show patterns and the positions thereof displayed on the screen of cathode ray tube 18 as well as the correspondence between these positions and the addresses in the sub-memory 2.
  • FIG.7a shows the manner of displaying the patterns of letters, digits and the like on the screen of the cathode ray tube
  • FIG. 7b shows the positions of the patterns of the letters, digits and the like to be displayed on the screen of the cathode ray tube 18
  • FIG. 7c shows the correspondence between the address symbol numbers B B,,,,, of sub-memory 2 and the symbol numbers 8,,
  • FIG. 8 shows a truth table showing the state of the address symbol numbers B through B when they are stored in the register 3.
  • D D D D shown logical values of the contents of register 3 when they appear on respective output conductors D after being decoded by decoder 4, whereas g,, g 2 and g show the logical values appearing on respective output conductors g g and g of register 3 shown in FIGS. 1 and 6.
  • FIG. 9 shows a typical construction of the dot matrix electrode consisting of portions 19a and 19b of the cathode ray tube 18, which are situated in front of the electron gun of the cathode ray tube.
  • y,, y' y y and y (collectively designated 19a) and x',, x' x;,, x'.,, x',, x, and x", (collectively designated 19b) electrode plates respectively connected to conductors y, through y, and conductors at, through x described above.
  • These electrode plates comprise a matrix of 5 X 7.
  • each of the electrodes y, through is provided with equally spaced apart five openings and each of the electrodes x, through x is provided with equally spaced apart seven openings.
  • the openings of the electrode plates y, through y, and the openings of the electrode plates .t' through x, are superposed at the crossings of these electrode plates.
  • a shield plate 142 is interposed between these groups of electrode plates or in front of electrode plates x, through x' .
  • FIG. 10 shows one example of the pattern displayed on the screen of the cathode ray tube. In this case, a letter B is displayed. I
  • the operation of the novel display device is generally as follows Upon application of a start signal pulse to start-stop control 9, a start signal is supplied to cause to respective circuit blocks.
  • the start-stop control 9 functions to coincide with each other the phases of the deflection signal applied to coil 17, the information read signal for obtaining information from memories and the scanning pulses on conductors y, y, for the matrix electrode and the signal provided by the start-stop control operates address register 11) and counter 12 which have been held in their set state to transfer the information to be displayed from memory 1.
  • the content of the memory is determined so as to coincide the positions of the position numbers 8,, S of the screen of the cathode ray tube shown in FIG.
  • Three codes of the contents written in the register 3 are utilized as the gate signals for selecting the alphabet symbol memory 6, the digit symbol memory 7 and the katakana symbol memory 8, respectively and the remaining contents of the register are codes for selecting the patterns of the letters, digits and symbols, respectively.
  • These codes are supplied to gate circuit 5 through decoder 4. Consequently, one of the letter digit or katakana symbols having patterns in the memories 8, 7 and 6 is selected and the selected pattern is applied to the matrix electrode portion 19b according to the memory and in synchronism with a pulse signal from counter 12 for scanning the dot matrix electrode portion 19a in the cathode ray tube 18 whereby the selected pattern is synthesized with the pulse signal to form the desired pattern.
  • synthesizers 15 and 16 comprising the deflection circuit pass deflection currents through the deflection coil of the cathode ray tube in synchronism with the pulse utilized to form the pattern.
  • the content of the register 3 reads out a code corresponding to the pattern of the letter and the like to be displayed next time from the sub-memory 2 and the code is applied to the matrix electrode of the cathode ray tube to display the newly selected pattern on the screen.
  • the deflection currents supplied by the stepped wave synthesizers 15 and 16 have been varied stepwisely, the pattern of the next letter can be displayed at the desired position.
  • Memory 1, sub-memory 2, address register 10 and read out control 1 l are not limited to the particular types illustrated.
  • memory 1 may be eliminated, in which case the sub-memory 2 is used as the memory of the electronic computer. It is only essential to arrange the components so that the contents of the sub-memory 2 are successively read out into register 3 at a high speed in accordance with the arrangement of the letter on the screen by a single output pulse from counter 12. This is possible by conventional computer technique.
  • codes corresponding to the symbols of the letters, digits or the like to be displayed are sequentially read out and stored in the register 3.
  • the start-stop control 9 comprises a single RS flipflop to store start and stop signals. Assuming now that upon receival of a stop signal, the address register 10, counter 12, X-axis stepped wave synthesizer 15 and Y- axis stepped wave synthesizer 16 are set. Then, upon receival of a start signal at the start-stop control 9, address register 10, counter 12 and X and Y axis stepped wave synthesizers 15 and 16 will start under predetermined conditions, which should satisfy the following. Address register 10 should indicate an address number B shown in FIG.
  • counter 12 should correspond to waveforms 23, 24, 25, 26, 27 and 28 at a time to shown in FIG. 2a.
  • the wave forms of the currents passed through the deflection coil 17 of the cathode ray tube 18 by the X-axis stepped wave synthesizer 15 and the Y-axis stepped wave synthesizer 16 should correspond to the waveforms 23, 24, 25, 26, 27, and 28 of the counter 12 at a time to and current waveforms 30 and 31 at a time T in FIG. 212.
  • FIG. 8 shows the codes read out from register 3 which are applied directly to gate circuit 5 and the codes read out from register 3 which are applied to gate circuit 5 through decoder 4.
  • a code 1 is represented by a positive voltage and a code 0 by a zero voltage
  • a positive voltage will be applied on conductor g, with zero voltages upon conductors g and g shown in FIG. 6.
  • the positive potential impressed upon conductor 81 is higher than the voltages on conductors A A A diodes 89 through connected to conductor g, are biased in the reverse direction so that they pass no current.
  • diodes 103 through 109 connected to conductor g are biased in the foreward direction to pass currents.
  • Codes on conductors D D D D are supplied to conductors 6,, G G a G, respectively. Again assuming positive voltage logical values for the codes on conductors D through D,, then a positive voltage will be impressed only upon conductor G, the potential impressed across diode 96 of the selected alphabet symbol memory 6 is a negative bias because the voltages on conductors A and G are equal or the voltage on conductor G is higher than that impressed upon conductor A whereby diode 96 does not pass current.
  • 3 to 5 are the same conductors which are connected to the dot matrix electrode portion 19b of the cathode ray tube 18. Since the selected conductor A is being impressed with a positive potential, diodes 52 through 58 are biased in the reverse direction and hence are non-conductive. Positive pulses 24 through 28 shown in FIG. 2a correspond to voltages appearing on conductors y, through y respectively, and during the interval between t, to a positive potential is applied upon conductor y, and conductors y to y, inclusive are at a zero voltage. This positive voltage appears on conductors x through x through diodes 81 through $5 and thence through diodes 61 through 65.
  • conductors y through y are at the zero voltage
  • conductors x and x are also at the zero voltage.
  • the positive potential is thereafter applied sequentially upon conductors y through y thus forming a series of codes on conductors x through x-,.
  • a series of codes prepared by the diode matrix connected to conductor A and the voltage impressed upon conductors y, to y,, inclusive are synthesized by the dot matrixes 19a electrode portions and 19b of the cathode ray tube 18 to display an alphabet A.
  • di odes 59 through 65 function to prevent interference with diode memory blocks of other letters and the like.
  • a signal is applied to the Y-axis stepped wave synthesizer 16 from a counter included in the X-axis stepped wave synthesizer 15 to vary the condition of the stepped wave generated by the synthesizer 16.
  • the counter in the X-axis stepped wave synthesizer 15 is a 11 step counter for the letters, digits and symbols to be formed at the sides of positions S S shown in FIG. 7(b).
  • a pulse signal is applied to the Y-axis stepped wave synthesizer I6 to change its state as shown in FIG. 2b.
  • FIG. 2b shows the current passed through the deflection coil I7 of the cathode ray tube 18 by the X-axis stepped wave synthesizer 15, which is similar to the waveform 29 shown in FIG. 2a.
  • the waveform 31 shown in FIG. 2 b shows a signal generated by Y-axis stepped wave synthesizer 16 under the control of an output from the counter included in the X-axis stepped wave synthesizer 15.
  • Waveform 30 shows the horizontal deflection current through the deflection coil of the cathode ray tube 1% and as shown by FIG.
  • Patterns of the letters and the like to be displayed are dependent upon the contents of the register 3 which are applied directly upon gate circuit over conductors g: and g and the contents of the register 23 which are applied to gate circuit 5 through decoder 4. Where the number of letters and the like required to be stored in these components increases, the number of conductors D through D,, also increases thus complicating the circuit arrangement of decorder 4.
  • the alphabet symbol memory 6, digit symbol memory 7 and katakana symbol memory 8 are comprised by a number of sub-divided block circuits and the number of codes corresponding to the codes on conductors g g and 83 for enabling and disenabling the gate circuit is increased to the number of sub-divided blocks of the letter, digit and symbol memories, which may be constructed by a diode circuit similar to that shown in FIG. 6. With this construction, it is possible to decrease the number of terminals 6,, G G thus simplifying the circuit construction of the decoder 4.
  • a decoder may be connected between submemory 2 and register 3.
  • memory 1 may be omitted, in which case sub-memory 2 is utilized as the memory of the computer thus providing a real time display apparatus for the computer.
  • the invention provides an improved display apparatus employing a novel cathode ray tube according to which letters, digits, symbols and the like can be displayed on the screen deflection of the electron beam is necessary only for suitably separating letters and the like displayed on the screen.
  • Letters and the like are formed by the selective operation of the matrix electrode acting portions 19a, 19b as a type of a matrix switch. For this reason the display apparatus operates very stably so that the letters and the like displayed on the screen of the cathode ray tube are more stable than in the conventional display apparatus.
  • the apparatus for generating patterns of the letters and the like, gate circuit 5, alphabet symbol memory 6, digit symbol memory 7, katakana symbol memory 8, counter 12 are all comprised by flip-flop circuits or logical circuits including combinations of diodes whereby the patterns of the letters and the like are displayed on the screen without the necessity of any digital-analogue conversion. For this reason, stable display can be made with inexpensive and simple apparatus not utilizing special and complicated components.
  • clock pulses generated by the clock pulse generator 13 are distributed among various component parts through counter 12, variations in the frequency of the clock pulse do not affect the quality of the letters and the like displayed on the screen of the cathode ray tube. Further, as the letters and the like are displayed by dots, it is possible to display a large number of letters and the like by merely increasing the contents of the memory.
  • Display apparatus comprising a cathode ray tube including a cathode electrode, a display screen, a matrix electrode disposed between said cathode electrode and display screen, said matrix electrode comprising a plurality of y electrode plates and a plurality of x electrode plates, said y and x electrode plates being arranged to form a matrix and having holes at their junctions adapted to pass electrons emitted from said cathode electrode, and a deflection coil disposed between said matrix electrode and said display screen; a plurality of discrete memories connected to control said plurality of x electrode plates, each of said memories being provided for a different group of patterns of the letters, digits and symbols to be displayed on said screen; address memory means for storing the positions on said screen at which the selected patterns of said letters, digits and symbols are to be displayed; information memory means for storing the information regarding the patterns to be displayed; means responsive to the outputs from said address memory means and said information memory means for selectively driving said plurality of memories to control said plurality of memories to
  • said information memory means is connected to said address memory means such that the contents of said information memory means are read out under the control of said address memory means
  • said driving means includes a register connected to said information memory means for receiving said read out contents, a decoder and a gate circuit connected between the output of said register and said plurality of memories and through which said read out contents are supplied to said plurality of memories.
  • each one of said plurality of memories for said groups of patterns comprises a plurality of parallel connected diode matrixes, each for one pattern.
  • said means for supplying said deflection signals comprised a X-axis stepped wave synthesizer and a Y- axis stepped wave synthesizer.
  • the display apparatus which further comprises a start-stop control for controlling the operations of said X-axis stepped wave synthesizer and said Y-axis stepped wave synthesizer and for controlling the operation of said address memory means.
  • the display apparatus which further comprises a clock pulse generator and a counter responsive to the output from said clock pulse generator for synchronously controlling the operations of said address memory means, said plurality of memories for said groups of patterns, said X-axis stepped wave synthesizer and said Y-axis stepped wave synthesrzer.
  • said information memory means comprises a main memory and a submemory.
  • said cathode ray tube further comprises a grid electrode and an elimination synchronizer connected to said grid electrode and adapted to apply an elimination signal of a very short interval to said grid electrode while said deflection signals change causing said deflection coil to position the next letter, digit or symbol to be displayed on said screen.
  • a display apparatus for displaying letters, digits, symbols and like patterns comprising a cathode ray tube including a cathode electrode, a control grid, a display screen, a dot matrix electrode disposed be tween said cathode electrode and display screen, said matrix electrode comprising a plurality of y electrode plates and a plurality of x electrode plates, said y and x electrode plates being arranged to form a matrix and having holes at their junctions adapted to pass electrons emitted from said cathode electrode, and a deflection coil disposed between said matrix electrode and said display screen; a main memory for storing information regarding the patterns to be displayed on said display screen; a register; an address register for storing the positions on said screen at which selected patterns are to be displayed; a sub-memory, responsive to said address register, connected between the output of said main memory and the input of said register for reading out the information from said main memory and storing the read out information in said register under the control of said address register; a

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Cited By (14)

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US3928845A (en) * 1974-12-11 1975-12-23 Rca Corp Character generator system selectively providing different dot-matrix size symbols
US3996584A (en) * 1973-04-16 1976-12-07 Burroughs Corporation Data handling system having a plurality of interrelated character generators
US4041482A (en) * 1975-03-25 1977-08-09 U.S. Philips Corporation Character generator for the reproduction of characters
US4338599A (en) * 1978-07-21 1982-07-06 Tandy Corporation Apparatus for alpha-numeric/graphic display
US4344090A (en) * 1978-09-25 1982-08-10 Indesit Industria Elettrodomestici Italiana S.P.A. Television set with picture-storage means
US4415890A (en) * 1979-05-31 1983-11-15 Canon Kabushiki Kaisha Character generator capable of storing character patterns at different addresses
US4428065A (en) 1979-06-28 1984-01-24 Xerox Corporation Data processing system with multiple display apparatus
US4470042A (en) * 1981-03-06 1984-09-04 Allen-Bradley Company System for displaying graphic and alphanumeric data
US4546451A (en) * 1982-02-12 1985-10-08 Metheus Corporation Raster graphics display refresh memory architecture offering rapid access speed
US4566038A (en) * 1981-10-26 1986-01-21 Excellon Industries Scan line generator
US4603330A (en) * 1982-10-01 1986-07-29 High Technology Solutions, Inc. Font display and text editing system with character overlay feature
US4631597A (en) * 1977-12-22 1986-12-23 Ricoh Company, Ltd. Video data transmission apparatus
US4735515A (en) * 1980-10-31 1988-04-05 Canon Kabushiki Kaisha Serial printing apparatus having two character generators, one which generates characters common to a plurality of countries
US6577318B1 (en) * 1998-12-22 2003-06-10 Nec Electronics Corporation Integrated circuit device and display device with the same

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US3964591A (en) * 1975-06-10 1976-06-22 International Business Machines Corporation Font selection system
JPS5713481A (en) * 1980-06-27 1982-01-23 Konishiroku Photo Ind Character generating system
US20220064774A1 (en) * 2019-02-20 2022-03-03 Posco Coated & Color Steel Co., Ltd. Plated steel sheet having excellent fusion resistance, and manufacturing method therefor

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Cited By (14)

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US3996584A (en) * 1973-04-16 1976-12-07 Burroughs Corporation Data handling system having a plurality of interrelated character generators
US3928845A (en) * 1974-12-11 1975-12-23 Rca Corp Character generator system selectively providing different dot-matrix size symbols
US4041482A (en) * 1975-03-25 1977-08-09 U.S. Philips Corporation Character generator for the reproduction of characters
US4631597A (en) * 1977-12-22 1986-12-23 Ricoh Company, Ltd. Video data transmission apparatus
US4338599A (en) * 1978-07-21 1982-07-06 Tandy Corporation Apparatus for alpha-numeric/graphic display
US4344090A (en) * 1978-09-25 1982-08-10 Indesit Industria Elettrodomestici Italiana S.P.A. Television set with picture-storage means
US4415890A (en) * 1979-05-31 1983-11-15 Canon Kabushiki Kaisha Character generator capable of storing character patterns at different addresses
US4428065A (en) 1979-06-28 1984-01-24 Xerox Corporation Data processing system with multiple display apparatus
US4735515A (en) * 1980-10-31 1988-04-05 Canon Kabushiki Kaisha Serial printing apparatus having two character generators, one which generates characters common to a plurality of countries
US4470042A (en) * 1981-03-06 1984-09-04 Allen-Bradley Company System for displaying graphic and alphanumeric data
US4566038A (en) * 1981-10-26 1986-01-21 Excellon Industries Scan line generator
US4546451A (en) * 1982-02-12 1985-10-08 Metheus Corporation Raster graphics display refresh memory architecture offering rapid access speed
US4603330A (en) * 1982-10-01 1986-07-29 High Technology Solutions, Inc. Font display and text editing system with character overlay feature
US6577318B1 (en) * 1998-12-22 2003-06-10 Nec Electronics Corporation Integrated circuit device and display device with the same

Also Published As

Publication number Publication date
SE372835B (enrdf_load_stackoverflow) 1975-01-13
GB1316696A (en) 1973-05-09
FR2077095A5 (enrdf_load_stackoverflow) 1971-10-15
CA954963A (en) 1974-09-17
DE2104266A1 (de) 1972-01-27
JPS4947565B1 (enrdf_load_stackoverflow) 1974-12-17

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