US3724201A

US3724201A - Nuclear-paced solid state wristwatch

Info

Publication number: US3724201A
Application number: US00110167A
Authority: US
Inventors: J Bergey
Original assignee: HMW Industries Inc
Current assignee: HMW Industries Inc
Priority date: 1971-01-27
Filing date: 1971-01-27
Publication date: 1973-04-03
Anticipated expiration: 1990-04-03

Abstract

Disclosed is a solid state wristwatch incorporating a nuclear timing source. A radioisotope such as Radium 226 decays, producing alpha particles that are detected and converted into electrical pulses of constant frequency. The electrical signals are divided in a CMOS binary chain and used to drive a digital time display of light emitting diodes. The watch is powered by a conventional 3 volt battery.

Description

United States Patent 1 u 11 3,724,201 Bergey Apr. 3, 1973 I541 NUCLEAR-PACED SOLID STATE 3,582,656 6/l97l Kochlcr ..250/a3.3 WRISTWATCH 3,505,804 4/1970 Hofstein ..58/23 [75] Inventor: John Hersey Lancaster Primary Examiner-Richard B. Wilkinson [73] Assignee: HMW Industries, lnc.,- Lancaster, Assistant Exaniiner-Edith C. Simmons Ja'ckmon Pa. Attorney-Le Blanc & Shur [22] Filed: Jan. 27, 1971 ABSTRACT [211 App! 110l67 Disclosed is a solid state wristwatch incorporating a nuclear timing source. A radioisotope such as Radium Cl 58/23 53/23 A 226 decays, producing alpha particles that are dev /333 tected and converted into electrical pulses of constant [51] Int. Cl. ..G04b 19/30, G04c 3/00 frequency. The electrical signals are divided in a Field of Search 23 23 CMOS binary chain and used to drive a digital time 106 display of light emitting diodes. The watch is powered by a conventional 3 volt battery. 5 6] References Cited 14 Claims, 12 Drawing Figures UNITED STATES PATENTS R26,958 9/1970 Lazrus et al. ..'.....58/23 i PRESET COUNT SET/RESET I 64 20 f .38 42 AMPLIFIER- FREQUENCY DISCRIMINATORT DIVIDER mm 58 E 30 4o ,sz I

46 BATTERY PATENTEDAPRS 197s SHEET 1 BF 5 Y R m N W. M N H m g lg M M m M W Q M T 01D Aw U2 fim mm m G n 5 VI 3 Tm T M N B G m l TmcULm F .JW D m m w R M m N m m m WW AD ATTORNEYS LPATENTEDAPR 3 I975 SHEET 4 UF 5 592: MINUTE HOURS DISPLAY DISPLAY DISPLAY 248 250 252 DEDDDE'R DECODER DEDDDER' DRIVER DRIVER DRIVER 226 228 230 I f f 'I-IO +6 H2 280 A08 264 266 LIGHT SENSORS LIGHT 270 DISPLAY I CONTROL 3 CONTROL cjmcun DRIVERS gg 298 268 -3l0 302 Z88 DEMAND BUTTON I8 READ SWITCH 284 292 ..J DISPLAY 4 O e TIMER ST HO 1 {3M O 296 304 ZHZ (DURING SETTING) m /294 t SET-HOLD HOURS SET 300 CIRCUIT CIRCUIT 326 Q soe sza HG. 7B

8 \LZIG PATENTEDAPRB ma 3.724.201

SHEET 5 0F 5 NUCLEAR-PACED SOLID STATE WRISTWATCH This invention relates to a solid state timepiece and more particularly to an electric watch which employs no moving parts. In the present invention, a frequency standard in the form of a nuclear timing source acts through solid state electronic circuit dividers and drivers to power in timed sequence the light-emitting diodes of an electro-optic display. Low power consumption and small size and weight are achieved through the use of complementary MOS circuits. Through the use of a nuclear timing source, the watch has improved shock insensitivity, lower cost, lower power consumption, is less affected by thermal variances and is smaller in size. In addition, the nuclear timing source has the feature that the overall accuracy of the watch increases with use. That is, the percentage timing error of the combined system decreases with increased operating time.

Battery-powered Wristwatches and other small portable timekeeping devices of various types are well known and are commercially available. The first commercially successful battery-powered wristwatch is of the type shown and described in assignees U.S. Pat. No. Re 26,187, reissued Apr. 4, 1967, to John A. Van Horn et al for Electric Watch. Electric watches of this type employ a balance wheel and a hairspring driven by the interaction of a current-carrying coil and a magnetic field produced by small permanent magnets.

In recent years, considerable effort has been directed toward the development of a wristwatch which does not employ an electromechanical oscillator as the master time reference. In many instances, these constructions have utilized a crystal-controlled high frequency oscillator as a frequency standard in conjunction with frequency conversion circuitry to produce a drive signal at a suitable timekeeping rate. In assignees U.S. application Ser. No. 768,076, now U.S. Pat. No. 3,560,998 filed Oct. 16, 1968, there is disclosed a watch of this general type using low power complementary MOS circuits which have sufficiently low power dissipation and small size to be practical for use in a battery-powered wristwatch. The oscillatorfrequency converter combination of that application is described as suitable for driving conventional watch hands over a watch dial or, alternatively, for selectively actuating the display elements of an optical display in response to the drive signal output of the converter.

In assignees copending U.S. application Ser. No. 818,228, filed Apr. 22, 1969, now U.S. Pat. No. 3,576,099 there is disclosed an improved watch con struction in which the optical display takes the form of a plurality of light-emitting diodes which are intermittently energized on demand at the option of the wearer of the watch. This assures a minimum power consumption and an increasingly long life for the watch battery. An improved watch construction of this general type incorporating solid state circuits and integrated circuit techniques is disclosed in assignees copending U.S. application Ser. No. 35,196, filed May 6, 1970.

The present invention is directed to an improved watch construction of the same general type as disclosed in the above-mentioned applications and one which utilizes no moving parts to perform the timekeeping function. In the watch of the present invention, the timekeeping source takes the form of a nuclear timer in which the particles or energy emitted from a nuclear source, such as Radium 226, are counted and form the timekeeping standard of the watch.

Alpha particles emitted from the timing source pass through a collimator provided with adjustable shading to a solid state detector. In the detector, the alpha particles produce corresponding charges or electrons to an amplifier and discriminator. Through suitable adjustment of the collimator shading and appropriate adjustment of the discriminator level, electrical output signals are derived from the discriminator at an accurately controlled frequency corresponding to the rate of decay of the nuclear or radioisotope source.

These accurate high frequency electrical signals are applied through a low power CMOS frequency divider, through a logic circuit and a solid state driver for actuating an electro-optic time display. The time display is preferably formed by an array of solid state lightemitting diodes which present the hours, minutes and seconds of time in digital decimal form. The amplifierdiscriminator, frequency divider, logic circuit, driver and time display are all energized from a conventional battery power supply in the watch case. In order to further conserve the limited amount of energy available from the tiny watch battery, the wristwatch of the present invention preferably incorporates a demand switch so that the electro-optic display is energized from the battery only on demand, i.e., only when the demand switch is depressed by the wearer of the watch.

Additional features of the watch of the present invention include arrangements for setting the watch and the provision of a light sensor circuit for controlling the illumination of the display in accordance with ambient light conditions.

It is therefore one object of the present invention to provide an improved solid state wristwatch.

Another object of the present invention is to provide an improved timepiece having no moving parts and with sufficiently small size and power consumption for use as a wristwatch.

Another object of the present invention is to provide a wristwatch having a nuclear or radioisotope time base.

Another object of the present invention is to provide a solid state wristwatch in which the timing source takes the form of an alpha emitter, such as Radium 226 or the like.

Another object of the present invention is to provide a solid state wristwatch having improved shock re sistance and one that is less affected by temperature variations.

Another object of the present invention is to provide a solid state wristwatch having no moving parts and one in which the accuracy of the watch increases with use.

These and further objects and advantages of the invention will be more apparent upon reference to the following specification, claims, and appended drawings, wherein:

FIG. 1 is a perspective view of a conventional sized man's wristwatch constructed in accordance with the present invention;

FIG. 2 is a simplified block diagram showing the principal components of the wristwatch of FIG. 1;

FIG. 3 is a more detailed block diagram of the wristwatch of FIGS. 1 and 2 showing the details of the nuclear or radioisotope time base;

FIG. 4 shows a seven bar segment light-emitting diode array which may form a part of the wristwatch of FIGS. 1-3',

FIG. 5 is a simplified block diagram of a multistage frequency divider constructed in accordance with the present invention;

FIG. 6 is a detailed circuit diagram showing one of the stages of the frequency divider of FIG. 5;

FIGS. 7, 7A, and 7B, taken together, form a detailed block diagram of a nuclear-paced solid state watch constructed in accordance with the present invention as illustrated in FIG. 1', and

FIGS. 8, 8A, and 8B, taken together, show an integrated circuit display actuator for one of the optical display stations and forming a part of the wristwatch of FIG. 1.

Referring to the drawings, the novel watch of the present invention is generally indicated at 10 in FIG. 1. The watch is constructed to fit into a watch case 12 'of approximately the size of a conventional mans wristwatch. The case 12 is shown connected to a wristwatch strap 14 and includes a display window 16 through which time is displayed in digital form as indicated at 20'. Mounted on the case 12 is a pushbutton demand switch 18 by means of which the -display 20 may be actuated when the wearer of the wristwatch 10 desires to ascertain the time.

In normal operation, time is continuously being kept playing this time at any instant. When the wearer desires to ascertain the correct time, he depresses the pushbutton 18 with his finger and the correct time immediately is displayed at 20 through the window 16,

l which shows a dot display giving the correct time reading at 10:10, namely 10 minutes after 10 oclock. The hours and minutes, i.e., 10:10, are displayed through the window 16 for a predetermined length of time, preferably 1% seconds, irrespective of whether or not the pushbutton 18 remains depressed. The exact time of the display is chosen to give the wearer adequate time to consult the display to determine the hour and minute of time. Should the minutes change during the time of display, thischange is immediately indicated by advancement of the minute reading to the next number, i.e., eleven, as the watch is being read. If the pushbutton 18 remains depressed, at the end of 1% seconds the hours and minutes of the display are extinguished, i.e., they disappear and simultaneously the seconds reading is displayed through the window 16 immediately below the hours and minutes display 20. The advancing seconds cycling from O to 59 continue to be displayed through window 16 until the pushbutton switch 18 is released.

FIG. 2 is a simplified block diagram of the principal components of the watch 10 of FIG. 1. The watch comprises a time base or frequency standard 26 in the form of a radioisotope or decaying nuclear source, preferably adjusted to produce an electrical output signal on lead 28 at a frequency of 32,768 Hz. This relatively high frequency is supplied to a frequency converter 30 in the form of a divider which divides down the frequency from the'standard 26 so that the output from the converter 30 appearing on lead 32 is at a frequency of 1 Hz. This signal is applied to a display actuator 34 which in turn drives the display of the watch by way of electrical lead 36. While FIG. 2 shows both an hours and minutes display, i.e., 10:10, and a seconds display, i.e., 59, it is understood as previously described that these do not occur simultaneously, but, instead, the minutes are first displayed for a predetermined time and if the pushbutton remains depressed, the hours and minutes are extinguished and the seconds become visible. In this way, all elements of the display are not simultaneously actuated, thus minimizing th power drain from the watch battery.

FIG. 3 is a more detailed block diagram of the watch 10 of the present invention. The electrical output from source 26 by way of lead 28 is supplied to the frequency divider having a preset count input terminal 38.

Display actuator 34 is formed from a logic circuit 40 having a set/reset terminal 42 and a display driver 44. Time base 26, divider 30, logic circuit 40, driver 44, andthe light-emitting diode display 20 are all energized from a suitable power supply, such as a conventional 3 volt battery 46. The time display driver 44 and the display 20 are connected to battery 46 through the pushbutton demand switch 18 so that driver44 and the time display are only energized during those periods of time when the demand switch is depressed and closed.

Frequency standard 26, enclosed in the dashed box 50 in FIG. 3, comprises a radioisotope 52 which supplies energy through a gap or window 54 in a collimator 56 to a solid state detector 58. Detector 58' is connected by

leads

60 and 62 to the input of an amplifierdiscriminator 64 energized from battery 46 and supplying electrical output pulses to lead 28. Collimator 56 is preferably provided with an adjustable shutter 66 which may be adjusted by thumbscrew 68 to provide adjustable shading in window 54. In this way, the amount of energy passing through. the window from radioisotope source 52 to detector 58 is controlled by causing more or less of the window to be obstructed by the shutter 66.

In the preferred embodiment, radioisotope or nuclear source 52 takes the form of Radium 226, which is an alpha emitter having a half life of 1,622 years. In place of the Radium, other alpha emitters, such as Americium 241 having a half life of 458 years, or Plutonium 239 having a half life of 24,000 years, may be employed as the radioisotope source 52 in FIG. 3. In addition to alpha emiflers, it is possible to employ for the nuclear source a beta emitter, such as Carbon 14 having a half life of 5,760 years. However, in most instances, alpha emitters are preferred since most alpha source pulses are of an amplitude so that absorption of the entire energy of the particle occurs. A very small fraction of the pulses are distributed in energy near the zero pulse height. On the other hand, beta emitters provide a fairly even distribution of energy from zero to the full energy pulse height. As a result, this property of the beta emitters makes the calibration and discrimination problem more acute.

Detector 58 is preferably in the form of a P-N junction or a P-I-N junction, but may be of the surface barrier type or may be a solid volume ofsemiconductor material. It provides a volume of semiconductor material in which the excess charge generated in the semiconductor by the slowing down of an energetic charge particle from source 52 is collected to indicate the presence of the charged particle. Preferably an electric field from the battery 46 is applied through the amplifier-discriminator 64 across the active detector volume to sweep out the excess charge. In some instances, it is desirable to cover the detector with a thin.

gold foil to protect the detector against deterioration at high irradiation rates. Amplifier-discriminator 64 may take the form of a convention bipolar transistor in tegrated circuit amplifier with discrimination, but in the preferred embodiment comprises a relatively low noise integrated field effect transistor amplifier with discrimination. The discriminator threshold of the amplifier is preferably set well above any anticipated noise signals to eliminate spurious counts and to enhance the stability of the detector-amplifier system.

In the preferred embodiment, frequency converter 30 takes the form of a multistage divider illustrated in general block form in FIG. 5. The frequency converter includes a plurality of series connected binary divider stages formed from complementary-symmetry MOS (CMOS) transistors of which four stages are illustrated in FIG. 5. Each stage is provided with a pair of input terminals and a pair of output terminals. The input to first stage 71, indicated at F and F, are the outputs derived from the amplifier-discriminator 64 of FIG. 3. Correspondingly, the input to second stage 72 is provided by the outputs of first stage 71, denoted F and F This is continued for all remaining stages whereby the output of the M stage 74 provides outputs F and F to the N stage 76. Stage 76 provides an output F which constitutes the drive signal for the logic circuit 40 of FIG. 3.

Each of the stages in the frequency divider 30 serves to divide the input to that particular stage by 2. Thus, a succession of N stages provides division by 2". If the frequency of the output signal F N is to be 1 Hz, the frequency of the source 26 must be a power of 2 and the number of stages N are chosen in accordance with the relationship N log, F. By way of example only, with a frequency standard 26 operating at 32,768 Hz, the frequency divider 30 must have stages to achieve a drive frequency of 1 Hz.

In order to render a multistage counter arrangement practical for use in a battery-powered wristwatch, it has been foundnecessary to employ circuits having low power dissipation levels. In particular, the divider 30 is formed employing pairs of complementary voltagelevel sensitive transistors so arranged that transistors of opposite conductivity type serve mutually in load circuits for each other. With the complementary symmetry or CMOS, the circuit configuration is such that substantial current flow occurs only during state transitions.

FIG. 6 is a detailed circuit diagram of one of the divider stages employing integrated circuit CMOS transistors. The circuit comprises a first. transmission pair 78 including a P-channel transistor 80 and an N- channel transistor 82 connected source-to-source at 84 and drain-to-drain at 86. Gate 88 of P-channel transistor 80 is connected to the F input while gate 90 of N-channel transistor 82 is connected to the F input.

A second transmission pair 92 includes a P-channel transistor 94 and an N-channel transistor 96 coupled source-to-source at 98 and drain-to-drain at 101). Gate 102 of N-channel transistor 96 is connected to the F input while gate 104 of P-channel transistor 94 is connected to the Finput. Common source terminal 98 of transmission pair 92 is connected to common drain terminal 86 of transmission pair 78.

A first logic pair 106 is formed of a P-channel transistor 108 and an N-channel transistor 110, connected at a common gate terminal 112 and at common drain terminal 114. Common gate terminal 112 is connected to output 86 of transmission pair 78. A source terminal 116 of P-channel transistor 108 is connected to the power supply at 118 while a source terminal 120 of N-channel transistor 110 is connected to ground at 122.

A second logic pair 124 is formed of a P-channel transistor 126 and an N-channel transistor 128 connected at a common gate terminal 130 to common drain terminal 114 of logic pair 116 and also by a feedback path 132 to common drain terminal 134 to output terminal 100 of transmission pair 92. A source terminal 136 of P-channel transistor 126 is connected to power supply at 118 while a source terminal 138 of N-channel transistor 128 is connected to ground at 122.

The circuit of FIG. 6 also includes a second identical grouping of two transmission pairs 140 and 142 and logic pairs 144 and 146. Transmission pair 140 includes a P-channel transistor 148 and an N-channel transistor 150 connected source-to-source at 152 and drain-todrain at 154. Gate terminal 156 of P-channel transistor 148 is connected to input Fwhile gate terminal 158 of N-channel transistor 150 is connected to input F.

Transmission pair 142 includes a P-channel transistor 160 and an N-channel transistor 162 connected source-to-source at 164 and drain-todrain at 166. Gate 168 of P-channel transistor 160 is connected to input F while gate 170 of N-channel transistor 162 is connected to input F.

Logic pair 144 includes a P-channel transistor 172 and Nchannel transistor 174 having a common gate connection 176 and a common drain connection 178. Logic pair 146 includes a P-channel transistor 180 and an N-channel transistor 182 having a common gate terminal 184 and a common drain terminal 186. Terminals 188 and 190 of P-channel transistors 172 and 180 are connected to power supply at 1 18 while source terminals 192 and 194 of N-channel transistors 174 and 182 are connected to ground at 122. A circuit output F is provided at common drain terminal 178 of logic pair 144 while a second circuit output F, is provided at common drain terminal 186 of logic pair 146.

Common drain terminal 186 also provides a feedback connection 196 to terminal 164 of transmission gate 142 and a second feedback connection 198 coupled to terminal 84 of transmission gate 78. The substrate terminals for the various MOS transistors are not shown in the interest of clarity but it should be understood that in all cases the substrates of P-channel transistors are coupled to the power supply and the substrates of N-channel transistors are coupled to ground.

To understand the operation of the above-described circuit, it should be recalled that for P-channel depletion mode operation, a source-to-drain conductive path exists for low gate voltages. Increasing gate voltage reduces the conductivity ultimately turning the transistor off when sufficient gate voltage is attained. Conversely, for N-channel enhancement operation, a conductive path does not exist for small gate voltages but rather is established when the gate voltage exceeds a minimum positive gating threshold.

By way of example only, for transmission pair 78, a ONE input state at F and a ZERO input state at F'(high and low voltages, respectively) will maintain both transistors 80 and 82 in a non-conductive (OFF) state. Conversely, in transmission pair 140, both transistors 148 and 150 will be in the conductive (ON) state.

As to logic pair 106, a positive voltage at common gate terminal 112 exceeding the gating threshold will turn N-channel transistor 110 ON and P-channel transistor 108 OFF. This establishes common drain output terminal 114 at ground potential through conducting transistor 110. Conversely, a low voltage at common gate terminal 112 will turn P-channel transistor 108 ON and turn N-channel transistor 110 OFF, which establishes common drain terminal 114 at essentially the power supplypotential through conducting transistor 108.

For a detailed description of the mode of operation of the circuit of FIG. 6, reference may be had to the disclosure of assignees U.S. application Ser. No. 768,076, filed Oct. 16, 1968, the disclosure of which is incorporated herein by reference. To achieve the desired degree of frequency division, it is merely necessary to combine a series of stages as described in FIG. 6 into a chain as shown in FIG. 5. Even a moderately large number of stages are small enough for use in a wristwatch and consume a realistically small amount of power due to the complementary MOS construction.

While the watch illustrated in FIG. 1 employs a 27 dot matrix of light-emitting diodes for each display number, this need not be the case and the display may take the form of a' seven bar segment as disclosed in assignees copending application Ser. No. 818,228, filed Apr. 22, 1969. FIG. 4 shows seven light-emitting

diodes

390, 392, 394, 396, 398, 400, and 402 of elongated shape and arranged so that by lighting an appropriate combination of the bars any one of the numbers through 9 may be displayed. In certain applications, the seven bar segment display of FIG. 4 is preferred in that it requires less energy for the optical display than the 27 dot matrix shown in FIG. 1.

FIGS. 7, 7A, and 7B show an overall block diagram of the watch of the present invention. Watch comprises a nuclear or radioisotope time base which is adjusted to produce an output on lead 28, i.e., an electrical pulse train on that lead having a pulse repetition rate of 32,768 Hz. The time base output passes through a complementary symmetry MOS counter 30, which acts as a divider, dividing the output by 2", i.e., a seven stage counter, to produce an output on lead 202 having a pulse repetition rate of 256 Hz. This signal is divided by two in counter 204, by two again in counter 206, by eight (2 in counter 208, and by four (2) in counter 210.

An 8 Hz output on lead 212 from counter 208 is applied to a set-hold circuit 214 where the 8 Hz repetition rate pulse train appears as an output on lead 216. The 8 Hz signal on lead 216 is applied to a counter 218 where it is divided by eight (2 to produce a 1 Hz output pulse train on lead 220. The l I-Iz pulse train is divided by 10 in counter 222, divided by six in counter 224, divided by 10 again in counter 226, divided by six again in counter 228, and the output of this counter is finally applied to counter 230 which divides by 12. The output of counter 22 appearing on

leads

232, 234, 236, and 238 is-a binary coded decimal 1248 code which is applied to the decoder-driver 240 which, in turn, energizes the tens digits of the seconds display indicated at 242. The ones digits of the seconds display indicated at 244 are similarly actuated from counter 224 by way of seconds decodendriver 246. Similar decoder-

drivers

248, 250, and 252 actuate the tens digits of the minutes display at 254, the ones digits of the minutes display at 256, and the hours display at 258. Counter 230 has five output leads to decoder-driver 252 for a purpose more fully described below. The other decoder-

drivers

246, 248 and 250 are actuated by BCD 1248 codes from their

respective counters

224, 226, and 228 in the same manner as decoder-driver 240 is actuated from counter As previously stated, in order to conserve energy, the light-emitting diodes are only energized on demand, i.e., when the pushbutton 18 of FIG. 1 is depressed by the wearers finger. Even when the button is depressed by the wearer, the lights are not always continuously lit butinstead, in order to conserve power, are intermittently lighted during less than full daylight conditions at a frequency sufficiently high to give the appearance of continuity due to the light retention properties of the human eye. The pulses for intermittently lighting or pulsing the seconds display are derived from a display control driver 260 which applies the on-off pulses by way of lead 262 to the seconds decoder-

drivers

240 and 246. Similar intermittent pulses from the display control drivers 260 are applied by lead 264 to the minutes decoder-

drivers

248 and 250 and by lead 266 to the hours decoder-driver 252. The exact frequency at which the displays are turned on and off while always sufficiently high to give the impression to the human eye of continuous light is determined by a light control circuit 268 which supplies a light control signal by lead 270 to display control drivers 260. The light control signal is either DC (full daylight) or a combination of a 64 Hz signal supplied from counter 206 by way of lead 272, a 128 Hz signal supplied by counter 204 by way of lead 274, and a 256 Hz signal supplied from the output of counter 200 by way of lead 276. These signals are combined in the light control circuit 268 in a manner determined by the output signal on lead 278 to the light control circuit from ambient light sensors 280. These light sensors are in the form of three photo-transistors mounted on the watch display face and act to produce increased illumination from the light-emitting diodes during strong daylight conditions and less illumination from the diodes under nighttime or reduced light con- The watch face is ordinarily not illuminated. The hours and minutes diodes only light up when the demand switch is depressed. Actuation of the demand button 18 by the wearer causes the read switch 284 in FIG. 7B to close, causing the positive side of the power supply to be connected by way of

leads

286 and 288 to the display control drivers 260. Energization of these drivers permits passage through them of the signal from the light control circuit 268 which is passed on to the decoder-drivers causing the minutes and hours displays to be illuminated. No output from the display control diodes 260 appears on lead 262 at this time and the seconds displays are not illuminated. Closure of read switch 284 also applies B+ by way of lead 290 to sethold circuit 214 which immediately resets timer 292 by way of lead 294. Display timer 292 is a divide by counter and has applied to its input the 8 Hz pulse train on lead 212. This timer divides the 8 Hz by 10 and after 1% seconds produces an output pulse on lead 296 which is applied to display control driver 260. This pulse causes the display control driver to change state, removing the output from

leads

264 and 266 and causing the minutes and hours display to be extinguished. At the same time, the output is switched to lead 262 causing the seconds display to be illuminated simultaneously with the extinguishment of the hours and minutes display.

A feature of the watch of the present invention lies in the fact that the hours may be set independently of the minutes and seconds and at a very rapid rate. Closure of hours set switch 298, which is actuated from the back cover of the watch, grounds one input of an hours set circuit 300 by way of

leads

302 and 304. Hours set circuit 300 receives a 2 Hz pulse train from counter 210 by way of lead 306 and actuation of the hours set circuit by closure of hours set switch 298 causes the hours set circuit 300 to pass the 2 Hz signal on lead 306 I to counter 230 by way of lead 308. Hours set switch 298 is also connected to the display control drivers 260 to cause an output to appear on

leads

264 and 266 assuring that the hours and minutes are displayed when the hours are being reset during closure of switch 298. A minute set switch 312 is connected by

leads

314 and 316 to a minute set circuit 318. As before, actuation of this circuit causes it to pass a 2 Hz pulse Uain on lead 320 from counter 210 by way of lead 322 to the divide by 10 counter 226 driving the minutes display. Minute set switch 312 is likewise connected by lead 324 to display control drivers 260, again to insure an output on

leads

264 and 266 during resetting.

It is also a feature of the watch of the present invention that actuation of the minute set switch 312 automatically zeros the seconds display. The reason for this is that most time signals, such as those given over the radio and the like, are given on the hour or on the minute and in order to start the watch in synchronism with the correct time as given by such a signal, it is necessary that the seconds display be at zero at the time the radio tone or other time signal is heard. In order to accomplish this, the minute set switch 312 is connected by

leads

314 and 316 and a further lead 326 to set-hold circuit 214. Energization of this circuit from lead 326 produces an output pulse on output lead 328 which is applied to the reset terminals of

counters

218, 222, and 224 by way of

leads

330, 332, and 334, resetting these counters to zero and causing the seconds display to be automatically zeroed.

FIGS. 8, 8A, and 8B, taken together, is a detailed circuit diagram of a decoder-driver for actuating a seven bar segment display of the type illustrated in FIG. 4.

'More specifically, the circuit of FIGS. 8, 8A, and 8B shows a complete integrated circuit type programmable counter-decoder for actuating a seven segment display and may be used for the counters and decoderdrivers, i.e., elements such as the combined

elements

224 and 246 of FIG. 6. The circuit of FIGS. 8, 8A, and 8B is formed of allcomplementary MOS circuitry and may be fabricated on a single monolithic chip. The circuit is designed to be-universal, i.e., may be used for any of the displays in FIG. 6, either the hours, minutes or seconds, since the circuit of FIGS. 8, 8A and 8B is capable of counting from 0 to 12. Substitution of the circuit of FIGS. 8, 8A and 8B for the seconds unit counter 222 and the decoder-driver 240 necessitates a separate divide by 8 counter 218 for applying a 1 Hz input pulse train to the input terminal 403 of the counter-decoder 401 of FIG. 8. Input terminal 403 is connected through an inverter 404 to the input of flipflop 406. The output of flip-flop 406'is, in turn, connected through flip-

flop stages

408, 410, 412, 414, and a resetting flip-flop 416. Counter401 is provided with a pair of

power supply terminals

418 and 420, labeled A and B in FIG. 8, and an output terminal 422 (for supplying a carry out signal to the next counter), labeled C. Power supply terminals A and B are wired in accordance with the diagram of FIG. 8A, depending upon whether the counter is used to count up to 12, up to 10 (zero through nine), or up to six (zero through five). If the counter is used to indicate hours and to count to 12 (display numerals 1 through 12), then the terminals A and B are both connected to ground. If counter 401 is used for the minutes ones display, or the seconds ones display, then terminal A is connected to ground and terminal B is connected to the positive side of the power supply. If counter-decoder 401 is used for the minutes tens or seconds tens display, i.e., counting zero through five, then both terminals A and B are connected to the positive side of the power supply. A reset terminal 424 is used to apply an external reset signal to flip-flop 406. This terminal is only used to reset the seconds counter-decoder and is not used in the minutes and hours circuits.

The outputs from the various stages of the flip-flops are applied through NOR logic gates and inverters to a BCD to decimal decoding circuit, generally indicated at 442 and comprising NOR

gates

446, 448, 450, 452, 454, 456, 458, 460, and 462. The binary coded decimal output of the flip-flop stages is decoded in circuit 442 for application to the seven

diodes

390, 392, 394, 396, 398, 400, and 402 connected to respective terminals R through X (FIG. 8B). These diodes are connected through NOR

gates

464, 466, 468, 470, 472, 474, and 478, to the decoding circuit 442. An extra diode in the form of a long vertical bar is indicated at 480 and this The following is a description of the operation of the counter-decoder circuit of FIGS. 8, 8A and 8B and the signals to the bar segment diodes when the circuit of FIGS. 8, 8A and 8B is used to count to 12 (l-12), to 10 (-9, or to six (0-5).

The input signal (IN) at 403 passes through inverter 404 and drives 4 flip-flops FFl, FF2, FF3, FF4, which gives on their positive outputs Q1, Q2, Q3, Q4 3. binary coded decimal (BCD) number in accordance with the input signals and the internal function of the circuit. Counter to 12 The

FF

1, 2, 3, and 4 are a BCD counter. The NOR gate 507 will read the number 10 (2 2 from 62 and the output of the NOR gate 506 will work like an inverter (A =0) while the NOR gate 505, because of the inverter 4, has a permanent 0 output. Each time the binary number of the counter passes at 10 (2 2), the output of the NOR gate 507 is 1 and enters the NOR gate 508 (whose second input is 0 at that time) and through the inverter 509 which drives both FF 5 and 6. Then the positive outputs Q of t hese two flipflops are l and their negative outputs Q at 0." Now, gate 516 is able to read the number 3 (2 2 of the BCD counter when it next appears and the NOR gate 510 is able to pass the inverted input signal which will reset flip-flop 416 a half period later. In the meantime, F F6 resets the flip-

flops FF

2, 3, and 4, while FF 1 is already at zero.

Flip-flop 416 being reset, the circuit keeps running and at 13 (2 2 on FFl and FF2 and l on FFS), the NOR gate 516 shifts to l which, through the inverter 517, gives another 0" input in NOR gate 515 (B =0 which makes its output to be a l and through the NOR gate 508 and the inverter 509 drives theflipsflop FF5 which is now reset and FF6 whichresets FF2, 3, and 4 before it is reset itself by the inverted input signal through the NOR gate 510, and the counter keeps running from 1.

When the flip-flop FFS, at the number 10, shifts to 1, carry out (C) through the NOR gates 513 and 514 passes from 0 to l. C goes back to 0 when FFS is reset at 13. This is the pulse which must be used to drive the next stage (falling pulse).

Counter to To count to 10, B is connected to l Now, through the NOR gates and

inverter

482, 484 and 475, we have a permanent 0 on the output Y. The resetting pulse read by the NOR gate 516 can no longer pass through the NOR gate 515 whose output is 0. The counter runs as before and each time the NOR gate 507 reads l0 (2 2'), through the NOR gate 508 and the inverter 509, it shifts the flip-flops FPS and FF6. The output of FFS is stopped by the NOR

gates

513, 515 and 482, and FF6 will reset FF2, 3, and 4 before it is reset itself as already explained. When flip-flop FF6 is set, through the NOR gates 512 and 514, C passes from l to 0 (falling pulse). When FF6 is reset, C goes back to l. A next stage would be driven by the falling pulse.

Counter to 6 I To count to 6, connect A to l also. (A =B= I Now, the NOR gate 507 will read the number 6 (2 2') through the NOR gate 505 while the output of the NOR

gates

506 and 518 are 0. The output signal on C is the same as when counting by 10. It is assumed that the reset input at R 424 was at 0. HR at l all the flip-flops FFl, 2, 3, 4, and 5 are reset no matter how FF6 is. If FF6 was resetting,

FF

2, 3, and 4, when resetting the whole circuit, FF6 will be reset before FF 1 shifts for the second time (when it drives FF 2).

Q1, Q2, Q3, Q4, and OS are the positive outputs of the first five flip-flops as shown on the drawing and Q R is the output of the inverter 509. I BCD to Decimal Decoder The six flip-flops FFl-6 are able to count to 12 (one to l2), 10 (0-9), and six (0-5) providing a BCD output for the units a single digit when desired for the tens. It is necessary to decode this binary number in a seven segments display for the units. The ten is directly driven from terminal Y by the flip-flop FFS through the NOR gates and

inverters

482, 484, and 475.

Assuming the on-off input is at ON, that is to say at 0, knowing how the tens (Y works, consider the unit R, s, 'r, U, v, w, x only. The BCD output of the counter is always one of the following numbers and only these numbers as given in the following table:

TABLE R Number Q1 Q2 Q3 Q4 l O O O O 0 0 Q Q Q Q Rm v1 1 2 2 2 at 2 Q l g 0 l i Q 0 The underlined digits in the Table are the minimum digits which must be read in order to read the corresponding number and this one only. In the first part of the circuit, the NOR gates 446 through 462 are a BCD to decimal decoder whose outputs are 0 through 8 (9 is not decoded). As an example, the NOR gate 446 has its four inputs connected at Q1, Q2, Q3, and Q4. That is to say that when these four numbers are at 0 (Q1 Q2= Q3= Q4'=0= BCD number 0), the output of this NOR gate 446 is l Now, if one or several inputs of this gate are not at O, i.e., at 1, the output of the NOR gate 446 is 0. That is to say that the output D0 is 1 if and only ifits BCD input is 0; it is the same for each of the outputs D1, 2, 3, 7, and 8, which is 1, respectively, for their

BCD input

1, 2, 3, 7, and 8.

Decimal to 7 Segment Decoder With the seven segments of the display being R, S, T, U, V, W, and X, assume that the segments are ON all the time except when not lit with the exception for the segment V, which is turned ON when needed.

Consider the segment R, as an example. D1 and D4, through the NOR gate 464 will turn off R (R at .0") each time D1 or D4 are at 1. So the segment R is ON (R at l for any number except for 1 and 4. It is the same for T, U, S, W, X through the NOR

gates

476, 466, 468, 470, and 474 As far as V is concerned, the output of the NOR gate 472 is 0 when DO, 3, 6 or 8 are at .1. The NOR gate 478 reverses this signal so that V is at l for the

numbers

0, 3, 6, and 8.

When the ON-OFF input at 486 is at I, through the NOR

gates

464, 476, 466, 468, 470, 478, 474, and

475, all the outputs R, T, U, S, W, V, X, and Y are at no matter how the counter-decoder is. This input is responsive to operation of the demand switch 18 and is used to turn off the display although the logic infonnation is saved and the counter still working.

A particular advantage of the circuit shown in FIGS. 8, 8A, and 8B, usable in conjunction with the 7 bar segment display of FIG. 4, and with the MOS complementary integrated circuit divider 30, is that the monolithic signal chip circuit of FIGS. 8, 8A, and 8B minimizes the circuit necessary and makes it possible to construct the watch utilizing a conventional 3 volt power supply. That is, the monolithic chip circuit of FIGS. 8, 8A and 8B is a universal circuit and only five are required, namely, one for the hours display, two for the minutes display (counting 6 and 10), and two for the seconds display (also counting 6 and 10).

For a more detailed showing and description of the operation of the circuit of FIGS. 8, 8A and 8B, reference may be had to assignees copending US. application Ser. No. 35,196, filed May 6, 1970, the disclosure of which is incorporated herein by reference.

It is apparent from the above that the present invention provides an improved wristwatch construction and particularly a construction which has as an important feature a completely solid state assembly requiring no moving parts forperforming the timekeeping function and displaying it. In the preferred embodiment, the display takes the form of a plurality of conventional lightemitting diodes, preferably gallium arsenide phosphide operating at a wavelength of approximately 6,500 Angstroms. Alternatively, the display may be formed from liquid crystal material rather than light-emitting diodes in a well-known manner, so that the liquid crystals scatter light when energized by the electric field.

An important feature of the present invention is the incorporation of a nuclear or radioisotope material which decays at a substantially constant rate and whose particles or energy emissions of decay may be counted to provide an accurate indication of the passage of time. In the preferred embodiment, the nuclear material is an alpha emitter and, by way of example only, may be formed of Radium 226. By adjusting either the variable shading or the setting of the limit value in the electrical circuit, or both, it is possible to adjust the output of the frequency standard or time base to the desired frequency, namely, 32,786 Hz (to the appropriate power of 2 consistent with the number of binary stages in the divider). The wristwatch of the present invention has improved shock insensitivity, lower cost, lower power consumption, and is less affected by thermal variations. Because of the nuclear source, it may be made smaller in size and therefore is suitable for use in lady's wristwatch. A further important feature is that the timepiece is such that its accuracy increases with use. This is because the percentage timing error of the combined system decreases with increased operating time.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore intended to be considered in all respects as illustrative and not restrictive, the scope'of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

What is claimed and desired to be secured by United States Letters patent is:

1. A nuclear-powered timekeeping device of sufficiently small size for use as a wristwatch comprising a source of radiant energy impulses of substantially constant frequency, a solid state detector adjacent said source for converting energy from said source into electrical impulses, a binary chain of CMOS divider stages coupled to said detector for reducing the frequency of said electrical impulses, a digital time display comprising a plurality of electro-optical elements, and a binary logic circuit coupling said divider to said display elements for selectively energizing said elements in accordance with the output of said divider.

2. A timekeeping device according to claim 1 wherein said logic circuit comprises a plurality of additional CMOS dividers for further reducing the frequency of said electrical impulses to display time in minutes and hours.

3. A timekeeping device according to claim 2 wherein said logic circuit comprises a plurality of gates for selectively energizing said display elements.

4. A timekeeping device according to claim 3 wherein said logic circuit comprises a binary coded decimal to display converter for converting binary coded decimal signals into drive signals for said display elements.

5. A timekeeping device according to claim 4 wherein said display elements are arranged to form a seven-bar segment display and said logic circuit comprises a binary coded decimal to seven-bar segment converter.

6. A timekeeping device according to claim 1 wherein said radiant energy source comprises an alpha emitter, and variable shading means positioned between said emitter and said detector.

7. A timekeeping device according to claim 6 wherein said emitter comprises Radium 226.

8. A. timekeeping device according to claim 6 wherein said emitter comprisesAmericium 241.

9. A timekeeping device according to claim 6 wherein said emitter comprises Plutonium 239.

10. A timekeeping device according to claim 1 wherein said electro-optical elements comprise a plurality of arrays of light-emitting diodes.

11. A timekeeping device according to claim 1 wherein said electro-optical elements comprise a plurality of arrays of liquid crystals.

12. A nuclear-paced time keeping device of sufficiently small size for use as a wristwatch comprising a radioactive alpha emitter, a solid state PN junction detector adjacent said emitter for converting energy from said source into electrical impulses, a collimator with adjustable shading for directing energy from said emitter to said detector, an amplifier and discriminator coupled to said detector, a frequency divider coupled to said detector through said amplifier and discriminator, a logic circuit coupled to the output of said divider, a digital electro-optical time display, a driver coupling said logic circuit to said digital display, a battery, and a manually operated demand switch coupling said battery to said digital display.

- reset terminal for adjusting the time displayed.

Claims

8. A timekeeping device according to claim 6 wherein said emitter comprises Americium 241.

13. A timekeeping device according to claim 12 wherein said frequency divider is provided with a preset count terminal for presetting the count of said divider.

14. A timekeeping device according to claim 13 wherein said logic circuit is provided with a set and reset terminal for adjusting the time displayed.